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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
25 #clock-cells = <0>;
[all …]
H A Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 atl_clkin0_ck: clock-atl-clkin0 {
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
11 clock-output-names = "atl_clkin0_ck";
15 atl_clkin1_ck: clock-atl-clkin1 {
16 #clock-cells = <0>;
17 compatible = "ti,dra7-atl-clock";
18 clock-output-names = "atl_clkin1_ck";
22 atl_clkin2_ck: clock-atl-clkin2 {
[all …]
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
[all …]
H A Ddm816x-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #clock-cells = <1>;
6 compatible = "ti,dm816-fapll-clock";
9 clock-indices = <1>, <2>, <3>, <4>, <5>,
11 clock-output-names = "main_pll_clk1",
21 #clock-cells = <1>;
22 compatible = "ti,dm816-fapll-clock";
25 clock-indices = <1>, <2>, <3>, <4>;
26 clock-output-names = "ddr_pll_clk1",
33 #clock-cells = <1>;
[all …]
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
[all …]
H A Dam33xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <22>;
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
20 clock-output-names = "adc_tsc_fck";
[all …]
H A Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
26 ti,max-div = <3>;
[all …]
H A Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
31 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dkeystone-pll.txt2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
23 #clock-cells = <0>;
[all …]
H A Daltr_socfpga.txt5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
18 - #clock-cells : from common clock binding, shall be set to 0.
21 - fixed-divider : If clocks have a fixed divider value, use this property.
22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
36 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
52 * divided by the divider controlled by ACLK_CLK_DIVISOR in
56 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */
60 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */
62 /** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */
64 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */
81 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */
83 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */
[all …]
H A Dtegra186-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
362 /** @brief output of the divider IPFS_CLK_DIVISOR */
551 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
555 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
563 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
565 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
567 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
693 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
697 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
699 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
[all …]
H A Dhi6220-clock.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 /* fixed rate clocks */
29 /* fixed factor clocks */
114 /* divider clocks */
150 /* divider clocks */
169 /* divider clocks */
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dlltc,ltc3676.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Linear Technology LTC3676 8-output regulators
10 - Tim Harvey <tharvey@gateworks.com>
30 after their hardware counterparts (SW|LDO)[1-4].
33 "^(sw[1-4]|ldo[24])$":
42 Regulators LDO1, LDO2, LDO4 have a fixed 0.725 V reference and thus
45 the regulator-always-on property set.
48 lltc,fb-voltage-divider:
[all …]
H A Dltc3676.txt1 Linear Technology LTC3676 8-output regulators
4 - compatible: "lltc,ltc3676"
5 - reg: I2C slave address
8 - regulators: Contains eight regulator child nodes sw1, sw2, sw3, sw4,
17 - lltc,fb-voltage-divider: An array of two integers containing the resistor
18 values R1 and R2 of the feedback voltage divider in ohms.
24 Regulators ldo1, ldo2, and ldo4 have a fixed 0.725 V reference and thus output
25 0.725 * (1 + R1/R2) V. The ldo3 regulator is fixed to 1.8 V. The ldo1 standby
26 regulator can not be disabled and thus should have the regulator-always-on
37 regulator-min-microvolt = <674400>;
[all …]
H A Dltc3589.txt1 Linear Technology LTC3589, LTC3589-1, and LTC3589-2 8-output regulators
4 - compatible: "lltc,ltc3589", "lltc,ltc3589-1" or "lltc,ltc3589-2"
5 - reg: I2C slave address
8 - regulators: Contains eight regulator child nodes sw1, sw2, sw3, bb-out,
13 nodes for sw1, sw2, sw3, bb-out, ldo1, and ldo2 additionally need to specify
17 - lltc,fb-voltage-divider: An array of two integers containing the resistor
18 values R1 and R2 of the feedback voltage divider in ohms.
22 0.3625 * (1 + R1/R2) V and 0.75 * (1 + R1/R2) V. Regulators bb-out and ldo1
23 have a fixed 0.8 V reference and thus output 0.8 * (1 + R1/R2) V. The ldo3
24 regulator is fixed to 1.8 V on LTC3589 and to 2.8 V on LTC3589-1,2. The ldo4
[all …]
/freebsd/sys/dev/clk/rockchip/
H A Drk_cru.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
59 /* Fixed rate clock. */
63 .clk.fixed = &(struct clk_fixed_def) { \
73 /* Fixed factor multipier/divider. */
77 .clk.fixed = &(struct clk_fixed_def) { \
123 /* Fractional rate multipier/divider. */
157 /* Composite clock without mux (divider only). */
174 /* Complex clock without divider (multiplexer only). */
194 /* Complex clock without divider (multiplexer only in GRF). */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dti,fixed-factor-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI fixed factor rate clock sources
10 - Tero Kristo <kristo@kernel.org>
11 - Sukrut Bellary <sbellary@baylibre.com>
14 This consists of a divider and a multiplier used to generate a fixed rate
18 - $ref: ti,autoidle.yaml#
22 const: ti,fixed-factor-clock
[all …]
H A Dautoidle.txt6 clock, it is always a derivative of some basic clock like a gate, divider,
7 or fixed-factor.
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - reg : offset for the register controlling the autoidle
13 - ti,autoidle-shift : bit shift of the autoidle enable bit
14 - ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
18 #clock-cells = <0>;
19 compatible = "ti,divider-clock";
21 ti,max-div = <31>;
22 ti,autoidle-shift = <8>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi_oc_tiny.txt4 - compatible : should be "opencores,tiny-spi-rtlsvn2".
5 - gpios : should specify GPIOs used for chipselect.
7 - clock-frequency : input clock frequency to the core.
8 - baud-width: width, in bits, of the programmable divider used to scale
11 The clock-frequency and baud-width properties are needed only if the divider
12 is programmable. They are not needed if the divider is fixed.
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dqcom,ipq4019-mdio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ipq4019-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Marko <robert.marko@sartura.hr>
15 - enum:
16 - qcom,ipq4019-mdio
17 - qcom,ipq5018-mdio
19 - items:
20 - enum:
[all …]
/freebsd/sys/dev/clk/
H A Dclk_fixed.h1 /*-
33 * A fixed clock can represent several different real-world objects, including
34 * an oscillator with a fixed output frequency, a fixed divider (multiplier and
35 * divisor must both be > 0), or a phase-fractional divider within a PLL
/freebsd/sys/arm/mv/clk/
H A Dperiph.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
231 .clk_def.mux_gate.fixed.clkdef.name = _fixed_name \
262 .clk_def.fixed.mux.clkdef.name = _mux_name, \
263 .clk_def.fixed.mux.offset = TBG_SEL, \
264 .clk_def.fixed.mux.shift = _mux_shift, \
265 .clk_def.fixed.mux.width = 0x1, \
266 .clk_def.fixed.mux.mux_flags = 0x0, \
267 .clk_def.fixed.gate.clkdef.name = _name, \
268 .clk_def.fixed.gate.offset = CLK_DIS, \
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3588-jaguar-pre-ict-tester.dtso1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
5 * Device Tree Overlay for the Pre-ICT tester adapter for the Mezzanine
8 * This adapter has a PCIe Gen2 x1 M.2 M-Key connector and two proprietary
10 * as 2-lane CSI).
19 /dts-v1/;
22 #include <dt-bindings/gpio/gpio.h>
23 #include <dt-bindings/pinctrl/rockchip.h>
26 pre_ict_tester_vcc_1v2: regulator-pre-ict-tester-vcc-1v2 {
27 compatible = "regulator-fixed";
28 regulator-name = "pre_ict_tester_vcc_1v2";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl-gw552x.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
25 gpio-keys {
26 compatible = "gpio-keys";
28 user-pb {
34 user-pb1x {
37 interrupt-parent = <&gsc>;
41 key-erased {
[all …]

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