Lines Matching +full:fixed +full:- +full:divider
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
231 .clk_def.mux_gate.fixed.clkdef.name = _fixed_name \
262 .clk_def.fixed.mux.clkdef.name = _mux_name, \
263 .clk_def.fixed.mux.offset = TBG_SEL, \
264 .clk_def.fixed.mux.shift = _mux_shift, \
265 .clk_def.fixed.mux.width = 0x1, \
266 .clk_def.fixed.mux.mux_flags = 0x0, \
267 .clk_def.fixed.gate.clkdef.name = _name, \
268 .clk_def.fixed.gate.offset = CLK_DIS, \
269 .clk_def.fixed.gate.shift = _gate_shift, \
270 .clk_def.fixed.gate.on_value = 0, \
271 .clk_def.fixed.gate.off_value = 1, \
272 .clk_def.fixed.gate.mask = 0x1, \
273 .clk_def.fixed.gate.gate_flags = 0x0, \
274 .clk_def.fixed.fixed.clkdef.name = _fixed_name \
309 struct clk_fixed_def fixed; member
331 struct clk_fixed_def fixed; member
343 /* Double divider clock */
345 /* Single divider clock */
353 /* Clock with fixed frequency divider */
355 /* Clock with double divider, without gate */
357 /* Clock with two fixed frequency dividers */
376 struct a37x0_periph_clk_fixed_def fixed; member