1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sm8650-camcc.h> 9#include <dt-bindings/clock/qcom,sm8650-dispcc.h> 10#include <dt-bindings/clock/qcom,sm8650-gcc.h> 11#include <dt-bindings/clock/qcom,sm8650-gpucc.h> 12#include <dt-bindings/clock/qcom,sm8650-tcsr.h> 13#include <dt-bindings/clock/qcom,sm8650-videocc.h> 14#include <dt-bindings/dma/qcom-gpi.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,icc.h> 18#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> 19#include <dt-bindings/interconnect/qcom,osm-l3.h> 20#include <dt-bindings/interrupt-controller/arm-gic.h> 21#include <dt-bindings/mailbox/qcom-ipcc.h> 22#include <dt-bindings/phy/phy-qcom-qmp.h> 23#include <dt-bindings/power/qcom,rpmhpd.h> 24#include <dt-bindings/power/qcom-rpmpd.h> 25#include <dt-bindings/reset/qcom,sm8650-gpucc.h> 26#include <dt-bindings/soc/qcom,gpr.h> 27#include <dt-bindings/soc/qcom,rpmh-rsc.h> 28#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 29#include <dt-bindings/thermal/thermal.h> 30 31/ { 32 interrupt-parent = <&intc>; 33 34 #address-cells = <2>; 35 #size-cells = <2>; 36 37 chosen { }; 38 39 clocks { 40 xo_board: xo-board { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 }; 44 45 sleep_clk: sleep-clk { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 }; 49 50 bi_tcxo_div2: bi-tcxo-div2-clk { 51 compatible = "fixed-factor-clock"; 52 #clock-cells = <0>; 53 54 clocks = <&rpmhcc RPMH_CXO_CLK>; 55 clock-mult = <1>; 56 clock-div = <2>; 57 }; 58 59 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 60 compatible = "fixed-factor-clock"; 61 #clock-cells = <0>; 62 63 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 64 clock-mult = <1>; 65 clock-div = <2>; 66 }; 67 }; 68 69 cpus { 70 #address-cells = <2>; 71 #size-cells = <0>; 72 73 cpu0: cpu@0 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a520"; 76 reg = <0 0>; 77 78 i-cache-size = <65536>; 79 i-cache-line-size = <64>; 80 d-cache-size = <65536>; 81 d-cache-line-size = <64>; 82 83 clocks = <&cpufreq_hw 0>; 84 85 power-domains = <&cpu_pd0>; 86 power-domain-names = "psci"; 87 88 enable-method = "psci"; 89 next-level-cache = <&l2_0>; 90 capacity-dmips-mhz = <1024>; 91 dynamic-power-coefficient = <100>; 92 93 qcom,freq-domain = <&cpufreq_hw 0>; 94 95 operating-points-v2 = <&cpu0_opp_table>; 96 97 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 98 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 99 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 100 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 101 <&epss_l3 MASTER_EPSS_L3_APPS 102 &epss_l3 SLAVE_EPSS_L3_SHARED>; 103 104 #cooling-cells = <2>; 105 106 l2_0: l2-cache { 107 compatible = "cache"; 108 cache-level = <2>; 109 cache-unified; 110 next-level-cache = <&l3_0>; 111 cache-size = <524288>; 112 cache-line-size = <64>; 113 114 l3_0: l3-cache { 115 compatible = "cache"; 116 cache-level = <3>; 117 cache-unified; 118 cache-size = <12582912>; 119 cache-line-size = <64>; 120 }; 121 }; 122 }; 123 124 cpu1: cpu@100 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a520"; 127 reg = <0 0x100>; 128 129 i-cache-size = <65536>; 130 i-cache-line-size = <64>; 131 d-cache-size = <65536>; 132 d-cache-line-size = <64>; 133 134 clocks = <&cpufreq_hw 0>; 135 136 power-domains = <&cpu_pd1>; 137 power-domain-names = "psci"; 138 139 enable-method = "psci"; 140 next-level-cache = <&l2_0>; 141 capacity-dmips-mhz = <1024>; 142 dynamic-power-coefficient = <100>; 143 144 qcom,freq-domain = <&cpufreq_hw 0>; 145 146 operating-points-v2 = <&cpu0_opp_table>; 147 148 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 149 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 150 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 151 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 152 <&epss_l3 MASTER_EPSS_L3_APPS 153 &epss_l3 SLAVE_EPSS_L3_SHARED>; 154 155 #cooling-cells = <2>; 156 }; 157 158 cpu2: cpu@200 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a720"; 161 reg = <0 0x200>; 162 163 i-cache-size = <65536>; 164 i-cache-line-size = <64>; 165 d-cache-size = <65536>; 166 d-cache-line-size = <64>; 167 168 clocks = <&cpufreq_hw 3>; 169 170 power-domains = <&cpu_pd2>; 171 power-domain-names = "psci"; 172 173 enable-method = "psci"; 174 next-level-cache = <&l2_200>; 175 capacity-dmips-mhz = <2909>; 176 dynamic-power-coefficient = <238>; 177 178 qcom,freq-domain = <&cpufreq_hw 3>; 179 180 operating-points-v2 = <&cpu2_opp_table>; 181 182 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 183 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 184 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 185 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 186 <&epss_l3 MASTER_EPSS_L3_APPS 187 &epss_l3 SLAVE_EPSS_L3_SHARED>; 188 189 #cooling-cells = <2>; 190 191 l2_200: l2-cache { 192 compatible = "cache"; 193 cache-level = <2>; 194 cache-unified; 195 next-level-cache = <&l3_0>; 196 cache-size = <524288>; 197 cache-line-size = <64>; 198 }; 199 }; 200 201 cpu3: cpu@300 { 202 device_type = "cpu"; 203 compatible = "arm,cortex-a720"; 204 reg = <0 0x300>; 205 206 i-cache-size = <65536>; 207 i-cache-line-size = <64>; 208 d-cache-size = <65536>; 209 d-cache-line-size = <64>; 210 211 clocks = <&cpufreq_hw 3>; 212 213 power-domains = <&cpu_pd3>; 214 power-domain-names = "psci"; 215 216 enable-method = "psci"; 217 next-level-cache = <&l2_300>; 218 capacity-dmips-mhz = <2909>; 219 dynamic-power-coefficient = <238>; 220 221 qcom,freq-domain = <&cpufreq_hw 3>; 222 223 operating-points-v2 = <&cpu2_opp_table>; 224 225 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 226 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 227 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 228 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 229 <&epss_l3 MASTER_EPSS_L3_APPS 230 &epss_l3 SLAVE_EPSS_L3_SHARED>; 231 232 #cooling-cells = <2>; 233 234 l2_300: l2-cache { 235 compatible = "cache"; 236 cache-level = <2>; 237 cache-unified; 238 next-level-cache = <&l3_0>; 239 cache-size = <524288>; 240 cache-line-size = <64>; 241 }; 242 }; 243 244 cpu4: cpu@400 { 245 device_type = "cpu"; 246 compatible = "arm,cortex-a720"; 247 reg = <0 0x400>; 248 249 i-cache-size = <65536>; 250 i-cache-line-size = <64>; 251 d-cache-size = <65536>; 252 d-cache-line-size = <64>; 253 254 clocks = <&cpufreq_hw 3>; 255 256 power-domains = <&cpu_pd4>; 257 power-domain-names = "psci"; 258 259 enable-method = "psci"; 260 next-level-cache = <&l2_400>; 261 capacity-dmips-mhz = <2909>; 262 dynamic-power-coefficient = <238>; 263 264 qcom,freq-domain = <&cpufreq_hw 3>; 265 266 operating-points-v2 = <&cpu2_opp_table>; 267 268 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 269 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 270 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 271 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 272 <&epss_l3 MASTER_EPSS_L3_APPS 273 &epss_l3 SLAVE_EPSS_L3_SHARED>; 274 275 #cooling-cells = <2>; 276 277 l2_400: l2-cache { 278 compatible = "cache"; 279 cache-level = <2>; 280 cache-unified; 281 next-level-cache = <&l3_0>; 282 cache-size = <524288>; 283 cache-line-size = <64>; 284 }; 285 }; 286 287 cpu5: cpu@500 { 288 device_type = "cpu"; 289 compatible = "arm,cortex-a720"; 290 reg = <0 0x500>; 291 292 i-cache-size = <65536>; 293 i-cache-line-size = <64>; 294 d-cache-size = <65536>; 295 d-cache-line-size = <64>; 296 297 clocks = <&cpufreq_hw 1>; 298 299 power-domains = <&cpu_pd5>; 300 power-domain-names = "psci"; 301 302 enable-method = "psci"; 303 next-level-cache = <&l2_500>; 304 capacity-dmips-mhz = <2909>; 305 dynamic-power-coefficient = <238>; 306 307 qcom,freq-domain = <&cpufreq_hw 1>; 308 309 operating-points-v2 = <&cpu5_opp_table>; 310 311 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 312 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 313 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 314 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 315 <&epss_l3 MASTER_EPSS_L3_APPS 316 &epss_l3 SLAVE_EPSS_L3_SHARED>; 317 318 #cooling-cells = <2>; 319 320 l2_500: l2-cache { 321 compatible = "cache"; 322 cache-level = <2>; 323 cache-unified; 324 next-level-cache = <&l3_0>; 325 cache-size = <524288>; 326 cache-line-size = <64>; 327 }; 328 }; 329 330 cpu6: cpu@600 { 331 device_type = "cpu"; 332 compatible = "arm,cortex-a720"; 333 reg = <0 0x600>; 334 335 i-cache-size = <65536>; 336 i-cache-line-size = <64>; 337 d-cache-size = <65536>; 338 d-cache-line-size = <64>; 339 340 clocks = <&cpufreq_hw 1>; 341 342 power-domains = <&cpu_pd6>; 343 power-domain-names = "psci"; 344 345 enable-method = "psci"; 346 next-level-cache = <&l2_600>; 347 capacity-dmips-mhz = <2909>; 348 dynamic-power-coefficient = <238>; 349 350 qcom,freq-domain = <&cpufreq_hw 1>; 351 352 operating-points-v2 = <&cpu5_opp_table>; 353 354 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 355 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 356 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 357 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 358 <&epss_l3 MASTER_EPSS_L3_APPS 359 &epss_l3 SLAVE_EPSS_L3_SHARED>; 360 361 #cooling-cells = <2>; 362 363 l2_600: l2-cache { 364 compatible = "cache"; 365 cache-level = <2>; 366 cache-unified; 367 next-level-cache = <&l3_0>; 368 cache-size = <524288>; 369 cache-line-size = <64>; 370 }; 371 }; 372 373 cpu7: cpu@700 { 374 device_type = "cpu"; 375 compatible = "arm,cortex-x4"; 376 reg = <0 0x700>; 377 378 i-cache-size = <65536>; 379 i-cache-line-size = <64>; 380 d-cache-size = <65536>; 381 d-cache-line-size = <64>; 382 383 clocks = <&cpufreq_hw 2>; 384 385 power-domains = <&cpu_pd7>; 386 power-domain-names = "psci"; 387 388 enable-method = "psci"; 389 next-level-cache = <&l2_700>; 390 capacity-dmips-mhz = <3591>; 391 dynamic-power-coefficient = <588>; 392 393 qcom,freq-domain = <&cpufreq_hw 2>; 394 395 operating-points-v2 = <&cpu7_opp_table>; 396 397 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 398 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 399 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 400 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 401 <&epss_l3 MASTER_EPSS_L3_APPS 402 &epss_l3 SLAVE_EPSS_L3_SHARED>; 403 404 #cooling-cells = <2>; 405 406 l2_700: l2-cache { 407 compatible = "cache"; 408 cache-level = <2>; 409 cache-unified; 410 next-level-cache = <&l3_0>; 411 cache-size = <2097152>; 412 cache-line-size = <64>; 413 }; 414 }; 415 416 cpu-map { 417 cluster0 { 418 core0 { 419 cpu = <&cpu0>; 420 }; 421 422 core1 { 423 cpu = <&cpu1>; 424 }; 425 426 core2 { 427 cpu = <&cpu2>; 428 }; 429 430 core3 { 431 cpu = <&cpu3>; 432 }; 433 434 core4 { 435 cpu = <&cpu4>; 436 }; 437 438 core5 { 439 cpu = <&cpu5>; 440 }; 441 442 core6 { 443 cpu = <&cpu6>; 444 }; 445 446 core7 { 447 cpu = <&cpu7>; 448 }; 449 }; 450 }; 451 452 idle-states { 453 entry-method = "psci"; 454 455 silver_cpu_sleep_0: cpu-sleep-0-0 { 456 compatible = "arm,idle-state"; 457 idle-state-name = "silver-rail-power-collapse"; 458 arm,psci-suspend-param = <0x40000004>; 459 entry-latency-us = <550>; 460 exit-latency-us = <750>; 461 min-residency-us = <6700>; 462 local-timer-stop; 463 }; 464 465 gold_cpu_sleep_0: cpu-sleep-1-0 { 466 compatible = "arm,idle-state"; 467 idle-state-name = "gold-rail-power-collapse"; 468 arm,psci-suspend-param = <0x40000004>; 469 entry-latency-us = <600>; 470 exit-latency-us = <1300>; 471 min-residency-us = <8136>; 472 local-timer-stop; 473 }; 474 475 gold_plus_cpu_sleep_0: cpu-sleep-2-0 { 476 compatible = "arm,idle-state"; 477 idle-state-name = "gold-plus-rail-power-collapse"; 478 arm,psci-suspend-param = <0x40000004>; 479 entry-latency-us = <500>; 480 exit-latency-us = <1350>; 481 min-residency-us = <7480>; 482 local-timer-stop; 483 }; 484 }; 485 486 domain-idle-states { 487 cluster_sleep_0: cluster-sleep-0 { 488 compatible = "domain-idle-state"; 489 arm,psci-suspend-param = <0x41000044>; 490 entry-latency-us = <750>; 491 exit-latency-us = <2350>; 492 min-residency-us = <9144>; 493 }; 494 495 cluster_sleep_1: cluster-sleep-1 { 496 compatible = "domain-idle-state"; 497 arm,psci-suspend-param = <0x4100c344>; 498 entry-latency-us = <2800>; 499 exit-latency-us = <4400>; 500 min-residency-us = <10150>; 501 }; 502 }; 503 }; 504 505 ete-0 { 506 compatible = "arm,embedded-trace-extension"; 507 508 cpu = <&cpu0>; 509 510 out-ports { 511 port { 512 ete0_out_funnel_ete: endpoint { 513 remote-endpoint = <&funnel_ete_in_ete0>; 514 }; 515 }; 516 }; 517 }; 518 519 ete-1 { 520 compatible = "arm,embedded-trace-extension"; 521 522 cpu = <&cpu1>; 523 524 out-ports { 525 port { 526 ete1_out_funnel_ete: endpoint { 527 remote-endpoint = <&funnel_ete_in_ete1>; 528 }; 529 }; 530 }; 531 }; 532 533 ete-2 { 534 compatible = "arm,embedded-trace-extension"; 535 536 cpu = <&cpu2>; 537 538 out-ports { 539 port { 540 ete2_out_funnel_ete: endpoint { 541 remote-endpoint = <&funnel_ete_in_ete2>; 542 }; 543 }; 544 }; 545 }; 546 547 ete-3 { 548 compatible = "arm,embedded-trace-extension"; 549 550 cpu = <&cpu3>; 551 552 out-ports { 553 port { 554 ete3_out_funnel_ete: endpoint { 555 remote-endpoint = <&funnel_ete_in_ete3>; 556 }; 557 }; 558 }; 559 }; 560 561 ete-4 { 562 compatible = "arm,embedded-trace-extension"; 563 564 cpu = <&cpu4>; 565 566 out-ports { 567 port { 568 ete4_out_funnel_ete: endpoint { 569 remote-endpoint = <&funnel_ete_in_ete4>; 570 }; 571 }; 572 }; 573 }; 574 575 ete-5 { 576 compatible = "arm,embedded-trace-extension"; 577 578 cpu = <&cpu5>; 579 580 out-ports { 581 port { 582 ete5_out_funnel_ete: endpoint { 583 remote-endpoint = <&funnel_ete_in_ete5>; 584 }; 585 }; 586 }; 587 }; 588 589 ete-6 { 590 compatible = "arm,embedded-trace-extension"; 591 592 cpu = <&cpu6>; 593 594 out-ports { 595 port { 596 ete6_out_funnel_ete: endpoint { 597 remote-endpoint = <&funnel_ete_in_ete6>; 598 }; 599 }; 600 }; 601 }; 602 603 ete-7 { 604 compatible = "arm,embedded-trace-extension"; 605 606 cpu = <&cpu7>; 607 608 out-ports { 609 port { 610 ete7_out_funnel_ete: endpoint { 611 remote-endpoint = <&funnel_ete_in_ete7>; 612 }; 613 }; 614 }; 615 }; 616 617 funnel-ete { 618 compatible = "arm,coresight-static-funnel"; 619 620 in-ports { 621 #address-cells = <1>; 622 #size-cells = <0>; 623 624 port@0 { 625 reg = <0>; 626 627 funnel_ete_in_ete0: endpoint { 628 remote-endpoint = <&ete0_out_funnel_ete>; 629 }; 630 }; 631 632 port@1 { 633 reg = <1>; 634 635 funnel_ete_in_ete1: endpoint { 636 remote-endpoint = <&ete1_out_funnel_ete>; 637 }; 638 }; 639 640 port@2 { 641 reg = <2>; 642 643 funnel_ete_in_ete2: endpoint { 644 remote-endpoint = <&ete2_out_funnel_ete>; 645 }; 646 }; 647 648 port@3 { 649 reg = <3>; 650 651 funnel_ete_in_ete3: endpoint { 652 remote-endpoint = <&ete3_out_funnel_ete>; 653 }; 654 }; 655 656 port@4 { 657 reg = <4>; 658 659 funnel_ete_in_ete4: endpoint { 660 remote-endpoint = <&ete4_out_funnel_ete>; 661 }; 662 }; 663 664 port@5 { 665 reg = <5>; 666 667 funnel_ete_in_ete5: endpoint { 668 remote-endpoint = <&ete5_out_funnel_ete>; 669 }; 670 }; 671 672 port@6 { 673 reg = <6>; 674 675 funnel_ete_in_ete6: endpoint { 676 remote-endpoint = <&ete6_out_funnel_ete>; 677 }; 678 }; 679 680 port@7 { 681 reg = <7>; 682 683 funnel_ete_in_ete7: endpoint { 684 remote-endpoint = <&ete7_out_funnel_ete>; 685 }; 686 }; 687 }; 688 689 out-ports { 690 port { 691 funnel_ete_out_funnel_apss: endpoint { 692 remote-endpoint = <&funnel_apss_in_funnel_ete>; 693 }; 694 }; 695 }; 696 }; 697 698 firmware { 699 scm: scm { 700 compatible = "qcom,scm-sm8650", "qcom,scm"; 701 qcom,dload-mode = <&tcsr 0x19000>; 702 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 703 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 704 }; 705 }; 706 707 clk_virt: interconnect-0 { 708 compatible = "qcom,sm8650-clk-virt"; 709 #interconnect-cells = <2>; 710 qcom,bcm-voters = <&apps_bcm_voter>; 711 }; 712 713 mc_virt: interconnect-1 { 714 compatible = "qcom,sm8650-mc-virt"; 715 #interconnect-cells = <2>; 716 qcom,bcm-voters = <&apps_bcm_voter>; 717 }; 718 719 qup_opp_table_100mhz: opp-table-qup100mhz { 720 compatible = "operating-points-v2"; 721 722 opp-75000000 { 723 opp-hz = /bits/ 64 <75000000>; 724 required-opps = <&rpmhpd_opp_low_svs>; 725 }; 726 727 opp-100000000 { 728 opp-hz = /bits/ 64 <100000000>; 729 required-opps = <&rpmhpd_opp_svs>; 730 }; 731 }; 732 733 qup_opp_table_120mhz: opp-table-qup120mhz { 734 compatible = "operating-points-v2"; 735 736 opp-75000000 { 737 opp-hz = /bits/ 64 <75000000>; 738 required-opps = <&rpmhpd_opp_low_svs>; 739 }; 740 741 opp-120000000 { 742 opp-hz = /bits/ 64 <120000000>; 743 required-opps = <&rpmhpd_opp_svs>; 744 }; 745 }; 746 747 qup_opp_table_128mhz: opp-table-qup128mhz { 748 compatible = "operating-points-v2"; 749 750 opp-75000000 { 751 opp-hz = /bits/ 64 <75000000>; 752 required-opps = <&rpmhpd_opp_low_svs>; 753 }; 754 755 opp-128000000 { 756 opp-hz = /bits/ 64 <128000000>; 757 required-opps = <&rpmhpd_opp_svs>; 758 }; 759 }; 760 761 qup_opp_table_240mhz: opp-table-qup240mhz { 762 compatible = "operating-points-v2"; 763 764 opp-150000000 { 765 opp-hz = /bits/ 64 <150000000>; 766 required-opps = <&rpmhpd_opp_low_svs>; 767 }; 768 769 opp-240000000 { 770 opp-hz = /bits/ 64 <240000000>; 771 required-opps = <&rpmhpd_opp_svs>; 772 }; 773 }; 774 775 memory@a0000000 { 776 device_type = "memory"; 777 /* We expect the bootloader to fill in the size */ 778 reg = <0 0xa0000000 0 0>; 779 }; 780 781 cpu0_opp_table: opp-table-cpu0 { 782 compatible = "operating-points-v2"; 783 opp-shared; 784 785 opp-307200000 { 786 opp-hz = /bits/ 64 <307200000>; 787 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 788 }; 789 790 opp-364800000 { 791 opp-hz = /bits/ 64 <364800000>; 792 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 793 }; 794 795 opp-460800000 { 796 opp-hz = /bits/ 64 <460800000>; 797 opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>; 798 }; 799 800 opp-556800000 { 801 opp-hz = /bits/ 64 <556800000>; 802 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 803 }; 804 805 opp-672000000 { 806 opp-hz = /bits/ 64 <672000000>; 807 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 808 }; 809 810 opp-787200000 { 811 opp-hz = /bits/ 64 <787200000>; 812 opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>; 813 }; 814 815 opp-902400000 { 816 opp-hz = /bits/ 64 <902400000>; 817 opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>; 818 }; 819 820 opp-1017600000 { 821 opp-hz = /bits/ 64 <1017600000>; 822 opp-peak-kBps = <(466000 * 16) (547000 * 4) (940800 * 32)>; 823 }; 824 825 opp-1132800000 { 826 opp-hz = /bits/ 64 <1132800000>; 827 opp-peak-kBps = <(466000 * 16) (547000 * 4) (1036800 * 32)>; 828 }; 829 830 opp-1248000000 { 831 opp-hz = /bits/ 64 <1248000000>; 832 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1132800 * 32)>; 833 }; 834 835 opp-1344000000 { 836 opp-hz = /bits/ 64 <1344000000>; 837 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; 838 }; 839 840 opp-1440000000 { 841 opp-hz = /bits/ 64 <1440000000>; 842 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; 843 }; 844 845 opp-1459200000 { 846 opp-hz = /bits/ 64 <1459200000>; 847 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; 848 }; 849 850 opp-1536000000 { 851 opp-hz = /bits/ 64 <1536000000>; 852 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>; 853 }; 854 855 opp-1574400000 { 856 opp-hz = /bits/ 64 <1574400000>; 857 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>; 858 }; 859 860 opp-1651200000 { 861 opp-hz = /bits/ 64 <1651200000>; 862 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; 863 }; 864 865 opp-1689600000 { 866 opp-hz = /bits/ 64 <1689600000>; 867 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; 868 }; 869 870 opp-1747200000 { 871 opp-hz = /bits/ 64 <1747200000>; 872 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; 873 }; 874 875 opp-1804800000 { 876 opp-hz = /bits/ 64 <1804800000>; 877 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>; 878 }; 879 880 opp-1843200000 { 881 opp-hz = /bits/ 64 <1843200000>; 882 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>; 883 }; 884 885 opp-1920000000 { 886 opp-hz = /bits/ 64 <1920000000>; 887 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>; 888 }; 889 890 opp-1939200000 { 891 opp-hz = /bits/ 64 <1939200000>; 892 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>; 893 }; 894 895 opp-2035200000 { 896 opp-hz = /bits/ 64 <2035200000>; 897 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>; 898 }; 899 900 opp-2150400000 { 901 opp-hz = /bits/ 64 <2150400000>; 902 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>; 903 }; 904 905 opp-2265600000 { 906 opp-hz = /bits/ 64 <2265600000>; 907 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (2035200 * 32)>; 908 }; 909 }; 910 911 cpu2_opp_table: opp-table-cpu2 { 912 compatible = "operating-points-v2"; 913 opp-shared; 914 915 opp-460800000 { 916 opp-hz = /bits/ 64 <460800000>; 917 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 918 }; 919 920 opp-499200000 { 921 opp-hz = /bits/ 64 <499200000>; 922 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 923 }; 924 925 opp-576000000 { 926 opp-hz = /bits/ 64 <576000000>; 927 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 928 }; 929 930 opp-614400000 { 931 opp-hz = /bits/ 64 <614400000>; 932 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 933 }; 934 935 opp-691200000 { 936 opp-hz = /bits/ 64 <691200000>; 937 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 938 }; 939 940 opp-729600000 { 941 opp-hz = /bits/ 64 <729600000>; 942 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 943 }; 944 945 opp-806400000 { 946 opp-hz = /bits/ 64 <806400000>; 947 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 948 }; 949 950 opp-844800000 { 951 opp-hz = /bits/ 64 <844800000>; 952 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 953 }; 954 955 opp-902400000 { 956 opp-hz = /bits/ 64 <902400000>; 957 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 958 }; 959 960 opp-960000000 { 961 opp-hz = /bits/ 64 <960000000>; 962 opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>; 963 }; 964 965 opp-1036800000 { 966 opp-hz = /bits/ 64 <1036800000>; 967 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 968 }; 969 970 opp-1075200000 { 971 opp-hz = /bits/ 64 <1075200000>; 972 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 973 }; 974 975 opp-1152000000 { 976 opp-hz = /bits/ 64 <1152000000>; 977 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 978 }; 979 980 opp-1190400000 { 981 opp-hz = /bits/ 64 <1190400000>; 982 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; 983 }; 984 985 opp-1267200000 { 986 opp-hz = /bits/ 64 <1267200000>; 987 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 988 }; 989 990 opp-1286400000 { 991 opp-hz = /bits/ 64 <1286400000>; 992 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 993 }; 994 995 opp-1382400000 { 996 opp-hz = /bits/ 64 <1382400000>; 997 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 998 }; 999 1000 opp-1401600000 { 1001 opp-hz = /bits/ 64 <1401600000>; 1002 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; 1003 }; 1004 1005 opp-1497600000 { 1006 opp-hz = /bits/ 64 <1497600000>; 1007 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1008 }; 1009 1010 opp-1612800000 { 1011 opp-hz = /bits/ 64 <1612800000>; 1012 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1013 }; 1014 1015 opp-1708800000 { 1016 opp-hz = /bits/ 64 <1708800000>; 1017 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1018 }; 1019 1020 opp-1728000000 { 1021 opp-hz = /bits/ 64 <1728000000>; 1022 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1023 }; 1024 1025 opp-1824000000 { 1026 opp-hz = /bits/ 64 <1824000000>; 1027 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1028 }; 1029 1030 opp-1843200000 { 1031 opp-hz = /bits/ 64 <1843200000>; 1032 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1033 }; 1034 1035 opp-1920000000 { 1036 opp-hz = /bits/ 64 <1920000000>; 1037 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>; 1038 }; 1039 1040 opp-1958400000 { 1041 opp-hz = /bits/ 64 <1958400000>; 1042 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1043 }; 1044 1045 opp-2035200000 { 1046 opp-hz = /bits/ 64 <2035200000>; 1047 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1048 }; 1049 1050 opp-2073600000 { 1051 opp-hz = /bits/ 64 <2073600000>; 1052 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1053 }; 1054 1055 opp-2131200000 { 1056 opp-hz = /bits/ 64 <2131200000>; 1057 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1058 }; 1059 1060 opp-2188800000 { 1061 opp-hz = /bits/ 64 <2188800000>; 1062 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1063 }; 1064 1065 opp-2246400000 { 1066 opp-hz = /bits/ 64 <2246400000>; 1067 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1068 }; 1069 1070 opp-2304000000 { 1071 opp-hz = /bits/ 64 <2304000000>; 1072 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1073 }; 1074 1075 opp-2323200000 { 1076 opp-hz = /bits/ 64 <2323200000>; 1077 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1078 }; 1079 1080 opp-2380800000 { 1081 opp-hz = /bits/ 64 <2380800000>; 1082 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1083 }; 1084 1085 opp-2400000000 { 1086 opp-hz = /bits/ 64 <2400000000>; 1087 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1088 }; 1089 1090 opp-2438400000 { 1091 opp-hz = /bits/ 64 <2438400000>; 1092 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1093 }; 1094 1095 opp-2515200000 { 1096 opp-hz = /bits/ 64 <2515200000>; 1097 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1098 }; 1099 1100 opp-2572800000 { 1101 opp-hz = /bits/ 64 <2572800000>; 1102 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1103 }; 1104 1105 opp-2630400000 { 1106 opp-hz = /bits/ 64 <2630400000>; 1107 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1108 }; 1109 1110 opp-2707200000 { 1111 opp-hz = /bits/ 64 <2707200000>; 1112 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1113 }; 1114 1115 opp-2764800000 { 1116 opp-hz = /bits/ 64 <2764800000>; 1117 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; 1118 }; 1119 1120 opp-2841600000 { 1121 opp-hz = /bits/ 64 <2841600000>; 1122 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1123 }; 1124 1125 opp-2899200000 { 1126 opp-hz = /bits/ 64 <2899200000>; 1127 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1128 }; 1129 1130 opp-2956800000 { 1131 opp-hz = /bits/ 64 <2956800000>; 1132 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1133 }; 1134 1135 opp-3014400000 { 1136 opp-hz = /bits/ 64 <3014400000>; 1137 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1138 }; 1139 1140 opp-3072000000 { 1141 opp-hz = /bits/ 64 <3072000000>; 1142 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1143 }; 1144 1145 opp-3148800000 { 1146 opp-hz = /bits/ 64 <3148800000>; 1147 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1148 }; 1149 }; 1150 1151 cpu5_opp_table: opp-table-cpu5 { 1152 compatible = "operating-points-v2"; 1153 opp-shared; 1154 1155 opp-460800000 { 1156 opp-hz = /bits/ 64 <460800000>; 1157 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1158 }; 1159 1160 opp-499200000 { 1161 opp-hz = /bits/ 64 <499200000>; 1162 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1163 }; 1164 1165 opp-576000000 { 1166 opp-hz = /bits/ 64 <576000000>; 1167 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1168 }; 1169 1170 opp-614400000 { 1171 opp-hz = /bits/ 64 <614400000>; 1172 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 1173 }; 1174 1175 opp-691200000 { 1176 opp-hz = /bits/ 64 <691200000>; 1177 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1178 }; 1179 1180 opp-729600000 { 1181 opp-hz = /bits/ 64 <729600000>; 1182 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1183 }; 1184 1185 opp-806400000 { 1186 opp-hz = /bits/ 64 <806400000>; 1187 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1188 }; 1189 1190 opp-844800000 { 1191 opp-hz = /bits/ 64 <844800000>; 1192 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1193 }; 1194 1195 opp-902400000 { 1196 opp-hz = /bits/ 64 <902400000>; 1197 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1198 }; 1199 1200 opp-960000000 { 1201 opp-hz = /bits/ 64 <960000000>; 1202 opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>; 1203 }; 1204 1205 opp-1036800000 { 1206 opp-hz = /bits/ 64 <1036800000>; 1207 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1208 }; 1209 1210 opp-1075200000 { 1211 opp-hz = /bits/ 64 <1075200000>; 1212 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1213 }; 1214 1215 opp-1152000000 { 1216 opp-hz = /bits/ 64 <1152000000>; 1217 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1218 }; 1219 1220 opp-1190400000 { 1221 opp-hz = /bits/ 64 <1190400000>; 1222 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; 1223 }; 1224 1225 opp-1267200000 { 1226 opp-hz = /bits/ 64 <1267200000>; 1227 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1228 }; 1229 1230 opp-1286400000 { 1231 opp-hz = /bits/ 64 <1286400000>; 1232 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1233 }; 1234 1235 opp-1382400000 { 1236 opp-hz = /bits/ 64 <1382400000>; 1237 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1238 }; 1239 1240 opp-1401600000 { 1241 opp-hz = /bits/ 64 <1401600000>; 1242 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; 1243 }; 1244 1245 opp-1497600000 { 1246 opp-hz = /bits/ 64 <1497600000>; 1247 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1248 }; 1249 1250 opp-1612800000 { 1251 opp-hz = /bits/ 64 <1612800000>; 1252 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1253 }; 1254 1255 opp-1708800000 { 1256 opp-hz = /bits/ 64 <1708800000>; 1257 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1258 }; 1259 1260 opp-1728000000 { 1261 opp-hz = /bits/ 64 <1728000000>; 1262 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1263 }; 1264 1265 opp-1824000000 { 1266 opp-hz = /bits/ 64 <1824000000>; 1267 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1268 }; 1269 1270 opp-1843200000 { 1271 opp-hz = /bits/ 64 <1843200000>; 1272 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1273 }; 1274 1275 opp-1920000000 { 1276 opp-hz = /bits/ 64 <1920000000>; 1277 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>; 1278 }; 1279 1280 opp-1958400000 { 1281 opp-hz = /bits/ 64 <1958400000>; 1282 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1283 }; 1284 1285 opp-2035200000 { 1286 opp-hz = /bits/ 64 <2035200000>; 1287 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1288 }; 1289 1290 opp-2073600000 { 1291 opp-hz = /bits/ 64 <2073600000>; 1292 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1293 }; 1294 1295 opp-2131200000 { 1296 opp-hz = /bits/ 64 <2131200000>; 1297 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1298 }; 1299 1300 opp-2188800000 { 1301 opp-hz = /bits/ 64 <2188800000>; 1302 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1303 }; 1304 1305 opp-2246400000 { 1306 opp-hz = /bits/ 64 <2246400000>; 1307 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1308 }; 1309 1310 opp-2304000000 { 1311 opp-hz = /bits/ 64 <2304000000>; 1312 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1313 }; 1314 1315 opp-2323200000 { 1316 opp-hz = /bits/ 64 <2323200000>; 1317 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1318 }; 1319 1320 opp-2380800000 { 1321 opp-hz = /bits/ 64 <2380800000>; 1322 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1323 }; 1324 1325 opp-2400000000 { 1326 opp-hz = /bits/ 64 <2400000000>; 1327 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1328 }; 1329 1330 opp-2438400000 { 1331 opp-hz = /bits/ 64 <2438400000>; 1332 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1333 }; 1334 1335 opp-2515200000 { 1336 opp-hz = /bits/ 64 <2515200000>; 1337 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1338 }; 1339 1340 opp-2572800000 { 1341 opp-hz = /bits/ 64 <2572800000>; 1342 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1343 }; 1344 1345 opp-2630400000 { 1346 opp-hz = /bits/ 64 <2630400000>; 1347 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1348 }; 1349 1350 opp-2707200000 { 1351 opp-hz = /bits/ 64 <2707200000>; 1352 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1353 }; 1354 1355 opp-2764800000 { 1356 opp-hz = /bits/ 64 <2764800000>; 1357 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; 1358 }; 1359 1360 opp-2841600000 { 1361 opp-hz = /bits/ 64 <2841600000>; 1362 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1363 }; 1364 1365 opp-2899200000 { 1366 opp-hz = /bits/ 64 <2899200000>; 1367 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1368 }; 1369 1370 opp-2956800000 { 1371 opp-hz = /bits/ 64 <2956800000>; 1372 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1373 }; 1374 1375 opp-3014400000 { 1376 opp-hz = /bits/ 64 <3014400000>; 1377 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1378 }; 1379 1380 opp-3072000000 { 1381 opp-hz = /bits/ 64 <3072000000>; 1382 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1383 }; 1384 1385 opp-3148800000 { 1386 opp-hz = /bits/ 64 <3148800000>; 1387 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1388 }; 1389 }; 1390 1391 cpu7_opp_table: opp-table-cpu7 { 1392 compatible = "operating-points-v2"; 1393 opp-shared; 1394 1395 opp-480000000 { 1396 opp-hz = /bits/ 64 <480000000>; 1397 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1398 }; 1399 1400 opp-499200000 { 1401 opp-hz = /bits/ 64 <499200000>; 1402 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1403 }; 1404 1405 opp-576000000 { 1406 opp-hz = /bits/ 64 <576000000>; 1407 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1408 }; 1409 1410 opp-614400000 { 1411 opp-hz = /bits/ 64 <614400000>; 1412 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 1413 }; 1414 1415 opp-672000000 { 1416 opp-hz = /bits/ 64 <672000000>; 1417 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1418 }; 1419 1420 opp-729600000 { 1421 opp-hz = /bits/ 64 <729600000>; 1422 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1423 }; 1424 1425 opp-787200000 { 1426 opp-hz = /bits/ 64 <787200000>; 1427 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1428 }; 1429 1430 opp-844800000 { 1431 opp-hz = /bits/ 64 <844800000>; 1432 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1433 }; 1434 1435 opp-902400000 { 1436 opp-hz = /bits/ 64 <902400000>; 1437 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1438 }; 1439 1440 opp-940800000 { 1441 opp-hz = /bits/ 64 <940800000>; 1442 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1443 }; 1444 1445 opp-1017600000 { 1446 opp-hz = /bits/ 64 <1017600000>; 1447 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1448 }; 1449 1450 opp-1075200000 { 1451 opp-hz = /bits/ 64 <1075200000>; 1452 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1453 }; 1454 1455 opp-1132800000 { 1456 opp-hz = /bits/ 64 <1132800000>; 1457 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1458 }; 1459 1460 opp-1190400000 { 1461 opp-hz = /bits/ 64 <1190400000>; 1462 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; 1463 }; 1464 1465 opp-1248000000 { 1466 opp-hz = /bits/ 64 <1248000000>; 1467 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1468 }; 1469 1470 opp-1305600000 { 1471 opp-hz = /bits/ 64 <1305600000>; 1472 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1473 }; 1474 1475 opp-1363200000 { 1476 opp-hz = /bits/ 64 <1363200000>; 1477 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1478 }; 1479 1480 opp-1420800000 { 1481 opp-hz = /bits/ 64 <1420800000>; 1482 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; 1483 }; 1484 1485 opp-1478400000 { 1486 opp-hz = /bits/ 64 <1478400000>; 1487 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1488 }; 1489 1490 opp-1555200000 { 1491 opp-hz = /bits/ 64 <1555200000>; 1492 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1493 }; 1494 1495 opp-1593600000 { 1496 opp-hz = /bits/ 64 <1593600000>; 1497 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1498 }; 1499 1500 opp-1670400000 { 1501 opp-hz = /bits/ 64 <1670400000>; 1502 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1503 }; 1504 1505 opp-1708800000 { 1506 opp-hz = /bits/ 64 <1708800000>; 1507 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1508 }; 1509 1510 opp-1804800000 { 1511 opp-hz = /bits/ 64 <1804800000>; 1512 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1513 }; 1514 1515 opp-1824000000 { 1516 opp-hz = /bits/ 64 <1824000000>; 1517 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1518 }; 1519 1520 opp-1939200000 { 1521 opp-hz = /bits/ 64 <1939200000>; 1522 opp-peak-kBps = <(806000 * 16) (3686000 * 4) (1440000 * 32)>; 1523 }; 1524 1525 opp-2035200000 { 1526 opp-hz = /bits/ 64 <2035200000>; 1527 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1528 }; 1529 1530 opp-2073600000 { 1531 opp-hz = /bits/ 64 <2073600000>; 1532 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1533 }; 1534 1535 opp-2112000000 { 1536 opp-hz = /bits/ 64 <2112000000>; 1537 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1538 }; 1539 1540 opp-2169600000 { 1541 opp-hz = /bits/ 64 <2169600000>; 1542 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1543 }; 1544 1545 opp-2208000000 { 1546 opp-hz = /bits/ 64 <2208000000>; 1547 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1548 }; 1549 1550 opp-2246400000 { 1551 opp-hz = /bits/ 64 <2246400000>; 1552 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1553 }; 1554 1555 opp-2304000000 { 1556 opp-hz = /bits/ 64 <2304000000>; 1557 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1558 }; 1559 1560 opp-2342400000 { 1561 opp-hz = /bits/ 64 <2342400000>; 1562 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1563 }; 1564 1565 opp-2380800000 { 1566 opp-hz = /bits/ 64 <2380800000>; 1567 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1568 }; 1569 1570 opp-2438400000 { 1571 opp-hz = /bits/ 64 <2438400000>; 1572 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1573 }; 1574 1575 opp-2457600000 { 1576 opp-hz = /bits/ 64 <2457600000>; 1577 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1578 }; 1579 1580 opp-2496000000 { 1581 opp-hz = /bits/ 64 <2496000000>; 1582 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1583 }; 1584 1585 opp-2553600000 { 1586 opp-hz = /bits/ 64 <2553600000>; 1587 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1588 }; 1589 1590 opp-2630400000 { 1591 opp-hz = /bits/ 64 <2630400000>; 1592 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1593 }; 1594 1595 opp-2688000000 { 1596 opp-hz = /bits/ 64 <2688000000>; 1597 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1598 }; 1599 1600 opp-2745600000 { 1601 opp-hz = /bits/ 64 <2745600000>; 1602 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; 1603 }; 1604 1605 opp-2803200000 { 1606 opp-hz = /bits/ 64 <2803200000>; 1607 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1608 }; 1609 1610 opp-2880000000 { 1611 opp-hz = /bits/ 64 <2880000000>; 1612 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1613 }; 1614 1615 opp-2937600000 { 1616 opp-hz = /bits/ 64 <2937600000>; 1617 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1618 }; 1619 1620 opp-2995200000 { 1621 opp-hz = /bits/ 64 <2995200000>; 1622 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1623 }; 1624 1625 opp-3052800000 { 1626 opp-hz = /bits/ 64 <3052800000>; 1627 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1628 }; 1629 1630 opp-3187200000 { 1631 opp-hz = /bits/ 64 <3187200000>; 1632 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1633 }; 1634 1635 opp-3302400000 { 1636 opp-hz = /bits/ 64 <3302400000>; 1637 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1638 }; 1639 }; 1640 1641 pmu-a520 { 1642 compatible = "arm,cortex-a520-pmu"; 1643 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 1644 }; 1645 1646 pmu-a720 { 1647 compatible = "arm,cortex-a720-pmu"; 1648 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 1649 }; 1650 1651 pmu-x4 { 1652 compatible = "arm,cortex-x4-pmu"; 1653 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster2>; 1654 }; 1655 1656 psci { 1657 compatible = "arm,psci-1.0"; 1658 method = "smc"; 1659 1660 cpu_pd0: power-domain-cpu0 { 1661 #power-domain-cells = <0>; 1662 power-domains = <&cluster_pd>; 1663 domain-idle-states = <&silver_cpu_sleep_0>; 1664 }; 1665 1666 cpu_pd1: power-domain-cpu1 { 1667 #power-domain-cells = <0>; 1668 power-domains = <&cluster_pd>; 1669 domain-idle-states = <&silver_cpu_sleep_0>; 1670 }; 1671 1672 cpu_pd2: power-domain-cpu2 { 1673 #power-domain-cells = <0>; 1674 power-domains = <&cluster_pd>; 1675 domain-idle-states = <&gold_cpu_sleep_0>; 1676 }; 1677 1678 cpu_pd3: power-domain-cpu3 { 1679 #power-domain-cells = <0>; 1680 power-domains = <&cluster_pd>; 1681 domain-idle-states = <&gold_cpu_sleep_0>; 1682 }; 1683 1684 cpu_pd4: power-domain-cpu4 { 1685 #power-domain-cells = <0>; 1686 power-domains = <&cluster_pd>; 1687 domain-idle-states = <&gold_cpu_sleep_0>; 1688 }; 1689 1690 cpu_pd5: power-domain-cpu5 { 1691 #power-domain-cells = <0>; 1692 power-domains = <&cluster_pd>; 1693 domain-idle-states = <&gold_cpu_sleep_0>; 1694 }; 1695 1696 cpu_pd6: power-domain-cpu6 { 1697 #power-domain-cells = <0>; 1698 power-domains = <&cluster_pd>; 1699 domain-idle-states = <&gold_cpu_sleep_0>; 1700 }; 1701 1702 cpu_pd7: power-domain-cpu7 { 1703 #power-domain-cells = <0>; 1704 power-domains = <&cluster_pd>; 1705 domain-idle-states = <&gold_plus_cpu_sleep_0>; 1706 }; 1707 1708 cluster_pd: power-domain-cluster { 1709 #power-domain-cells = <0>; 1710 domain-idle-states = <&cluster_sleep_0>, 1711 <&cluster_sleep_1>; 1712 }; 1713 }; 1714 1715 reserved_memory: reserved-memory { 1716 #address-cells = <2>; 1717 #size-cells = <2>; 1718 ranges; 1719 1720 hyp_mem: hyp@80000000 { 1721 reg = <0 0x80000000 0 0xe00000>; 1722 no-map; 1723 }; 1724 1725 cpusys_vm_mem: cpusys-vm@80e00000 { 1726 reg = <0 0x80e00000 0 0x400000>; 1727 no-map; 1728 }; 1729 1730 /* Merged xbl_dtlog, xbl_ramdump and aop_image regions */ 1731 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 { 1732 reg = <0 0x81a00000 0 0x260000>; 1733 no-map; 1734 }; 1735 1736 aop_cmd_db_mem: aop-cmd-db@81c60000 { 1737 compatible = "qcom,cmd-db"; 1738 reg = <0 0x81c60000 0 0x20000>; 1739 no-map; 1740 }; 1741 1742 /* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */ 1743 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 1744 reg = <0 0x81c80000 0 0x75000>; 1745 no-map; 1746 }; 1747 1748 /* Secdata region can be reused by apps */ 1749 1750 smem: smem@81d00000 { 1751 compatible = "qcom,smem"; 1752 reg = <0 0x81d00000 0 0x200000>; 1753 hwlocks = <&tcsr_mutex 3>; 1754 no-map; 1755 }; 1756 1757 adsp_mhi_mem: adsp-mhi@81f00000 { 1758 reg = <0 0x81f00000 0 0x20000>; 1759 no-map; 1760 }; 1761 1762 pvmfw_mem: pvmfw@824a0000 { 1763 reg = <0 0x824a0000 0 0x100000>; 1764 no-map; 1765 }; 1766 1767 global_sync_mem: global-sync@82600000 { 1768 reg = <0 0x82600000 0 0x100000>; 1769 no-map; 1770 }; 1771 1772 tz_stat_mem: tz-stat@82700000 { 1773 reg = <0 0x82700000 0 0x100000>; 1774 no-map; 1775 }; 1776 1777 qdss_mem: qdss@82800000 { 1778 reg = <0 0x82800000 0 0x2000000>; 1779 no-map; 1780 }; 1781 1782 qlink_logging_mem: qlink-logging@84800000 { 1783 reg = <0 0x84800000 0 0x200000>; 1784 no-map; 1785 }; 1786 1787 mpss_dsm_mem: mpss-dsm@86b00000 { 1788 reg = <0 0x86b00000 0 0x4900000>; 1789 no-map; 1790 }; 1791 1792 mpss_dsm_mem_2: mpss-dsm-2@8b400000 { 1793 reg = <0 0x8b400000 0 0x800000>; 1794 no-map; 1795 }; 1796 1797 mpss_mem: mpss@8bc00000 { 1798 reg = <0 0x8bc00000 0 0xf400000>; 1799 no-map; 1800 }; 1801 1802 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { 1803 reg = <0 0x9b000000 0 0x80000>; 1804 no-map; 1805 }; 1806 1807 ipa_fw_mem: ipa-fw@9b080000 { 1808 reg = <0 0x9b080000 0 0x10000>; 1809 no-map; 1810 }; 1811 1812 ipa_gsi_mem: ipa-gsi@9b090000 { 1813 reg = <0 0x9b090000 0 0xa000>; 1814 no-map; 1815 }; 1816 1817 gpu_micro_code_mem: gpu-micro-code@9b09a000 { 1818 reg = <0 0x9b09a000 0 0x2000>; 1819 no-map; 1820 }; 1821 1822 spss_region_mem: spss@9b0a0000 { 1823 reg = <0 0x9b0a0000 0 0x1e0000>; 1824 no-map; 1825 }; 1826 1827 /* First part of the "SPU secure shared memory" region */ 1828 spu_tz_shared_mem: spu-tz-shared@9b280000 { 1829 reg = <0 0x9b280000 0 0x60000>; 1830 no-map; 1831 }; 1832 1833 /* Second part of the "SPU secure shared memory" region */ 1834 spu_modem_shared_mem: spu-modem-shared@9b2e0000 { 1835 reg = <0 0x9b2e0000 0 0x20000>; 1836 no-map; 1837 }; 1838 1839 camera_mem: camera@9b300000 { 1840 reg = <0 0x9b300000 0 0x800000>; 1841 no-map; 1842 }; 1843 1844 video_mem: video@9bb00000 { 1845 reg = <0 0x9bb00000 0 0x800000>; 1846 no-map; 1847 }; 1848 1849 cvp_mem: cvp@9c300000 { 1850 reg = <0 0x9c300000 0 0x700000>; 1851 no-map; 1852 }; 1853 1854 cdsp_mem: cdsp@9ca00000 { 1855 reg = <0 0x9ca00000 0 0x1400000>; 1856 no-map; 1857 }; 1858 1859 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 { 1860 reg = <0 0x9de00000 0 0x80000>; 1861 no-map; 1862 }; 1863 1864 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 { 1865 reg = <0 0x9de80000 0 0x80000>; 1866 no-map; 1867 }; 1868 1869 adspslpi_mem: adspslpi@9df00000 { 1870 reg = <0 0x9df00000 0 0x4080000>; 1871 no-map; 1872 }; 1873 1874 rmtfs_mem: rmtfs@d7c00000 { 1875 compatible = "qcom,rmtfs-mem"; 1876 reg = <0 0xd7c00000 0 0x400000>; 1877 no-map; 1878 1879 qcom,client-id = <1>; 1880 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 1881 }; 1882 1883 /* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */ 1884 tz_merged_mem: tz-merged@d8000000 { 1885 reg = <0 0xd8000000 0 0x800000>; 1886 no-map; 1887 }; 1888 1889 hwfence_shbuf: hwfence-shbuf@e6440000 { 1890 reg = <0 0xe6440000 0 0x2dd000>; 1891 no-map; 1892 }; 1893 1894 trust_ui_vm_mem: trust-ui-vm@f3800000 { 1895 reg = <0 0xf3800000 0 0x4400000>; 1896 no-map; 1897 }; 1898 1899 oem_vm_mem: oem-vm@f7c00000 { 1900 reg = <0 0xf7c00000 0 0x4c00000>; 1901 no-map; 1902 }; 1903 1904 llcc_lpi_mem: llcc-lpi@ff800000 { 1905 reg = <0 0xff800000 0 0x600000>; 1906 no-map; 1907 }; 1908 }; 1909 1910 smp2p-adsp { 1911 compatible = "qcom,smp2p"; 1912 1913 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1914 IPCC_MPROC_SIGNAL_SMP2P 1915 IRQ_TYPE_EDGE_RISING>; 1916 1917 mboxes = <&ipcc IPCC_CLIENT_LPASS 1918 IPCC_MPROC_SIGNAL_SMP2P>; 1919 1920 qcom,smem = <443>, <429>; 1921 qcom,local-pid = <0>; 1922 qcom,remote-pid = <2>; 1923 1924 smp2p_adsp_out: master-kernel { 1925 qcom,entry-name = "master-kernel"; 1926 #qcom,smem-state-cells = <1>; 1927 }; 1928 1929 smp2p_adsp_in: slave-kernel { 1930 qcom,entry-name = "slave-kernel"; 1931 interrupt-controller; 1932 #interrupt-cells = <2>; 1933 }; 1934 }; 1935 1936 smp2p-cdsp { 1937 compatible = "qcom,smp2p"; 1938 1939 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1940 IPCC_MPROC_SIGNAL_SMP2P 1941 IRQ_TYPE_EDGE_RISING>; 1942 1943 mboxes = <&ipcc IPCC_CLIENT_CDSP 1944 IPCC_MPROC_SIGNAL_SMP2P>; 1945 1946 qcom,smem = <94>, <432>; 1947 qcom,local-pid = <0>; 1948 qcom,remote-pid = <5>; 1949 1950 smp2p_cdsp_out: master-kernel { 1951 qcom,entry-name = "master-kernel"; 1952 #qcom,smem-state-cells = <1>; 1953 }; 1954 1955 smp2p_cdsp_in: slave-kernel { 1956 qcom,entry-name = "slave-kernel"; 1957 interrupt-controller; 1958 #interrupt-cells = <2>; 1959 }; 1960 }; 1961 1962 smp2p-modem { 1963 compatible = "qcom,smp2p"; 1964 1965 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1966 IPCC_MPROC_SIGNAL_SMP2P 1967 IRQ_TYPE_EDGE_RISING>; 1968 1969 mboxes = <&ipcc IPCC_CLIENT_MPSS 1970 IPCC_MPROC_SIGNAL_SMP2P>; 1971 1972 qcom,smem = <435>, <428>; 1973 qcom,local-pid = <0>; 1974 qcom,remote-pid = <1>; 1975 1976 smp2p_modem_out: master-kernel { 1977 qcom,entry-name = "master-kernel"; 1978 #qcom,smem-state-cells = <1>; 1979 }; 1980 1981 smp2p_modem_in: slave-kernel { 1982 qcom,entry-name = "slave-kernel"; 1983 interrupt-controller; 1984 #interrupt-cells = <2>; 1985 }; 1986 1987 ipa_smp2p_out: ipa-ap-to-modem { 1988 qcom,entry-name = "ipa"; 1989 #qcom,smem-state-cells = <1>; 1990 }; 1991 1992 ipa_smp2p_in: ipa-modem-to-ap { 1993 qcom,entry-name = "ipa"; 1994 interrupt-controller; 1995 #interrupt-cells = <2>; 1996 }; 1997 }; 1998 1999 soc: soc@0 { 2000 compatible = "simple-bus"; 2001 2002 #address-cells = <2>; 2003 #size-cells = <2>; 2004 dma-ranges = <0 0 0 0 0x10 0>; 2005 ranges = <0 0 0 0 0x10 0>; 2006 2007 gcc: clock-controller@100000 { 2008 compatible = "qcom,sm8650-gcc"; 2009 reg = <0 0x00100000 0 0x1f4200>; 2010 2011 clocks = <&bi_tcxo_div2>, 2012 <&bi_tcxo_ao_div2>, 2013 <&sleep_clk>, 2014 <&pcie0_phy>, 2015 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 2016 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 2017 <&ufs_mem_phy 0>, 2018 <&ufs_mem_phy 1>, 2019 <&ufs_mem_phy 2>, 2020 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 2021 2022 #clock-cells = <1>; 2023 #reset-cells = <1>; 2024 #power-domain-cells = <1>; 2025 }; 2026 2027 ipcc: mailbox@406000 { 2028 compatible = "qcom,sm8650-ipcc", "qcom,ipcc"; 2029 reg = <0 0x00406000 0 0x1000>; 2030 2031 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>; 2032 interrupt-controller; 2033 #interrupt-cells = <3>; 2034 2035 #mbox-cells = <2>; 2036 }; 2037 2038 gpi_dma2: dma-controller@800000 { 2039 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 2040 reg = <0 0x00800000 0 0x60000>; 2041 2042 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>, 2043 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>, 2044 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, 2045 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, 2046 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, 2047 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, 2048 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, 2049 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, 2050 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, 2051 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>, 2052 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>, 2053 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>; 2054 2055 dma-channels = <12>; 2056 dma-channel-mask = <0x3f>; 2057 #dma-cells = <3>; 2058 2059 iommus = <&apps_smmu 0x436 0>; 2060 2061 dma-coherent; 2062 2063 status = "disabled"; 2064 }; 2065 2066 qupv3_id_1: geniqup@8c0000 { 2067 compatible = "qcom,geni-se-qup"; 2068 reg = <0 0x008c0000 0 0x2000>; 2069 2070 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 2071 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 2072 clock-names = "m-ahb", 2073 "s-ahb"; 2074 2075 iommus = <&apps_smmu 0x423 0>; 2076 2077 dma-coherent; 2078 2079 #address-cells = <2>; 2080 #size-cells = <2>; 2081 ranges; 2082 2083 status = "disabled"; 2084 2085 i2c8: i2c@880000 { 2086 compatible = "qcom,geni-i2c"; 2087 reg = <0 0x00880000 0 0x4000>; 2088 2089 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 2090 2091 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 2092 clock-names = "se"; 2093 2094 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2095 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2096 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2097 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2098 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2099 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2100 interconnect-names = "qup-core", 2101 "qup-config", 2102 "qup-memory"; 2103 2104 power-domains = <&rpmhpd RPMHPD_CX>; 2105 2106 operating-points-v2 = <&qup_opp_table_120mhz>; 2107 2108 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 2109 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 2110 dma-names = "tx", 2111 "rx"; 2112 2113 pinctrl-0 = <&qup_i2c8_data_clk>; 2114 pinctrl-names = "default"; 2115 2116 #address-cells = <1>; 2117 #size-cells = <0>; 2118 2119 status = "disabled"; 2120 }; 2121 2122 spi8: spi@880000 { 2123 compatible = "qcom,geni-spi"; 2124 reg = <0 0x00880000 0 0x4000>; 2125 2126 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 2127 2128 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 2129 clock-names = "se"; 2130 2131 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2132 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2133 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2134 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2135 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2136 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2137 interconnect-names = "qup-core", 2138 "qup-config", 2139 "qup-memory"; 2140 2141 power-domains = <&rpmhpd RPMHPD_CX>; 2142 2143 operating-points-v2 = <&qup_opp_table_100mhz>; 2144 2145 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 2146 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 2147 dma-names = "tx", 2148 "rx"; 2149 2150 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 2151 pinctrl-names = "default"; 2152 2153 #address-cells = <1>; 2154 #size-cells = <0>; 2155 2156 status = "disabled"; 2157 }; 2158 2159 i2c9: i2c@884000 { 2160 compatible = "qcom,geni-i2c"; 2161 reg = <0 0x00884000 0 0x4000>; 2162 2163 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; 2164 2165 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 2166 clock-names = "se"; 2167 2168 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2169 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2170 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2171 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2172 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2173 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2174 interconnect-names = "qup-core", 2175 "qup-config", 2176 "qup-memory"; 2177 2178 power-domains = <&rpmhpd RPMHPD_CX>; 2179 2180 operating-points-v2 = <&qup_opp_table_120mhz>; 2181 2182 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 2183 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 2184 dma-names = "tx", 2185 "rx"; 2186 2187 pinctrl-0 = <&qup_i2c9_data_clk>; 2188 pinctrl-names = "default"; 2189 2190 #address-cells = <1>; 2191 #size-cells = <0>; 2192 2193 status = "disabled"; 2194 }; 2195 2196 spi9: spi@884000 { 2197 compatible = "qcom,geni-spi"; 2198 reg = <0 0x00884000 0 0x4000>; 2199 2200 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; 2201 2202 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 2203 clock-names = "se"; 2204 2205 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2206 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2207 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2208 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2209 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2210 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2211 interconnect-names = "qup-core", 2212 "qup-config", 2213 "qup-memory"; 2214 2215 power-domains = <&rpmhpd RPMHPD_CX>; 2216 2217 operating-points-v2 = <&qup_opp_table_120mhz>; 2218 2219 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 2220 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 2221 dma-names = "tx", 2222 "rx"; 2223 2224 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 2225 pinctrl-names = "default"; 2226 2227 #address-cells = <1>; 2228 #size-cells = <0>; 2229 2230 status = "disabled"; 2231 }; 2232 2233 i2c10: i2c@888000 { 2234 compatible = "qcom,geni-i2c"; 2235 reg = <0 0x00888000 0 0x4000>; 2236 2237 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; 2238 2239 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 2240 clock-names = "se"; 2241 2242 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2243 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2244 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2245 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2246 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2247 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2248 interconnect-names = "qup-core", 2249 "qup-config", 2250 "qup-memory"; 2251 2252 power-domains = <&rpmhpd RPMHPD_CX>; 2253 2254 operating-points-v2 = <&qup_opp_table_120mhz>; 2255 2256 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 2257 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 2258 dma-names = "tx", 2259 "rx"; 2260 2261 pinctrl-0 = <&qup_i2c10_data_clk>; 2262 pinctrl-names = "default"; 2263 2264 #address-cells = <1>; 2265 #size-cells = <0>; 2266 2267 status = "disabled"; 2268 }; 2269 2270 spi10: spi@888000 { 2271 compatible = "qcom,geni-spi"; 2272 reg = <0 0x00888000 0 0x4000>; 2273 2274 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; 2275 2276 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 2277 clock-names = "se"; 2278 2279 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2280 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2281 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2282 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2283 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2284 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2285 interconnect-names = "qup-core", 2286 "qup-config", 2287 "qup-memory"; 2288 2289 power-domains = <&rpmhpd RPMHPD_CX>; 2290 2291 operating-points-v2 = <&qup_opp_table_120mhz>; 2292 2293 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 2294 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 2295 dma-names = "tx", 2296 "rx"; 2297 2298 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 2299 pinctrl-names = "default"; 2300 2301 #address-cells = <1>; 2302 #size-cells = <0>; 2303 2304 status = "disabled"; 2305 }; 2306 2307 i2c11: i2c@88c000 { 2308 compatible = "qcom,geni-i2c"; 2309 reg = <0 0x0088c000 0 0x4000>; 2310 2311 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2312 2313 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 2314 clock-names = "se"; 2315 2316 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2317 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2318 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2319 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2320 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2321 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2322 interconnect-names = "qup-core", 2323 "qup-config", 2324 "qup-memory"; 2325 2326 power-domains = <&rpmhpd RPMHPD_CX>; 2327 2328 operating-points-v2 = <&qup_opp_table_120mhz>; 2329 2330 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 2331 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 2332 dma-names = "tx", 2333 "rx"; 2334 2335 pinctrl-0 = <&qup_i2c11_data_clk>; 2336 pinctrl-names = "default"; 2337 2338 #address-cells = <1>; 2339 #size-cells = <0>; 2340 2341 status = "disabled"; 2342 }; 2343 2344 spi11: spi@88c000 { 2345 compatible = "qcom,geni-spi"; 2346 reg = <0 0x0088c000 0 0x4000>; 2347 2348 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2349 2350 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 2351 clock-names = "se"; 2352 2353 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2354 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2355 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2356 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2357 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2358 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2359 interconnect-names = "qup-core", 2360 "qup-config", 2361 "qup-memory"; 2362 2363 power-domains = <&rpmhpd RPMHPD_CX>; 2364 2365 operating-points-v2 = <&qup_opp_table_120mhz>; 2366 2367 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 2368 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 2369 dma-names = "tx", 2370 "rx"; 2371 2372 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 2373 pinctrl-names = "default"; 2374 2375 #address-cells = <1>; 2376 #size-cells = <0>; 2377 2378 status = "disabled"; 2379 }; 2380 2381 i2c12: i2c@890000 { 2382 compatible = "qcom,geni-i2c"; 2383 reg = <0 0x00890000 0 0x4000>; 2384 2385 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2386 2387 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 2388 clock-names = "se"; 2389 2390 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2391 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2392 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2393 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2394 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2395 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2396 interconnect-names = "qup-core", 2397 "qup-config", 2398 "qup-memory"; 2399 2400 power-domains = <&rpmhpd RPMHPD_CX>; 2401 2402 operating-points-v2 = <&qup_opp_table_100mhz>; 2403 2404 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 2405 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 2406 dma-names = "tx", 2407 "rx"; 2408 2409 pinctrl-0 = <&qup_i2c12_data_clk>; 2410 pinctrl-names = "default"; 2411 2412 #address-cells = <1>; 2413 #size-cells = <0>; 2414 2415 status = "disabled"; 2416 }; 2417 2418 spi12: spi@890000 { 2419 compatible = "qcom,geni-spi"; 2420 reg = <0 0x00890000 0 0x4000>; 2421 2422 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2423 2424 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 2425 clock-names = "se"; 2426 2427 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2428 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2429 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2430 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2431 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2432 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2433 interconnect-names = "qup-core", 2434 "qup-config", 2435 "qup-memory"; 2436 2437 power-domains = <&rpmhpd RPMHPD_CX>; 2438 2439 operating-points-v2 = <&qup_opp_table_100mhz>; 2440 2441 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 2442 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 2443 dma-names = "tx", 2444 "rx"; 2445 2446 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 2447 pinctrl-names = "default"; 2448 2449 #address-cells = <1>; 2450 #size-cells = <0>; 2451 2452 status = "disabled"; 2453 }; 2454 2455 i2c13: i2c@894000 { 2456 compatible = "qcom,geni-i2c"; 2457 reg = <0 0x00894000 0 0x4000>; 2458 2459 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; 2460 2461 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 2462 clock-names = "se"; 2463 2464 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2465 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2466 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2467 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2468 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2469 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2470 interconnect-names = "qup-core", 2471 "qup-config", 2472 "qup-memory"; 2473 2474 power-domains = <&rpmhpd RPMHPD_CX>; 2475 2476 operating-points-v2 = <&qup_opp_table_100mhz>; 2477 2478 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 2479 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 2480 dma-names = "tx", 2481 "rx"; 2482 2483 pinctrl-0 = <&qup_i2c13_data_clk>; 2484 pinctrl-names = "default"; 2485 2486 #address-cells = <1>; 2487 #size-cells = <0>; 2488 2489 status = "disabled"; 2490 }; 2491 2492 spi13: spi@894000 { 2493 compatible = "qcom,geni-spi"; 2494 reg = <0 0x00894000 0 0x4000>; 2495 2496 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; 2497 2498 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 2499 clock-names = "se"; 2500 2501 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2502 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2503 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2504 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2505 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2506 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2507 interconnect-names = "qup-core", 2508 "qup-config", 2509 "qup-memory"; 2510 2511 power-domains = <&rpmhpd RPMHPD_CX>; 2512 2513 operating-points-v2 = <&qup_opp_table_100mhz>; 2514 2515 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 2516 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 2517 dma-names = "tx", 2518 "rx"; 2519 2520 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 2521 pinctrl-names = "default"; 2522 2523 #address-cells = <1>; 2524 #size-cells = <0>; 2525 2526 status = "disabled"; 2527 }; 2528 2529 uart14: serial@898000 { 2530 compatible = "qcom,geni-uart"; 2531 reg = <0 0x00898000 0 0x4000>; 2532 2533 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH 0>; 2534 2535 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 2536 clock-names = "se"; 2537 2538 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2539 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2540 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2541 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 2542 interconnect-names = "qup-core", 2543 "qup-config"; 2544 2545 power-domains = <&rpmhpd RPMHPD_CX>; 2546 2547 operating-points-v2 = <&qup_opp_table_128mhz>; 2548 2549 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 2550 pinctrl-names = "default"; 2551 2552 status = "disabled"; 2553 }; 2554 2555 uart15: serial@89c000 { 2556 compatible = "qcom,geni-debug-uart"; 2557 reg = <0 0x0089c000 0 0x4000>; 2558 2559 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 2560 2561 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 2562 clock-names = "se"; 2563 2564 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2565 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2566 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2567 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 2568 interconnect-names = "qup-core", 2569 "qup-config"; 2570 2571 power-domains = <&rpmhpd RPMHPD_CX>; 2572 2573 operating-points-v2 = <&qup_opp_table_100mhz>; 2574 2575 pinctrl-0 = <&qup_uart15_default>; 2576 pinctrl-names = "default"; 2577 2578 status = "disabled"; 2579 }; 2580 }; 2581 2582 i2c_master_hub_0: geniqup@9c0000 { 2583 compatible = "qcom,geni-se-i2c-master-hub"; 2584 reg = <0 0x009c0000 0 0x2000>; 2585 2586 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 2587 clock-names = "s-ahb"; 2588 2589 #address-cells = <2>; 2590 #size-cells = <2>; 2591 ranges; 2592 2593 status = "disabled"; 2594 2595 i2c_hub_0: i2c@980000 { 2596 compatible = "qcom,geni-i2c-master-hub"; 2597 reg = <0 0x00980000 0 0x4000>; 2598 2599 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>; 2600 2601 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 2602 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2603 clock-names = "se", 2604 "core"; 2605 2606 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2607 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2608 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2609 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2610 interconnect-names = "qup-core", 2611 "qup-config"; 2612 2613 power-domains = <&rpmhpd RPMHPD_CX>; 2614 2615 required-opps = <&rpmhpd_opp_low_svs>; 2616 2617 pinctrl-0 = <&hub_i2c0_data_clk>; 2618 pinctrl-names = "default"; 2619 2620 #address-cells = <1>; 2621 #size-cells = <0>; 2622 2623 status = "disabled"; 2624 }; 2625 2626 i2c_hub_1: i2c@984000 { 2627 compatible = "qcom,geni-i2c-master-hub"; 2628 reg = <0 0x00984000 0 0x4000>; 2629 2630 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH 0>; 2631 2632 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 2633 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2634 clock-names = "se", 2635 "core"; 2636 2637 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2638 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2639 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2640 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2641 interconnect-names = "qup-core", 2642 "qup-config"; 2643 2644 power-domains = <&rpmhpd RPMHPD_CX>; 2645 2646 required-opps = <&rpmhpd_opp_low_svs>; 2647 2648 pinctrl-0 = <&hub_i2c1_data_clk>; 2649 pinctrl-names = "default"; 2650 2651 #address-cells = <1>; 2652 #size-cells = <0>; 2653 2654 status = "disabled"; 2655 }; 2656 2657 i2c_hub_2: i2c@988000 { 2658 compatible = "qcom,geni-i2c-master-hub"; 2659 reg = <0 0x00988000 0 0x4000>; 2660 2661 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH 0>; 2662 2663 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 2664 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2665 clock-names = "se", 2666 "core"; 2667 2668 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2669 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2670 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2671 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2672 interconnect-names = "qup-core", 2673 "qup-config"; 2674 2675 power-domains = <&rpmhpd RPMHPD_CX>; 2676 2677 required-opps = <&rpmhpd_opp_low_svs>; 2678 2679 pinctrl-0 = <&hub_i2c2_data_clk>; 2680 pinctrl-names = "default"; 2681 2682 #address-cells = <1>; 2683 #size-cells = <0>; 2684 2685 status = "disabled"; 2686 }; 2687 2688 i2c_hub_3: i2c@98c000 { 2689 compatible = "qcom,geni-i2c-master-hub"; 2690 reg = <0 0x0098c000 0 0x4000>; 2691 2692 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>; 2693 2694 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 2695 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2696 clock-names = "se", 2697 "core"; 2698 2699 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2700 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2701 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2702 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2703 interconnect-names = "qup-core", 2704 "qup-config"; 2705 2706 power-domains = <&rpmhpd RPMHPD_CX>; 2707 2708 required-opps = <&rpmhpd_opp_low_svs>; 2709 2710 pinctrl-0 = <&hub_i2c3_data_clk>; 2711 pinctrl-names = "default"; 2712 2713 #address-cells = <1>; 2714 #size-cells = <0>; 2715 2716 status = "disabled"; 2717 }; 2718 2719 i2c_hub_4: i2c@990000 { 2720 compatible = "qcom,geni-i2c-master-hub"; 2721 reg = <0 0x00990000 0 0x4000>; 2722 2723 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>; 2724 2725 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 2726 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2727 clock-names = "se", 2728 "core"; 2729 2730 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2731 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2732 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2733 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2734 interconnect-names = "qup-core", 2735 "qup-config"; 2736 2737 power-domains = <&rpmhpd RPMHPD_CX>; 2738 2739 required-opps = <&rpmhpd_opp_low_svs>; 2740 2741 pinctrl-0 = <&hub_i2c4_data_clk>; 2742 pinctrl-names = "default"; 2743 2744 #address-cells = <1>; 2745 #size-cells = <0>; 2746 2747 status = "disabled"; 2748 }; 2749 2750 i2c_hub_5: i2c@994000 { 2751 compatible = "qcom,geni-i2c-master-hub"; 2752 reg = <0 0x00994000 0 0x4000>; 2753 2754 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH 0>; 2755 2756 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 2757 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2758 clock-names = "se", 2759 "core"; 2760 2761 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2762 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2763 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2764 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2765 interconnect-names = "qup-core", 2766 "qup-config"; 2767 2768 power-domains = <&rpmhpd RPMHPD_CX>; 2769 2770 required-opps = <&rpmhpd_opp_low_svs>; 2771 2772 pinctrl-0 = <&hub_i2c5_data_clk>; 2773 pinctrl-names = "default"; 2774 2775 #address-cells = <1>; 2776 #size-cells = <0>; 2777 2778 status = "disabled"; 2779 }; 2780 2781 i2c_hub_6: i2c@998000 { 2782 compatible = "qcom,geni-i2c-master-hub"; 2783 reg = <0 0x00998000 0 0x4000>; 2784 2785 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH 0>; 2786 2787 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 2788 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2789 clock-names = "se", 2790 "core"; 2791 2792 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2793 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2794 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2795 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2796 interconnect-names = "qup-core", 2797 "qup-config"; 2798 2799 power-domains = <&rpmhpd RPMHPD_CX>; 2800 2801 required-opps = <&rpmhpd_opp_low_svs>; 2802 2803 pinctrl-0 = <&hub_i2c6_data_clk>; 2804 pinctrl-names = "default"; 2805 2806 #address-cells = <1>; 2807 #size-cells = <0>; 2808 2809 status = "disabled"; 2810 }; 2811 2812 i2c_hub_7: i2c@99c000 { 2813 compatible = "qcom,geni-i2c-master-hub"; 2814 reg = <0 0x0099c000 0 0x4000>; 2815 2816 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; 2817 2818 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 2819 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2820 clock-names = "se", 2821 "core"; 2822 2823 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2824 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2825 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2826 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2827 interconnect-names = "qup-core", 2828 "qup-config"; 2829 2830 power-domains = <&rpmhpd RPMHPD_CX>; 2831 2832 required-opps = <&rpmhpd_opp_low_svs>; 2833 2834 pinctrl-0 = <&hub_i2c7_data_clk>; 2835 pinctrl-names = "default"; 2836 2837 #address-cells = <1>; 2838 #size-cells = <0>; 2839 2840 status = "disabled"; 2841 }; 2842 2843 i2c_hub_8: i2c@9a0000 { 2844 compatible = "qcom,geni-i2c-master-hub"; 2845 reg = <0 0x009a0000 0 0x4000>; 2846 2847 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH 0>; 2848 2849 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 2850 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2851 clock-names = "se", 2852 "core"; 2853 2854 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2855 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2856 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2857 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2858 interconnect-names = "qup-core", 2859 "qup-config"; 2860 2861 power-domains = <&rpmhpd RPMHPD_CX>; 2862 2863 required-opps = <&rpmhpd_opp_low_svs>; 2864 2865 pinctrl-0 = <&hub_i2c8_data_clk>; 2866 pinctrl-names = "default"; 2867 2868 #address-cells = <1>; 2869 #size-cells = <0>; 2870 2871 status = "disabled"; 2872 }; 2873 2874 i2c_hub_9: i2c@9a4000 { 2875 compatible = "qcom,geni-i2c-master-hub"; 2876 reg = <0 0x009a4000 0 0x4000>; 2877 2878 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH 0>; 2879 2880 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 2881 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2882 clock-names = "se", 2883 "core"; 2884 2885 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2886 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2887 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2888 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2889 interconnect-names = "qup-core", 2890 "qup-config"; 2891 2892 power-domains = <&rpmhpd RPMHPD_CX>; 2893 2894 required-opps = <&rpmhpd_opp_low_svs>; 2895 2896 pinctrl-0 = <&hub_i2c9_data_clk>; 2897 pinctrl-names = "default"; 2898 2899 #address-cells = <1>; 2900 #size-cells = <0>; 2901 2902 status = "disabled"; 2903 }; 2904 }; 2905 2906 gpi_dma1: dma-controller@a00000 { 2907 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 2908 reg = <0 0x00a00000 0 0x60000>; 2909 2910 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>, 2911 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>, 2912 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>, 2913 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>, 2914 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>, 2915 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>, 2916 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>, 2917 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>, 2918 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>, 2919 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>, 2920 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>, 2921 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 2922 2923 dma-channels = <12>; 2924 dma-channel-mask = <0xc>; 2925 #dma-cells = <3>; 2926 2927 iommus = <&apps_smmu 0xb6 0>; 2928 dma-coherent; 2929 2930 status = "disabled"; 2931 }; 2932 2933 qupv3_id_0: geniqup@ac0000 { 2934 compatible = "qcom,geni-se-qup"; 2935 reg = <0 0x00ac0000 0 0x2000>; 2936 2937 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 2938 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 2939 clock-names = "m-ahb", 2940 "s-ahb"; 2941 2942 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2943 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 2944 interconnect-names = "qup-core"; 2945 2946 iommus = <&apps_smmu 0xa3 0>; 2947 2948 dma-coherent; 2949 2950 #address-cells = <2>; 2951 #size-cells = <2>; 2952 ranges; 2953 2954 status = "disabled"; 2955 2956 i2c0: i2c@a80000 { 2957 compatible = "qcom,geni-i2c"; 2958 reg = <0 0x00a80000 0 0x4000>; 2959 2960 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 2961 2962 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2963 clock-names = "se"; 2964 2965 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2966 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2967 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2968 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2969 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2970 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2971 interconnect-names = "qup-core", 2972 "qup-config", 2973 "qup-memory"; 2974 2975 power-domains = <&rpmhpd RPMHPD_CX>; 2976 2977 operating-points-v2 = <&qup_opp_table_120mhz>; 2978 2979 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 2980 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 2981 dma-names = "tx", 2982 "rx"; 2983 2984 pinctrl-0 = <&qup_i2c0_data_clk>; 2985 pinctrl-names = "default"; 2986 2987 #address-cells = <1>; 2988 #size-cells = <0>; 2989 2990 status = "disabled"; 2991 }; 2992 2993 spi0: spi@a80000 { 2994 compatible = "qcom,geni-spi"; 2995 reg = <0 0x00a80000 0 0x4000>; 2996 2997 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 2998 2999 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 3000 clock-names = "se"; 3001 3002 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3003 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3004 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3005 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3006 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3007 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3008 interconnect-names = "qup-core", 3009 "qup-config", 3010 "qup-memory"; 3011 3012 power-domains = <&rpmhpd RPMHPD_CX>; 3013 3014 operating-points-v2 = <&qup_opp_table_120mhz>; 3015 3016 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 3017 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 3018 dma-names = "tx", 3019 "rx"; 3020 3021 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 3022 pinctrl-names = "default"; 3023 3024 #address-cells = <1>; 3025 #size-cells = <0>; 3026 3027 status = "disabled"; 3028 }; 3029 3030 i2c1: i2c@a84000 { 3031 compatible = "qcom,geni-i2c"; 3032 reg = <0 0x00a84000 0 0x4000>; 3033 3034 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 3035 3036 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 3037 clock-names = "se"; 3038 3039 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3040 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3041 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3042 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3043 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3044 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3045 interconnect-names = "qup-core", 3046 "qup-config", 3047 "qup-memory"; 3048 3049 power-domains = <&rpmhpd RPMHPD_CX>; 3050 3051 operating-points-v2 = <&qup_opp_table_120mhz>; 3052 3053 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 3054 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 3055 dma-names = "tx", 3056 "rx"; 3057 3058 pinctrl-0 = <&qup_i2c1_data_clk>; 3059 pinctrl-names = "default"; 3060 3061 #address-cells = <1>; 3062 #size-cells = <0>; 3063 3064 status = "disabled"; 3065 }; 3066 3067 spi1: spi@a84000 { 3068 compatible = "qcom,geni-spi"; 3069 reg = <0 0x00a84000 0 0x4000>; 3070 3071 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 3072 3073 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 3074 clock-names = "se"; 3075 3076 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3077 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3078 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3079 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3080 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3081 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3082 interconnect-names = "qup-core", 3083 "qup-config", 3084 "qup-memory"; 3085 3086 power-domains = <&rpmhpd RPMHPD_CX>; 3087 3088 operating-points-v2 = <&qup_opp_table_120mhz>; 3089 3090 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 3091 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 3092 dma-names = "tx", 3093 "rx"; 3094 3095 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 3096 pinctrl-names = "default"; 3097 3098 #address-cells = <1>; 3099 #size-cells = <0>; 3100 3101 status = "disabled"; 3102 }; 3103 3104 i2c2: i2c@a88000 { 3105 compatible = "qcom,geni-i2c"; 3106 reg = <0 0x00a88000 0 0x4000>; 3107 3108 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 3109 3110 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 3111 clock-names = "se"; 3112 3113 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3114 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3115 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3116 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3117 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3118 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3119 interconnect-names = "qup-core", 3120 "qup-config", 3121 "qup-memory"; 3122 3123 power-domains = <&rpmhpd RPMHPD_CX>; 3124 3125 operating-points-v2 = <&qup_opp_table_240mhz>; 3126 3127 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 3128 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 3129 dma-names = "tx", 3130 "rx"; 3131 3132 pinctrl-0 = <&qup_i2c2_data_clk>; 3133 pinctrl-names = "default"; 3134 3135 #address-cells = <1>; 3136 #size-cells = <0>; 3137 3138 status = "disabled"; 3139 }; 3140 3141 spi2: spi@a88000 { 3142 compatible = "qcom,geni-spi"; 3143 reg = <0 0x00a88000 0 0x4000>; 3144 3145 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 3146 3147 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 3148 clock-names = "se"; 3149 3150 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3151 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3152 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3153 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3154 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3155 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3156 interconnect-names = "qup-core", 3157 "qup-config", 3158 "qup-memory"; 3159 3160 power-domains = <&rpmhpd RPMHPD_CX>; 3161 3162 operating-points-v2 = <&qup_opp_table_240mhz>; 3163 3164 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 3165 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 3166 dma-names = "tx", 3167 "rx"; 3168 3169 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 3170 pinctrl-names = "default"; 3171 3172 #address-cells = <1>; 3173 #size-cells = <0>; 3174 3175 status = "disabled"; 3176 }; 3177 3178 i2c3: i2c@a8c000 { 3179 compatible = "qcom,geni-i2c"; 3180 reg = <0 0x00a8c000 0 0x4000>; 3181 3182 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 3183 3184 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 3185 clock-names = "se"; 3186 3187 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3188 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3189 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3190 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3191 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3192 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3193 interconnect-names = "qup-core", 3194 "qup-config", 3195 "qup-memory"; 3196 3197 power-domains = <&rpmhpd RPMHPD_CX>; 3198 3199 operating-points-v2 = <&qup_opp_table_100mhz>; 3200 3201 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 3202 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 3203 dma-names = "tx", 3204 "rx"; 3205 3206 pinctrl-0 = <&qup_i2c3_data_clk>; 3207 pinctrl-names = "default"; 3208 3209 #address-cells = <1>; 3210 #size-cells = <0>; 3211 3212 status = "disabled"; 3213 }; 3214 3215 spi3: spi@a8c000 { 3216 compatible = "qcom,geni-spi"; 3217 reg = <0 0x00a8c000 0 0x4000>; 3218 3219 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 3220 3221 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 3222 clock-names = "se"; 3223 3224 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3225 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3226 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3227 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3228 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3229 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3230 interconnect-names = "qup-core", 3231 "qup-config", 3232 "qup-memory"; 3233 3234 power-domains = <&rpmhpd RPMHPD_CX>; 3235 3236 operating-points-v2 = <&qup_opp_table_100mhz>; 3237 3238 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 3239 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 3240 dma-names = "tx", 3241 "rx"; 3242 3243 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 3244 pinctrl-names = "default"; 3245 3246 #address-cells = <1>; 3247 #size-cells = <0>; 3248 3249 status = "disabled"; 3250 }; 3251 3252 i2c4: i2c@a90000 { 3253 compatible = "qcom,geni-i2c"; 3254 reg = <0 0x00a90000 0 0x4000>; 3255 3256 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; 3257 3258 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 3259 clock-names = "se"; 3260 3261 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3262 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3263 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3264 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3265 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3266 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3267 interconnect-names = "qup-core", 3268 "qup-config", 3269 "qup-memory"; 3270 3271 power-domains = <&rpmhpd RPMHPD_CX>; 3272 3273 operating-points-v2 = <&qup_opp_table_120mhz>; 3274 3275 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 3276 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 3277 dma-names = "tx", 3278 "rx"; 3279 3280 pinctrl-0 = <&qup_i2c4_data_clk>; 3281 pinctrl-names = "default"; 3282 3283 #address-cells = <1>; 3284 #size-cells = <0>; 3285 3286 status = "disabled"; 3287 }; 3288 3289 spi4: spi@a90000 { 3290 compatible = "qcom,geni-spi"; 3291 reg = <0 0x00a90000 0 0x4000>; 3292 3293 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; 3294 3295 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 3296 clock-names = "se"; 3297 3298 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3299 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3300 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3301 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3302 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3303 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3304 interconnect-names = "qup-core", 3305 "qup-config", 3306 "qup-memory"; 3307 3308 power-domains = <&rpmhpd RPMHPD_CX>; 3309 3310 operating-points-v2 = <&qup_opp_table_120mhz>; 3311 3312 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 3313 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 3314 dma-names = "tx", 3315 "rx"; 3316 3317 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 3318 pinctrl-names = "default"; 3319 3320 #address-cells = <1>; 3321 #size-cells = <0>; 3322 3323 status = "disabled"; 3324 }; 3325 3326 i2c5: i2c@a94000 { 3327 compatible = "qcom,geni-i2c"; 3328 reg = <0 0x00a94000 0 0x4000>; 3329 3330 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; 3331 3332 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 3333 clock-names = "se"; 3334 3335 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3336 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3337 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3338 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3339 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3340 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3341 interconnect-names = "qup-core", 3342 "qup-config", 3343 "qup-memory"; 3344 3345 power-domains = <&rpmhpd RPMHPD_CX>; 3346 3347 operating-points-v2 = <&qup_opp_table_100mhz>; 3348 3349 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 3350 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 3351 dma-names = "tx", 3352 "rx"; 3353 3354 pinctrl-0 = <&qup_i2c5_data_clk>; 3355 pinctrl-names = "default"; 3356 3357 #address-cells = <1>; 3358 #size-cells = <0>; 3359 3360 status = "disabled"; 3361 }; 3362 3363 spi5: spi@a94000 { 3364 compatible = "qcom,geni-spi"; 3365 reg = <0 0x00a94000 0 0x4000>; 3366 3367 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; 3368 3369 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 3370 clock-names = "se"; 3371 3372 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3373 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3374 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3375 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3376 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3377 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3378 interconnect-names = "qup-core", 3379 "qup-config", 3380 "qup-memory"; 3381 3382 power-domains = <&rpmhpd RPMHPD_CX>; 3383 3384 operating-points-v2 = <&qup_opp_table_100mhz>; 3385 3386 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 3387 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 3388 dma-names = "tx", 3389 "rx"; 3390 3391 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 3392 pinctrl-names = "default"; 3393 3394 #address-cells = <1>; 3395 #size-cells = <0>; 3396 3397 status = "disabled"; 3398 }; 3399 3400 i2c6: i2c@a98000 { 3401 compatible = "qcom,geni-i2c"; 3402 reg = <0 0x00a98000 0 0x4000>; 3403 3404 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 3405 3406 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 3407 clock-names = "se"; 3408 3409 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3410 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3411 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3412 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3413 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3414 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3415 interconnect-names = "qup-core", 3416 "qup-config", 3417 "qup-memory"; 3418 3419 power-domains = <&rpmhpd RPMHPD_CX>; 3420 3421 operating-points-v2 = <&qup_opp_table_120mhz>; 3422 3423 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 3424 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 3425 dma-names = "tx", 3426 "rx"; 3427 3428 pinctrl-0 = <&qup_i2c6_data_clk>; 3429 pinctrl-names = "default"; 3430 3431 #address-cells = <1>; 3432 #size-cells = <0>; 3433 3434 status = "disabled"; 3435 }; 3436 3437 spi6: spi@a98000 { 3438 compatible = "qcom,geni-spi"; 3439 reg = <0 0x00a98000 0 0x4000>; 3440 3441 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 3442 3443 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 3444 clock-names = "se"; 3445 3446 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3447 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3448 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3449 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3450 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3451 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3452 interconnect-names = "qup-core", 3453 "qup-config", 3454 "qup-memory"; 3455 3456 power-domains = <&rpmhpd RPMHPD_CX>; 3457 3458 operating-points-v2 = <&qup_opp_table_120mhz>; 3459 3460 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 3461 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 3462 dma-names = "tx", 3463 "rx"; 3464 3465 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 3466 pinctrl-names = "default"; 3467 3468 #address-cells = <1>; 3469 #size-cells = <0>; 3470 3471 status = "disabled"; 3472 }; 3473 3474 i2c7: i2c@a9c000 { 3475 compatible = "qcom,geni-i2c"; 3476 reg = <0 0x00a9c000 0 0x4000>; 3477 3478 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>; 3479 3480 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 3481 clock-names = "se"; 3482 3483 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3484 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3485 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3486 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3487 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3488 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3489 interconnect-names = "qup-core", 3490 "qup-config", 3491 "qup-memory"; 3492 3493 power-domains = <&rpmhpd RPMHPD_CX>; 3494 3495 operating-points-v2 = <&qup_opp_table_100mhz>; 3496 3497 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 3498 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 3499 dma-names = "tx", 3500 "rx"; 3501 3502 pinctrl-0 = <&qup_i2c7_data_clk>; 3503 pinctrl-names = "default"; 3504 3505 #address-cells = <1>; 3506 #size-cells = <0>; 3507 3508 status = "disabled"; 3509 }; 3510 3511 spi7: spi@a9c000 { 3512 compatible = "qcom,geni-spi"; 3513 reg = <0 0x00a9c000 0 0x4000>; 3514 3515 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>; 3516 3517 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 3518 clock-names = "se"; 3519 3520 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3521 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3522 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3523 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3524 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3525 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3526 interconnect-names = "qup-core", 3527 "qup-config", 3528 "qup-memory"; 3529 3530 power-domains = <&rpmhpd RPMHPD_CX>; 3531 3532 operating-points-v2 = <&qup_opp_table_100mhz>; 3533 3534 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 3535 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 3536 dma-names = "tx", 3537 "rx"; 3538 3539 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 3540 pinctrl-names = "default"; 3541 3542 #address-cells = <1>; 3543 #size-cells = <0>; 3544 3545 status = "disabled"; 3546 }; 3547 }; 3548 3549 rng: rng@10c3000 { 3550 compatible = "qcom,sm8650-trng", "qcom,trng"; 3551 reg = <0 0x010c3000 0 0x1000>; 3552 }; 3553 3554 cnoc_main: interconnect@1500000 { 3555 compatible = "qcom,sm8650-cnoc-main"; 3556 reg = <0 0x01500000 0 0x14080>; 3557 3558 qcom,bcm-voters = <&apps_bcm_voter>; 3559 3560 #interconnect-cells = <2>; 3561 }; 3562 3563 config_noc: interconnect@1600000 { 3564 compatible = "qcom,sm8650-config-noc"; 3565 reg = <0 0x01600000 0 0x6200>; 3566 3567 qcom,bcm-voters = <&apps_bcm_voter>; 3568 3569 #interconnect-cells = <2>; 3570 }; 3571 3572 system_noc: interconnect@1680000 { 3573 compatible = "qcom,sm8650-system-noc"; 3574 reg = <0 0x01680000 0 0x1d080>; 3575 3576 qcom,bcm-voters = <&apps_bcm_voter>; 3577 3578 #interconnect-cells = <2>; 3579 }; 3580 3581 pcie_noc: interconnect@16c0000 { 3582 compatible = "qcom,sm8650-pcie-anoc"; 3583 reg = <0 0x016c0000 0 0x12200>; 3584 3585 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 3586 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 3587 3588 qcom,bcm-voters = <&apps_bcm_voter>; 3589 3590 #interconnect-cells = <2>; 3591 }; 3592 3593 aggre1_noc: interconnect@16e0000 { 3594 compatible = "qcom,sm8650-aggre1-noc"; 3595 reg = <0 0x016e0000 0 0x16400>; 3596 3597 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3598 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 3599 3600 qcom,bcm-voters = <&apps_bcm_voter>; 3601 3602 #interconnect-cells = <2>; 3603 }; 3604 3605 aggre2_noc: interconnect@1700000 { 3606 compatible = "qcom,sm8650-aggre2-noc"; 3607 reg = <0 0x01700000 0 0x1e400>; 3608 3609 clocks = <&rpmhcc RPMH_IPA_CLK>; 3610 3611 qcom,bcm-voters = <&apps_bcm_voter>; 3612 3613 #interconnect-cells = <2>; 3614 }; 3615 3616 mmss_noc: interconnect@1780000 { 3617 compatible = "qcom,sm8650-mmss-noc"; 3618 reg = <0 0x01780000 0 0x5b800>; 3619 3620 qcom,bcm-voters = <&apps_bcm_voter>; 3621 3622 #interconnect-cells = <2>; 3623 }; 3624 3625 pcie0: pcie@1c00000 { 3626 device_type = "pci"; 3627 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 3628 reg = <0 0x01c00000 0 0x3000>, 3629 <0 0x60000000 0 0xf1d>, 3630 <0 0x60000f20 0 0xa8>, 3631 <0 0x60001000 0 0x1000>, 3632 <0 0x60100000 0 0x100000>; 3633 reg-names = "parf", "dbi", "elbi", "atu", "config"; 3634 3635 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>, 3636 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>, 3637 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>, 3638 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>, 3639 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>, 3640 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>, 3641 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>, 3642 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>, 3643 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>; 3644 interrupt-names = "msi0", 3645 "msi1", 3646 "msi2", 3647 "msi3", 3648 "msi4", 3649 "msi5", 3650 "msi6", 3651 "msi7", 3652 "global"; 3653 3654 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 3655 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 3656 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 3657 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 3658 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 3659 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 3660 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 3661 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 3662 clock-names = "aux", 3663 "cfg", 3664 "bus_master", 3665 "bus_slave", 3666 "slave_q2a", 3667 "ddrss_sf_tbu", 3668 "noc_aggr", 3669 "cnoc_sf_axi"; 3670 3671 resets = <&gcc GCC_PCIE_0_BCR>; 3672 reset-names = "pci"; 3673 3674 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 3675 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3676 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3677 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 3678 interconnect-names = "pcie-mem", 3679 "cpu-pcie"; 3680 3681 power-domains = <&gcc PCIE_0_GDSC>; 3682 3683 operating-points-v2 = <&pcie0_opp_table>; 3684 3685 iommu-map = <0 &apps_smmu 0x1400 0x0 0x1>, 3686 <0x100 &apps_smmu 0x1401 0x0 0x1>; 3687 3688 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, 3689 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, 3690 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, 3691 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 3692 interrupt-map-mask = <0 0 0 0x7>; 3693 #interrupt-cells = <1>; 3694 3695 msi-map = <0x0 &gic_its 0x1400 0x1>, 3696 <0x100 &gic_its 0x1401 0x1>; 3697 msi-map-mask = <0xff00>; 3698 3699 linux,pci-domain = <0>; 3700 num-lanes = <2>; 3701 bus-range = <0 0xff>; 3702 3703 phys = <&pcie0_phy>; 3704 phy-names = "pciephy"; 3705 3706 #address-cells = <3>; 3707 #size-cells = <2>; 3708 ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, 3709 <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>; 3710 3711 dma-coherent; 3712 3713 status = "disabled"; 3714 3715 pcie0_opp_table: opp-table { 3716 compatible = "operating-points-v2"; 3717 3718 /* 2.5 GT/s x1 */ 3719 opp-2500000-1 { 3720 opp-hz = /bits/ 64 <2500000>; 3721 required-opps = <&rpmhpd_opp_low_svs>; 3722 opp-peak-kBps = <250000 1>; 3723 opp-level = <1>; 3724 }; 3725 3726 /* 2.5 GT/s x2 */ 3727 opp-5000000-1 { 3728 opp-hz = /bits/ 64 <5000000>; 3729 required-opps = <&rpmhpd_opp_low_svs>; 3730 opp-peak-kBps = <500000 1>; 3731 opp-level = <1>; 3732 }; 3733 3734 /* 5 GT/s x1 */ 3735 opp-5000000-2 { 3736 opp-hz = /bits/ 64 <5000000>; 3737 required-opps = <&rpmhpd_opp_low_svs>; 3738 opp-peak-kBps = <500000 1>; 3739 opp-level = <2>; 3740 }; 3741 3742 /* 5 GT/s x2 */ 3743 opp-10000000-2 { 3744 opp-hz = /bits/ 64 <10000000>; 3745 required-opps = <&rpmhpd_opp_low_svs>; 3746 opp-peak-kBps = <1000000 1>; 3747 opp-level = <2>; 3748 }; 3749 3750 /* 8 GT/s x1 */ 3751 opp-8000000-3 { 3752 opp-hz = /bits/ 64 <8000000>; 3753 required-opps = <&rpmhpd_opp_nom>; 3754 opp-peak-kBps = <984500 1>; 3755 opp-level = <3>; 3756 }; 3757 3758 /* 8 GT/s x2 */ 3759 opp-16000000-3 { 3760 opp-hz = /bits/ 64 <16000000>; 3761 required-opps = <&rpmhpd_opp_nom>; 3762 opp-peak-kBps = <1969000 1>; 3763 opp-level = <3>; 3764 }; 3765 }; 3766 3767 pcieport0: pcie@0 { 3768 device_type = "pci"; 3769 reg = <0x0 0x0 0x0 0x0 0x0>; 3770 bus-range = <0x01 0xff>; 3771 3772 #address-cells = <3>; 3773 #size-cells = <2>; 3774 ranges; 3775 }; 3776 }; 3777 3778 pcie0_phy: phy@1c06000 { 3779 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy"; 3780 reg = <0 0x01c06000 0 0x2000>; 3781 3782 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 3783 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 3784 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 3785 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 3786 <&gcc GCC_PCIE_0_PIPE_CLK>; 3787 clock-names = "aux", 3788 "cfg_ahb", 3789 "ref", 3790 "rchng", 3791 "pipe"; 3792 3793 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 3794 assigned-clock-rates = <100000000>; 3795 3796 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 3797 reset-names = "phy"; 3798 3799 power-domains = <&gcc PCIE_0_PHY_GDSC>; 3800 3801 #clock-cells = <0>; 3802 clock-output-names = "pcie0_pipe_clk"; 3803 3804 #phy-cells = <0>; 3805 3806 status = "disabled"; 3807 }; 3808 3809 pcie1: pcie@1c08000 { 3810 device_type = "pci"; 3811 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 3812 reg = <0 0x01c08000 0 0x3000>, 3813 <0 0x40000000 0 0xf1d>, 3814 <0 0x40000f20 0 0xa8>, 3815 <0 0x40001000 0 0x1000>, 3816 <0 0x40100000 0 0x100000>; 3817 reg-names = "parf", 3818 "dbi", 3819 "elbi", 3820 "atu", 3821 "config"; 3822 3823 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>, 3824 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>, 3825 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>, 3826 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 0>, 3827 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>, 3828 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 0>, 3829 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, 3830 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH 0>, 3831 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 3832 interrupt-names = "msi0", 3833 "msi1", 3834 "msi2", 3835 "msi3", 3836 "msi4", 3837 "msi5", 3838 "msi6", 3839 "msi7", 3840 "global"; 3841 3842 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 3843 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 3844 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 3845 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 3846 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 3847 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 3848 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 3849 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 3850 clock-names = "aux", 3851 "cfg", 3852 "bus_master", 3853 "bus_slave", 3854 "slave_q2a", 3855 "ddrss_sf_tbu", 3856 "noc_aggr", 3857 "cnoc_sf_axi"; 3858 3859 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 3860 assigned-clock-rates = <19200000>; 3861 3862 resets = <&gcc GCC_PCIE_1_BCR>, 3863 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 3864 reset-names = "pci", 3865 "link_down"; 3866 3867 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 3868 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3869 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3870 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3871 interconnect-names = "pcie-mem", 3872 "cpu-pcie"; 3873 3874 power-domains = <&gcc PCIE_1_GDSC>; 3875 3876 operating-points-v2 = <&pcie1_opp_table>; 3877 3878 iommu-map = <0 &apps_smmu 0x1480 0x0 0x1>, 3879 <0x100 &apps_smmu 0x1481 0x0 0x1>; 3880 3881 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, 3882 <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, 3883 <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, 3884 <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; 3885 interrupt-map-mask = <0 0 0 0x7>; 3886 #interrupt-cells = <1>; 3887 3888 msi-map = <0x0 &gic_its 0x1480 0x1>, 3889 <0x100 &gic_its 0x1481 0x1>; 3890 msi-map-mask = <0xff00>; 3891 3892 linux,pci-domain = <1>; 3893 num-lanes = <2>; 3894 bus-range = <0 0xff>; 3895 3896 phys = <&pcie1_phy>; 3897 phy-names = "pciephy"; 3898 3899 dma-coherent; 3900 3901 #address-cells = <3>; 3902 #size-cells = <2>; 3903 ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, 3904 <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; 3905 3906 status = "disabled"; 3907 3908 pcie1_opp_table: opp-table { 3909 compatible = "operating-points-v2"; 3910 3911 /* 2.5 GT/s x1 */ 3912 opp-2500000-1 { 3913 opp-hz = /bits/ 64 <2500000>; 3914 required-opps = <&rpmhpd_opp_low_svs>; 3915 opp-peak-kBps = <250000 1>; 3916 opp-level = <1>; 3917 }; 3918 3919 /* 2.5 GT/s x2 */ 3920 opp-5000000-1 { 3921 opp-hz = /bits/ 64 <5000000>; 3922 required-opps = <&rpmhpd_opp_low_svs>; 3923 opp-peak-kBps = <500000 1>; 3924 opp-level = <1>; 3925 }; 3926 3927 /* 5 GT/s x1 */ 3928 opp-5000000-2 { 3929 opp-hz = /bits/ 64 <5000000>; 3930 required-opps = <&rpmhpd_opp_low_svs>; 3931 opp-peak-kBps = <500000 1>; 3932 opp-level = <2>; 3933 }; 3934 3935 /* 5 GT/s x2 */ 3936 opp-10000000-2 { 3937 opp-hz = /bits/ 64 <10000000>; 3938 required-opps = <&rpmhpd_opp_low_svs>; 3939 opp-peak-kBps = <1000000 1>; 3940 opp-level = <2>; 3941 }; 3942 3943 /* 8 GT/s x1 */ 3944 opp-8000000-3 { 3945 opp-hz = /bits/ 64 <8000000>; 3946 required-opps = <&rpmhpd_opp_nom>; 3947 opp-peak-kBps = <984500 1>; 3948 opp-level = <3>; 3949 }; 3950 3951 /* 8 GT/s x2 */ 3952 opp-16000000-3 { 3953 opp-hz = /bits/ 64 <16000000>; 3954 required-opps = <&rpmhpd_opp_nom>; 3955 opp-peak-kBps = <1969000 1>; 3956 opp-level = <3>; 3957 }; 3958 3959 /* 16 GT/s x1 */ 3960 opp-16000000-4 { 3961 opp-hz = /bits/ 64 <16000000>; 3962 required-opps = <&rpmhpd_opp_nom>; 3963 opp-peak-kBps = <1969000 1>; 3964 opp-level = <4>; 3965 }; 3966 3967 /* 16 GT/s x2 */ 3968 opp-32000000-4 { 3969 opp-hz = /bits/ 64 <32000000>; 3970 required-opps = <&rpmhpd_opp_nom>; 3971 opp-peak-kBps = <3938000 1>; 3972 opp-level = <4>; 3973 }; 3974 }; 3975 3976 pcie1_port0: pcie@0 { 3977 device_type = "pci"; 3978 reg = <0x0 0x0 0x0 0x0 0x0>; 3979 bus-range = <0x01 0xff>; 3980 3981 #address-cells = <3>; 3982 #size-cells = <2>; 3983 ranges; 3984 }; 3985 }; 3986 3987 pcie1_phy: phy@1c0e000 { 3988 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy"; 3989 reg = <0 0x01c0e000 0 0x2000>; 3990 3991 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 3992 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 3993 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 3994 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 3995 <&gcc GCC_PCIE_1_PIPE_CLK>; 3996 clock-names = "aux", 3997 "cfg_ahb", 3998 "ref", 3999 "rchng", 4000 "pipe"; 4001 4002 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 4003 assigned-clock-rates = <100000000>; 4004 4005 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 4006 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 4007 reset-names = "phy", 4008 "phy_nocsr"; 4009 4010 power-domains = <&gcc PCIE_1_PHY_GDSC>; 4011 4012 #clock-cells = <1>; 4013 clock-output-names = "pcie1_pipe_clk"; 4014 4015 #phy-cells = <0>; 4016 4017 status = "disabled"; 4018 }; 4019 4020 ufs_mem_phy: phy@1d80000 { 4021 compatible = "qcom,sm8650-qmp-ufs-phy"; 4022 reg = <0 0x01d80000 0 0x2000>; 4023 4024 clocks = <&rpmhcc RPMH_CXO_CLK>, 4025 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 4026 <&tcsr TCSR_UFS_CLKREF_EN>; 4027 clock-names = "ref", 4028 "ref_aux", 4029 "qref"; 4030 4031 resets = <&ufs_mem_hc 0>; 4032 reset-names = "ufsphy"; 4033 4034 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 4035 4036 #clock-cells = <1>; 4037 #phy-cells = <0>; 4038 4039 status = "disabled"; 4040 }; 4041 4042 ufs_mem_hc: ufshc@1d84000 { 4043 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 4044 reg = <0 0x01d84000 0 0x3000>; 4045 4046 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 4047 4048 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 4049 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 4050 <&gcc GCC_UFS_PHY_AHB_CLK>, 4051 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 4052 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 4053 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 4054 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 4055 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 4056 clock-names = "core_clk", 4057 "bus_aggr_clk", 4058 "iface_clk", 4059 "core_clk_unipro", 4060 "ref_clk", 4061 "tx_lane0_sync_clk", 4062 "rx_lane0_sync_clk", 4063 "rx_lane1_sync_clk"; 4064 4065 resets = <&gcc GCC_UFS_PHY_BCR>; 4066 reset-names = "rst"; 4067 4068 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 4069 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4070 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4071 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4072 interconnect-names = "ufs-ddr", 4073 "cpu-ufs"; 4074 4075 power-domains = <&gcc UFS_PHY_GDSC>; 4076 required-opps = <&rpmhpd_opp_nom>; 4077 4078 operating-points-v2 = <&ufs_opp_table>; 4079 4080 iommus = <&apps_smmu 0x60 0>; 4081 4082 dma-coherent; 4083 4084 lanes-per-direction = <2>; 4085 qcom,ice = <&ice>; 4086 4087 phys = <&ufs_mem_phy>; 4088 phy-names = "ufsphy"; 4089 4090 #reset-cells = <1>; 4091 4092 status = "disabled"; 4093 4094 ufs_opp_table: opp-table { 4095 compatible = "operating-points-v2"; 4096 4097 opp-100000000 { 4098 opp-hz = /bits/ 64 <100000000>, 4099 /bits/ 64 <0>, 4100 /bits/ 64 <0>, 4101 /bits/ 64 <100000000>, 4102 /bits/ 64 <0>, 4103 /bits/ 64 <0>, 4104 /bits/ 64 <0>, 4105 /bits/ 64 <0>; 4106 required-opps = <&rpmhpd_opp_low_svs>; 4107 }; 4108 4109 opp-201500000 { 4110 opp-hz = /bits/ 64 <201500000>, 4111 /bits/ 64 <0>, 4112 /bits/ 64 <0>, 4113 /bits/ 64 <201500000>, 4114 /bits/ 64 <0>, 4115 /bits/ 64 <0>, 4116 /bits/ 64 <0>, 4117 /bits/ 64 <0>; 4118 required-opps = <&rpmhpd_opp_svs>; 4119 }; 4120 4121 opp-403000000 { 4122 opp-hz = /bits/ 64 <403000000>, 4123 /bits/ 64 <0>, 4124 /bits/ 64 <0>, 4125 /bits/ 64 <403000000>, 4126 /bits/ 64 <0>, 4127 /bits/ 64 <0>, 4128 /bits/ 64 <0>, 4129 /bits/ 64 <0>; 4130 required-opps = <&rpmhpd_opp_nom>; 4131 }; 4132 }; 4133 }; 4134 4135 ice: crypto@1d88000 { 4136 compatible = "qcom,sm8650-inline-crypto-engine", 4137 "qcom,inline-crypto-engine"; 4138 reg = <0 0x01d88000 0 0x18000>; 4139 4140 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, 4141 <&gcc GCC_UFS_PHY_AHB_CLK>; 4142 clock-names = "core", 4143 "iface"; 4144 power-domains = <&gcc UFS_PHY_GDSC>; 4145 }; 4146 4147 cryptobam: dma-controller@1dc4000 { 4148 compatible = "qcom,bam-v1.7.0"; 4149 reg = <0 0x01dc4000 0 0x28000>; 4150 4151 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; 4152 4153 #dma-cells = <1>; 4154 4155 iommus = <&apps_smmu 0x480 0>, 4156 <&apps_smmu 0x481 0>; 4157 4158 qcom,ee = <0>; 4159 qcom,num-ees = <4>; 4160 num-channels = <20>; 4161 qcom,controlled-remotely; 4162 }; 4163 4164 crypto: crypto@1dfa000 { 4165 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; 4166 reg = <0 0x01dfa000 0 0x6000>; 4167 4168 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 4169 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4170 interconnect-names = "memory"; 4171 4172 dmas = <&cryptobam 4>, <&cryptobam 5>; 4173 dma-names = "rx", "tx"; 4174 4175 iommus = <&apps_smmu 0x480 0>, 4176 <&apps_smmu 0x481 0>; 4177 }; 4178 4179 tcsr_mutex: hwlock@1f40000 { 4180 compatible = "qcom,tcsr-mutex"; 4181 reg = <0 0x01f40000 0 0x20000>; 4182 4183 #hwlock-cells = <1>; 4184 }; 4185 4186 tcsr: clock-controller@1fc0000 { 4187 compatible = "qcom,sm8650-tcsr", "syscon"; 4188 reg = <0 0x01fc0000 0 0xa0000>; 4189 4190 clocks = <&rpmhcc RPMH_CXO_CLK>; 4191 4192 #clock-cells = <1>; 4193 #reset-cells = <1>; 4194 }; 4195 4196 gpu: gpu@3d00000 { 4197 compatible = "qcom,adreno-43051401", "qcom,adreno"; 4198 reg = <0x0 0x03d00000 0x0 0x40000>, 4199 <0x0 0x03d9e000 0x0 0x2000>, 4200 <0x0 0x03d61000 0x0 0x800>; 4201 reg-names = "kgsl_3d0_reg_memory", 4202 "cx_mem", 4203 "cx_dbgc"; 4204 4205 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; 4206 4207 iommus = <&adreno_smmu 0 0x0>, 4208 <&adreno_smmu 1 0x0>; 4209 4210 operating-points-v2 = <&gpu_opp_table>; 4211 4212 qcom,gmu = <&gmu>; 4213 #cooling-cells = <2>; 4214 4215 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4216 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4217 interconnect-names = "gfx-mem"; 4218 4219 status = "disabled"; 4220 4221 gpu_zap_shader: zap-shader { 4222 memory-region = <&gpu_micro_code_mem>; 4223 }; 4224 4225 /* Speedbin needs more work on A740+, keep only lower freqs */ 4226 gpu_opp_table: opp-table { 4227 compatible = "operating-points-v2-adreno", 4228 "operating-points-v2"; 4229 4230 opp-231000000 { 4231 opp-hz = /bits/ 64 <231000000>; 4232 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 4233 opp-peak-kBps = <2136718>; 4234 qcom,opp-acd-level = <0xc82f5ffd>; 4235 }; 4236 4237 opp-310000000 { 4238 opp-hz = /bits/ 64 <310000000>; 4239 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4240 opp-peak-kBps = <2136718>; 4241 qcom,opp-acd-level = <0xc82c5ffd>; 4242 }; 4243 4244 opp-366000000 { 4245 opp-hz = /bits/ 64 <366000000>; 4246 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 4247 opp-peak-kBps = <6074218>; 4248 qcom,opp-acd-level = <0xc02e5ffd>; 4249 }; 4250 4251 opp-422000000 { 4252 opp-hz = /bits/ 64 <422000000>; 4253 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4254 opp-peak-kBps = <8171875>; 4255 qcom,opp-acd-level = <0xc02d5ffd>; 4256 }; 4257 4258 opp-500000000 { 4259 opp-hz = /bits/ 64 <500000000>; 4260 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4261 opp-peak-kBps = <8171875>; 4262 qcom,opp-acd-level = <0xc02a5ffd>; 4263 }; 4264 4265 opp-578000000 { 4266 opp-hz = /bits/ 64 <578000000>; 4267 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4268 opp-peak-kBps = <8171875>; 4269 qcom,opp-acd-level = <0x882c5ffd>; 4270 }; 4271 4272 opp-629000000 { 4273 opp-hz = /bits/ 64 <629000000>; 4274 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4275 opp-peak-kBps = <10687500>; 4276 qcom,opp-acd-level = <0x882a5ffd>; 4277 }; 4278 4279 opp-680000000 { 4280 opp-hz = /bits/ 64 <680000000>; 4281 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4282 opp-peak-kBps = <12449218>; 4283 qcom,opp-acd-level = <0x882a5ffd>; 4284 }; 4285 4286 opp-720000000 { 4287 opp-hz = /bits/ 64 <720000000>; 4288 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4289 opp-peak-kBps = <12449218>; 4290 qcom,opp-acd-level = <0x882a5ffd>; 4291 }; 4292 4293 opp-770000000 { 4294 opp-hz = /bits/ 64 <770000000>; 4295 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4296 opp-peak-kBps = <12449218>; 4297 qcom,opp-acd-level = <0x882a5ffd>; 4298 }; 4299 4300 opp-834000000 { 4301 opp-hz = /bits/ 64 <834000000>; 4302 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4303 opp-peak-kBps = <14398437>; 4304 qcom,opp-acd-level = <0x882a5ffd>; 4305 }; 4306 }; 4307 }; 4308 4309 gmu: gmu@3d6a000 { 4310 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; 4311 reg = <0x0 0x03d6a000 0x0 0x35000>, 4312 <0x0 0x03d50000 0x0 0x10000>, 4313 <0x0 0x0b280000 0x0 0x10000>; 4314 reg-names = "gmu", "rscc", "gmu_pdc"; 4315 4316 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>, 4317 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 4318 interrupt-names = "hfi", "gmu"; 4319 4320 clocks = <&gpucc GPU_CC_AHB_CLK>, 4321 <&gpucc GPU_CC_CX_GMU_CLK>, 4322 <&gpucc GPU_CC_CXO_CLK>, 4323 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4324 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4325 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4326 <&gpucc GPU_CC_DEMET_CLK>; 4327 clock-names = "ahb", 4328 "gmu", 4329 "cxo", 4330 "axi", 4331 "memnoc", 4332 "hub", 4333 "demet"; 4334 4335 power-domains = <&gpucc GPU_CX_GDSC>, 4336 <&gpucc GPU_GX_GDSC>; 4337 power-domain-names = "cx", 4338 "gx"; 4339 4340 iommus = <&adreno_smmu 5 0x0>; 4341 4342 qcom,qmp = <&aoss_qmp>; 4343 4344 operating-points-v2 = <&gmu_opp_table>; 4345 4346 gmu_opp_table: opp-table { 4347 compatible = "operating-points-v2"; 4348 4349 opp-260000000 { 4350 opp-hz = /bits/ 64 <260000000>; 4351 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4352 }; 4353 4354 opp-625000000 { 4355 opp-hz = /bits/ 64 <625000000>; 4356 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4357 }; 4358 }; 4359 }; 4360 4361 gpucc: clock-controller@3d90000 { 4362 compatible = "qcom,sm8650-gpucc"; 4363 reg = <0 0x03d90000 0 0xa000>; 4364 4365 clocks = <&bi_tcxo_div2>, 4366 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4367 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4368 4369 #clock-cells = <1>; 4370 #reset-cells = <1>; 4371 #power-domain-cells = <1>; 4372 }; 4373 4374 adreno_smmu: iommu@3da0000 { 4375 compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", 4376 "qcom,smmu-500", "arm,mmu-500"; 4377 reg = <0x0 0x03da0000 0x0 0x40000>; 4378 #iommu-cells = <2>; 4379 #global-interrupts = <1>; 4380 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>, 4381 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>, 4382 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>, 4383 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>, 4384 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>, 4385 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>, 4386 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>, 4387 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>, 4388 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>, 4389 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>, 4390 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>, 4391 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>, 4392 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>, 4393 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>, 4394 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>, 4395 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>, 4396 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>, 4397 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>, 4398 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>, 4399 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>, 4400 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, 4401 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>, 4402 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>, 4403 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>, 4404 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>, 4405 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>; 4406 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4407 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4408 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4409 <&gpucc GPU_CC_AHB_CLK>; 4410 clock-names = "hlos", 4411 "bus", 4412 "iface", 4413 "ahb"; 4414 power-domains = <&gpucc GPU_CX_GDSC>; 4415 dma-coherent; 4416 }; 4417 4418 ipa: ipa@3f40000 { 4419 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; 4420 4421 iommus = <&apps_smmu 0x4a0 0x0>, 4422 <&apps_smmu 0x4a2 0x0>; 4423 reg = <0 0x3f40000 0 0x10000>, 4424 <0 0x3f50000 0 0x5000>, 4425 <0 0x3e04000 0 0xfc000>; 4426 reg-names = "ipa-reg", 4427 "ipa-shared", 4428 "gsi"; 4429 4430 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>, 4431 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>, 4432 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4433 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 4434 interrupt-names = "ipa", 4435 "gsi", 4436 "ipa-clock-query", 4437 "ipa-setup-ready"; 4438 4439 clocks = <&rpmhcc RPMH_IPA_CLK>; 4440 clock-names = "core"; 4441 4442 interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS 4443 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4444 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4445 &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4446 interconnect-names = "memory", 4447 "config"; 4448 4449 qcom,qmp = <&aoss_qmp>; 4450 4451 qcom,smem-states = <&ipa_smp2p_out 0>, 4452 <&ipa_smp2p_out 1>; 4453 qcom,smem-state-names = "ipa-clock-enabled-valid", 4454 "ipa-clock-enabled"; 4455 4456 qcom,gsi-loader = "self"; 4457 memory-region = <&ipa_fw_mem>; 4458 4459 sram = <&ipa_modem_tables>; 4460 4461 status = "disabled"; 4462 }; 4463 4464 remoteproc_mpss: remoteproc@4080000 { 4465 compatible = "qcom,sm8650-mpss-pas"; 4466 reg = <0x0 0x04080000 0x0 0x10000>; 4467 4468 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, 4469 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 4470 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 4471 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 4472 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 4473 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 4474 interrupt-names = "wdog", 4475 "fatal", 4476 "ready", 4477 "handover", 4478 "stop-ack", 4479 "shutdown-ack"; 4480 4481 clocks = <&rpmhcc RPMH_CXO_CLK>; 4482 clock-names = "xo"; 4483 4484 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 4485 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4486 4487 power-domains = <&rpmhpd RPMHPD_CX>, 4488 <&rpmhpd RPMHPD_MSS>; 4489 power-domain-names = "cx", 4490 "mss"; 4491 4492 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, 4493 <&mpss_dsm_mem>, <&mpss_dsm_mem_2>, 4494 <&qlink_logging_mem>; 4495 4496 qcom,qmp = <&aoss_qmp>; 4497 4498 qcom,smem-states = <&smp2p_modem_out 0>; 4499 qcom,smem-state-names = "stop"; 4500 4501 status = "disabled"; 4502 4503 glink-edge { 4504 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 4505 IPCC_MPROC_SIGNAL_GLINK_QMP 4506 IRQ_TYPE_EDGE_RISING>; 4507 4508 mboxes = <&ipcc IPCC_CLIENT_MPSS 4509 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4510 4511 qcom,remote-pid = <1>; 4512 4513 label = "mpss"; 4514 }; 4515 }; 4516 4517 remoteproc_adsp: remoteproc@6800000 { 4518 compatible = "qcom,sm8650-adsp-pas"; 4519 reg = <0x0 0x06800000 0x0 0x10000>; 4520 4521 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4522 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4523 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4524 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4525 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4526 interrupt-names = "wdog", 4527 "fatal", 4528 "ready", 4529 "handover", 4530 "stop-ack"; 4531 4532 clocks = <&rpmhcc RPMH_CXO_CLK>; 4533 clock-names = "xo"; 4534 4535 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 4536 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4537 4538 power-domains = <&rpmhpd RPMHPD_LCX>, 4539 <&rpmhpd RPMHPD_LMX>; 4540 power-domain-names = "lcx", 4541 "lmx"; 4542 4543 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 4544 4545 qcom,qmp = <&aoss_qmp>; 4546 4547 qcom,smem-states = <&smp2p_adsp_out 0>; 4548 qcom,smem-state-names = "stop"; 4549 4550 status = "disabled"; 4551 4552 glink-edge { 4553 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4554 IPCC_MPROC_SIGNAL_GLINK_QMP 4555 IRQ_TYPE_EDGE_RISING>; 4556 4557 mboxes = <&ipcc IPCC_CLIENT_LPASS 4558 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4559 4560 qcom,remote-pid = <2>; 4561 4562 label = "lpass"; 4563 4564 fastrpc { 4565 compatible = "qcom,fastrpc"; 4566 4567 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4568 4569 label = "adsp"; 4570 4571 qcom,non-secure-domain; 4572 4573 #address-cells = <1>; 4574 #size-cells = <0>; 4575 4576 compute-cb@3 { 4577 compatible = "qcom,fastrpc-compute-cb"; 4578 reg = <3>; 4579 4580 iommus = <&apps_smmu 0x1003 0x80>, 4581 <&apps_smmu 0x1043 0x20>; 4582 dma-coherent; 4583 }; 4584 4585 compute-cb@4 { 4586 compatible = "qcom,fastrpc-compute-cb"; 4587 reg = <4>; 4588 4589 iommus = <&apps_smmu 0x1004 0x80>, 4590 <&apps_smmu 0x1044 0x20>; 4591 dma-coherent; 4592 }; 4593 4594 compute-cb@5 { 4595 compatible = "qcom,fastrpc-compute-cb"; 4596 reg = <5>; 4597 4598 iommus = <&apps_smmu 0x1005 0x80>, 4599 <&apps_smmu 0x1045 0x20>; 4600 dma-coherent; 4601 }; 4602 4603 compute-cb@6 { 4604 compatible = "qcom,fastrpc-compute-cb"; 4605 reg = <6>; 4606 4607 iommus = <&apps_smmu 0x1006 0x80>, 4608 <&apps_smmu 0x1046 0x20>; 4609 dma-coherent; 4610 }; 4611 4612 compute-cb@7 { 4613 compatible = "qcom,fastrpc-compute-cb"; 4614 reg = <7>; 4615 4616 iommus = <&apps_smmu 0x1007 0x40>, 4617 <&apps_smmu 0x1067 0x0>, 4618 <&apps_smmu 0x1087 0x0>; 4619 dma-coherent; 4620 }; 4621 }; 4622 4623 gpr { 4624 compatible = "qcom,gpr"; 4625 qcom,glink-channels = "adsp_apps"; 4626 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4627 qcom,intents = <512 20>; 4628 #address-cells = <1>; 4629 #size-cells = <0>; 4630 4631 q6apm: service@1 { 4632 compatible = "qcom,q6apm"; 4633 reg = <GPR_APM_MODULE_IID>; 4634 #sound-dai-cells = <0>; 4635 qcom,protection-domain = "avs/audio", 4636 "msm/adsp/audio_pd"; 4637 4638 q6apmbedai: bedais { 4639 compatible = "qcom,q6apm-lpass-dais"; 4640 #sound-dai-cells = <1>; 4641 }; 4642 4643 q6apmdai: dais { 4644 compatible = "qcom,q6apm-dais"; 4645 iommus = <&apps_smmu 0x1001 0x80>, 4646 <&apps_smmu 0x1061 0x0>; 4647 }; 4648 }; 4649 4650 q6prm: service@2 { 4651 compatible = "qcom,q6prm"; 4652 reg = <GPR_PRM_MODULE_IID>; 4653 qcom,protection-domain = "avs/audio", 4654 "msm/adsp/audio_pd"; 4655 4656 q6prmcc: clock-controller { 4657 compatible = "qcom,q6prm-lpass-clocks"; 4658 #clock-cells = <2>; 4659 }; 4660 }; 4661 }; 4662 }; 4663 }; 4664 4665 lpass_wsa2macro: codec@6aa0000 { 4666 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4667 reg = <0 0x06aa0000 0 0x1000>; 4668 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4669 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4670 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4671 <&lpass_vamacro>; 4672 clock-names = "mclk", 4673 "macro", 4674 "dcodec", 4675 "fsgen"; 4676 4677 #clock-cells = <0>; 4678 clock-output-names = "wsa2-mclk"; 4679 #sound-dai-cells = <1>; 4680 }; 4681 4682 swr3: soundwire@6ab0000 { 4683 compatible = "qcom,soundwire-v2.0.0"; 4684 reg = <0 0x06ab0000 0 0x10000>; 4685 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 4686 clocks = <&lpass_wsa2macro>; 4687 clock-names = "iface"; 4688 label = "WSA2"; 4689 4690 pinctrl-0 = <&wsa2_swr_active>; 4691 pinctrl-names = "default"; 4692 4693 qcom,din-ports = <4>; 4694 qcom,dout-ports = <9>; 4695 4696 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4697 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4698 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4699 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4700 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4701 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4702 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4703 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4704 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4705 4706 #address-cells = <2>; 4707 #size-cells = <0>; 4708 #sound-dai-cells = <1>; 4709 status = "disabled"; 4710 }; 4711 4712 lpass_rxmacro: codec@6ac0000 { 4713 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 4714 reg = <0 0x06ac0000 0 0x1000>; 4715 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4716 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4717 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4718 <&lpass_vamacro>; 4719 clock-names = "mclk", 4720 "macro", 4721 "dcodec", 4722 "fsgen"; 4723 4724 #clock-cells = <0>; 4725 clock-output-names = "mclk"; 4726 #sound-dai-cells = <1>; 4727 }; 4728 4729 swr1: soundwire@6ad0000 { 4730 compatible = "qcom,soundwire-v2.0.0"; 4731 reg = <0 0x06ad0000 0 0x10000>; 4732 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 4733 clocks = <&lpass_rxmacro>; 4734 clock-names = "iface"; 4735 label = "RX"; 4736 4737 pinctrl-0 = <&rx_swr_active>; 4738 pinctrl-names = "default"; 4739 4740 qcom,din-ports = <1>; 4741 qcom,dout-ports = <11>; 4742 4743 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff 0xff>; 4744 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; 4745 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; 4746 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; 4747 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>; 4748 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff 0xff>; 4749 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff 0xff>; 4750 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; 4751 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff 0xff>; 4752 4753 #address-cells = <2>; 4754 #size-cells = <0>; 4755 #sound-dai-cells = <1>; 4756 status = "disabled"; 4757 }; 4758 4759 lpass_txmacro: codec@6ae0000 { 4760 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 4761 reg = <0 0x06ae0000 0 0x1000>; 4762 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4763 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4764 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4765 <&lpass_vamacro>; 4766 clock-names = "mclk", 4767 "macro", 4768 "dcodec", 4769 "fsgen"; 4770 4771 #clock-cells = <0>; 4772 clock-output-names = "mclk"; 4773 #sound-dai-cells = <1>; 4774 }; 4775 4776 lpass_wsamacro: codec@6b00000 { 4777 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4778 reg = <0 0x06b00000 0 0x1000>; 4779 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4780 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4781 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4782 <&lpass_vamacro>; 4783 clock-names = "mclk", 4784 "macro", 4785 "dcodec", 4786 "fsgen"; 4787 4788 #clock-cells = <0>; 4789 clock-output-names = "mclk"; 4790 #sound-dai-cells = <1>; 4791 }; 4792 4793 swr0: soundwire@6b10000 { 4794 compatible = "qcom,soundwire-v2.0.0"; 4795 reg = <0 0x06b10000 0 0x10000>; 4796 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 4797 clocks = <&lpass_wsamacro>; 4798 clock-names = "iface"; 4799 label = "WSA"; 4800 4801 pinctrl-0 = <&wsa_swr_active>; 4802 pinctrl-names = "default"; 4803 4804 qcom,din-ports = <4>; 4805 qcom,dout-ports = <9>; 4806 4807 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4808 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4809 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4810 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4811 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4812 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4813 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4814 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4815 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4816 4817 #address-cells = <2>; 4818 #size-cells = <0>; 4819 #sound-dai-cells = <1>; 4820 status = "disabled"; 4821 }; 4822 4823 swr2: soundwire@6d30000 { 4824 compatible = "qcom,soundwire-v2.0.0"; 4825 reg = <0 0x06d30000 0 0x10000>; 4826 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>, 4827 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>; 4828 interrupt-names = "core", "wakeup"; 4829 clocks = <&lpass_txmacro>; 4830 clock-names = "iface"; 4831 label = "TX"; 4832 4833 pinctrl-0 = <&tx_swr_active>; 4834 pinctrl-names = "default"; 4835 4836 qcom,din-ports = <4>; 4837 qcom,dout-ports = <1>; 4838 4839 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x01 0x03 0x03>; 4840 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x00 0x01 0x01>; 4841 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0x00>; 4842 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4843 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4844 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4845 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4846 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4847 qcom,ports-lane-control = /bits/ 8 <0xff 0x01 0x02 0x00 0x00>; 4848 4849 #address-cells = <2>; 4850 #size-cells = <0>; 4851 #sound-dai-cells = <1>; 4852 status = "disabled"; 4853 }; 4854 4855 lpass_vamacro: codec@6d44000 { 4856 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 4857 reg = <0 0x06d44000 0 0x1000>; 4858 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4859 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4860 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4861 clock-names = "mclk", 4862 "macro", 4863 "dcodec"; 4864 4865 #clock-cells = <0>; 4866 clock-output-names = "fsgen"; 4867 #sound-dai-cells = <1>; 4868 }; 4869 4870 lpass_tlmm: pinctrl@6e80000 { 4871 compatible = "qcom,sm8650-lpass-lpi-pinctrl"; 4872 reg = <0 0x06e80000 0 0x20000>; 4873 4874 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4875 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4876 clock-names = "core", "audio"; 4877 4878 gpio-controller; 4879 #gpio-cells = <2>; 4880 gpio-ranges = <&lpass_tlmm 0 0 23>; 4881 4882 tx_swr_active: tx-swr-active-state { 4883 clk-pins { 4884 pins = "gpio0"; 4885 function = "swr_tx_clk"; 4886 drive-strength = <2>; 4887 slew-rate = <1>; 4888 bias-disable; 4889 }; 4890 4891 data-pins { 4892 pins = "gpio1", "gpio2", "gpio14"; 4893 function = "swr_tx_data"; 4894 drive-strength = <2>; 4895 slew-rate = <1>; 4896 bias-bus-hold; 4897 }; 4898 }; 4899 4900 rx_swr_active: rx-swr-active-state { 4901 clk-pins { 4902 pins = "gpio3"; 4903 function = "swr_rx_clk"; 4904 drive-strength = <2>; 4905 slew-rate = <1>; 4906 bias-disable; 4907 }; 4908 4909 data-pins { 4910 pins = "gpio4", "gpio5"; 4911 function = "swr_rx_data"; 4912 drive-strength = <2>; 4913 slew-rate = <1>; 4914 bias-bus-hold; 4915 }; 4916 }; 4917 4918 dmic01_default: dmic01-default-state { 4919 clk-pins { 4920 pins = "gpio6"; 4921 function = "dmic1_clk"; 4922 drive-strength = <8>; 4923 output-high; 4924 }; 4925 4926 data-pins { 4927 pins = "gpio7"; 4928 function = "dmic1_data"; 4929 drive-strength = <8>; 4930 input-enable; 4931 }; 4932 }; 4933 4934 dmic23_default: dmic23-default-state { 4935 clk-pins { 4936 pins = "gpio8"; 4937 function = "dmic2_clk"; 4938 drive-strength = <8>; 4939 output-high; 4940 }; 4941 4942 data-pins { 4943 pins = "gpio9"; 4944 function = "dmic2_data"; 4945 drive-strength = <8>; 4946 input-enable; 4947 }; 4948 }; 4949 4950 wsa_swr_active: wsa-swr-active-state { 4951 clk-pins { 4952 pins = "gpio10"; 4953 function = "wsa_swr_clk"; 4954 drive-strength = <2>; 4955 slew-rate = <1>; 4956 bias-disable; 4957 }; 4958 4959 data-pins { 4960 pins = "gpio11"; 4961 function = "wsa_swr_data"; 4962 drive-strength = <2>; 4963 slew-rate = <1>; 4964 bias-bus-hold; 4965 }; 4966 }; 4967 4968 wsa2_swr_active: wsa2-swr-active-state { 4969 clk-pins { 4970 pins = "gpio15"; 4971 function = "wsa2_swr_clk"; 4972 drive-strength = <2>; 4973 slew-rate = <1>; 4974 bias-disable; 4975 }; 4976 4977 data-pins { 4978 pins = "gpio16"; 4979 function = "wsa2_swr_data"; 4980 drive-strength = <2>; 4981 slew-rate = <1>; 4982 bias-bus-hold; 4983 }; 4984 }; 4985 }; 4986 4987 lpass_lpiaon_noc: interconnect@7400000 { 4988 compatible = "qcom,sm8650-lpass-lpiaon-noc"; 4989 reg = <0 0x07400000 0 0x19080>; 4990 4991 #interconnect-cells = <2>; 4992 4993 qcom,bcm-voters = <&apps_bcm_voter>; 4994 }; 4995 4996 lpass_lpicx_noc: interconnect@7430000 { 4997 compatible = "qcom,sm8650-lpass-lpicx-noc"; 4998 reg = <0 0x07430000 0 0x3a200>; 4999 5000 #interconnect-cells = <2>; 5001 5002 qcom,bcm-voters = <&apps_bcm_voter>; 5003 }; 5004 5005 lpass_ag_noc: interconnect@7e40000 { 5006 compatible = "qcom,sm8650-lpass-ag-noc"; 5007 reg = <0 0x07e40000 0 0xe080>; 5008 5009 #interconnect-cells = <2>; 5010 5011 qcom,bcm-voters = <&apps_bcm_voter>; 5012 }; 5013 5014 sdhc_2: mmc@8804000 { 5015 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; 5016 reg = <0 0x08804000 0 0x1000>; 5017 5018 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>, 5019 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH 0>; 5020 interrupt-names = "hc_irq", 5021 "pwr_irq"; 5022 5023 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 5024 <&gcc GCC_SDCC2_APPS_CLK>, 5025 <&bi_tcxo_div2>; 5026 clock-names = "iface", 5027 "core", 5028 "xo"; 5029 5030 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 5031 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5032 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5033 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 5034 interconnect-names = "sdhc-ddr", 5035 "cpu-sdhc"; 5036 5037 power-domains = <&rpmhpd RPMHPD_CX>; 5038 operating-points-v2 = <&sdhc2_opp_table>; 5039 5040 iommus = <&apps_smmu 0x540 0>; 5041 5042 bus-width = <4>; 5043 5044 qcom,dll-config = <0x0007642c>; 5045 qcom,ddr-config = <0x80040868>; 5046 5047 dma-coherent; 5048 5049 status = "disabled"; 5050 5051 sdhc2_opp_table: opp-table { 5052 compatible = "operating-points-v2"; 5053 5054 opp-19200000 { 5055 opp-hz = /bits/ 64 <19200000>; 5056 required-opps = <&rpmhpd_opp_min_svs>; 5057 }; 5058 5059 opp-50000000 { 5060 opp-hz = /bits/ 64 <50000000>; 5061 required-opps = <&rpmhpd_opp_low_svs>; 5062 }; 5063 5064 opp-100000000 { 5065 opp-hz = /bits/ 64 <100000000>; 5066 required-opps = <&rpmhpd_opp_svs>; 5067 }; 5068 5069 opp-202000000 { 5070 opp-hz = /bits/ 64 <202000000>; 5071 required-opps = <&rpmhpd_opp_svs_l1>; 5072 }; 5073 }; 5074 }; 5075 5076 usb_1_hsphy: phy@88e3000 { 5077 compatible = "qcom,sm8650-snps-eusb2-phy", 5078 "qcom,sm8550-snps-eusb2-phy"; 5079 reg = <0 0x088e3000 0 0x154>; 5080 5081 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 5082 clock-names = "ref"; 5083 5084 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 5085 5086 #phy-cells = <0>; 5087 5088 status = "disabled"; 5089 }; 5090 5091 usb_dp_qmpphy: phy@88e8000 { 5092 compatible = "qcom,sm8650-qmp-usb3-dp-phy"; 5093 reg = <0 0x088e8000 0 0x3000>; 5094 5095 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 5096 <&rpmhcc RPMH_CXO_CLK>, 5097 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 5098 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 5099 clock-names = "aux", 5100 "ref", 5101 "com_aux", 5102 "usb3_pipe"; 5103 5104 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 5105 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 5106 reset-names = "phy", 5107 "common"; 5108 5109 power-domains = <&gcc USB3_PHY_GDSC>; 5110 5111 #clock-cells = <1>; 5112 #phy-cells = <1>; 5113 5114 mode-switch; 5115 orientation-switch; 5116 5117 status = "disabled"; 5118 5119 ports { 5120 #address-cells = <1>; 5121 #size-cells = <0>; 5122 5123 port@0 { 5124 reg = <0>; 5125 5126 usb_dp_qmpphy_out: endpoint { 5127 }; 5128 }; 5129 5130 port@1 { 5131 reg = <1>; 5132 5133 usb_dp_qmpphy_usb_ss_in: endpoint { 5134 remote-endpoint = <&usb_1_dwc3_ss>; 5135 }; 5136 }; 5137 5138 port@2 { 5139 reg = <2>; 5140 5141 usb_dp_qmpphy_dp_in: endpoint { 5142 remote-endpoint = <&mdss_dp0_out>; 5143 }; 5144 }; 5145 }; 5146 }; 5147 5148 usb_1: usb@a600000 { 5149 compatible = "qcom,sm8650-dwc3", "qcom,snps-dwc3"; 5150 reg = <0 0x0a600000 0 0xfc100>; 5151 5152 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, 5153 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, 5154 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, 5155 <&pdc 14 IRQ_TYPE_EDGE_RISING>, 5156 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 5157 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 5158 interrupt-names = "dwc_usb3", 5159 "pwr_event", 5160 "hs_phy_irq", 5161 "dp_hs_phy_irq", 5162 "dm_hs_phy_irq", 5163 "ss_phy_irq"; 5164 5165 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5166 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5167 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5168 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5169 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5170 <&tcsr TCSR_USB3_CLKREF_EN>; 5171 clock-names = "cfg_noc", 5172 "core", 5173 "iface", 5174 "sleep", 5175 "mock_utmi", 5176 "xo"; 5177 5178 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5179 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5180 assigned-clock-rates = <19200000>, <200000000>; 5181 5182 resets = <&gcc GCC_USB30_PRIM_BCR>; 5183 5184 phys = <&usb_1_hsphy>, 5185 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 5186 phy-names = "usb2-phy", 5187 "usb3-phy"; 5188 5189 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 5190 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5191 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5192 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 5193 interconnect-names = "usb-ddr", 5194 "apps-usb"; 5195 5196 iommus = <&apps_smmu 0x40 0>; 5197 5198 power-domains = <&gcc USB30_PRIM_GDSC>; 5199 required-opps = <&rpmhpd_opp_nom>; 5200 5201 snps,hird-threshold = /bits/ 8 <0x0>; 5202 snps,usb2-gadget-lpm-disable; 5203 snps,dis_u2_susphy_quirk; 5204 snps,dis_enblslpm_quirk; 5205 snps,dis-u1-entry-quirk; 5206 snps,dis-u2-entry-quirk; 5207 snps,is-utmi-l1-suspend; 5208 snps,usb3_lpm_capable; 5209 snps,usb2-lpm-disable; 5210 snps,has-lpm-erratum; 5211 tx-fifo-resize; 5212 5213 dma-coherent; 5214 5215 status = "disabled"; 5216 5217 ports { 5218 #address-cells = <1>; 5219 #size-cells = <0>; 5220 5221 port@0 { 5222 reg = <0>; 5223 5224 usb_1_dwc3_hs: endpoint { 5225 }; 5226 }; 5227 5228 port@1 { 5229 reg = <1>; 5230 5231 usb_1_dwc3_ss: endpoint { 5232 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 5233 }; 5234 }; 5235 }; 5236 }; 5237 5238 iris: video-codec@aa00000 { 5239 compatible = "qcom,sm8650-iris"; 5240 reg = <0 0x0aa00000 0 0xf0000>; 5241 5242 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; 5243 5244 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 5245 <&videocc VIDEO_CC_MVS0_GDSC>, 5246 <&rpmhpd RPMHPD_MXC>, 5247 <&rpmhpd RPMHPD_MMCX>; 5248 power-domain-names = "venus", 5249 "vcodec0", 5250 "mxc", 5251 "mmcx"; 5252 5253 operating-points-v2 = <&iris_opp_table>; 5254 5255 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 5256 <&videocc VIDEO_CC_MVS0C_CLK>, 5257 <&videocc VIDEO_CC_MVS0_CLK>; 5258 clock-names = "iface", 5259 "core", 5260 "vcodec0_core"; 5261 5262 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5263 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5264 <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS 5265 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5266 interconnect-names = "cpu-cfg", 5267 "video-mem"; 5268 5269 memory-region = <&video_mem>; 5270 5271 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 5272 <&videocc VIDEO_CC_XO_CLK_ARES>, 5273 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 5274 reset-names = "bus", 5275 "xo", 5276 "core"; 5277 5278 iommus = <&apps_smmu 0x1940 0>, 5279 <&apps_smmu 0x1947 0>; 5280 5281 dma-coherent; 5282 5283 /* 5284 * IRIS firmware is signed by vendors, only 5285 * enable on boards where the proper signed firmware 5286 * is available. 5287 */ 5288 status = "disabled"; 5289 5290 iris_opp_table: opp-table { 5291 compatible = "operating-points-v2"; 5292 5293 opp-196000000 { 5294 opp-hz = /bits/ 64 <196000000>; 5295 required-opps = <&rpmhpd_opp_low_svs_d1>, 5296 <&rpmhpd_opp_low_svs_d1>; 5297 }; 5298 5299 opp-300000000 { 5300 opp-hz = /bits/ 64 <300000000>; 5301 required-opps = <&rpmhpd_opp_svs>, 5302 <&rpmhpd_opp_low_svs>; 5303 }; 5304 5305 opp-380000000 { 5306 opp-hz = /bits/ 64 <380000000>; 5307 required-opps = <&rpmhpd_opp_svs_l1>, 5308 <&rpmhpd_opp_svs>; 5309 }; 5310 5311 opp-435000000 { 5312 opp-hz = /bits/ 64 <435000000>; 5313 required-opps = <&rpmhpd_opp_svs_l1>, 5314 <&rpmhpd_opp_svs_l1>; 5315 }; 5316 5317 opp-480000000 { 5318 opp-hz = /bits/ 64 <480000000>; 5319 required-opps = <&rpmhpd_opp_svs_l1>, 5320 <&rpmhpd_opp_nom>; 5321 }; 5322 5323 opp-533333334 { 5324 opp-hz = /bits/ 64 <533333334>; 5325 required-opps = <&rpmhpd_opp_svs_l1>, 5326 <&rpmhpd_opp_turbo>; 5327 }; 5328 }; 5329 }; 5330 5331 videocc: clock-controller@aaf0000 { 5332 compatible = "qcom,sm8650-videocc"; 5333 reg = <0 0x0aaf0000 0 0x10000>; 5334 clocks = <&bi_tcxo_div2>, 5335 <&gcc GCC_VIDEO_AHB_CLK>; 5336 power-domains = <&rpmhpd RPMHPD_MMCX>, 5337 <&rpmhpd RPMHPD_MXC>; 5338 #clock-cells = <1>; 5339 #reset-cells = <1>; 5340 #power-domain-cells = <1>; 5341 }; 5342 5343 cci0: cci@ac15000 { 5344 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 5345 reg = <0 0x0ac15000 0 0x1000>; 5346 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>; 5347 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5348 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 5349 <&camcc CAM_CC_CPAS_AHB_CLK>, 5350 <&camcc CAM_CC_CCI_0_CLK>; 5351 clock-names = "camnoc_axi", 5352 "cpas_ahb", 5353 "cci"; 5354 assigned-clocks = <&camcc CAM_CC_CCI_0_CLK>; 5355 assigned-clock-rates = <37500000>; 5356 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 5357 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 5358 pinctrl-names = "default", "sleep"; 5359 status = "disabled"; 5360 #address-cells = <1>; 5361 #size-cells = <0>; 5362 5363 cci0_i2c0: i2c-bus@0 { 5364 reg = <0>; 5365 clock-frequency = <1000000>; 5366 #address-cells = <1>; 5367 #size-cells = <0>; 5368 }; 5369 5370 cci0_i2c1: i2c-bus@1 { 5371 reg = <1>; 5372 clock-frequency = <1000000>; 5373 #address-cells = <1>; 5374 #size-cells = <0>; 5375 }; 5376 }; 5377 5378 cci1: cci@ac16000 { 5379 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 5380 reg = <0 0x0ac16000 0 0x1000>; 5381 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING 0>; 5382 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5383 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 5384 <&camcc CAM_CC_CPAS_AHB_CLK>, 5385 <&camcc CAM_CC_CCI_1_CLK>; 5386 clock-names = "camnoc_axi", 5387 "cpas_ahb", 5388 "cci"; 5389 assigned-clocks = <&camcc CAM_CC_CCI_1_CLK>; 5390 assigned-clock-rates = <37500000>; 5391 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 5392 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 5393 pinctrl-names = "default", "sleep"; 5394 status = "disabled"; 5395 #address-cells = <1>; 5396 #size-cells = <0>; 5397 5398 cci1_i2c0: i2c-bus@0 { 5399 reg = <0>; 5400 clock-frequency = <1000000>; 5401 #address-cells = <1>; 5402 #size-cells = <0>; 5403 }; 5404 5405 cci1_i2c1: i2c-bus@1 { 5406 reg = <1>; 5407 clock-frequency = <1000000>; 5408 #address-cells = <1>; 5409 #size-cells = <0>; 5410 }; 5411 }; 5412 5413 cci2: cci@ac17000 { 5414 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 5415 reg = <0 0x0ac17000 0 0x1000>; 5416 interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING 0>; 5417 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5418 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 5419 <&camcc CAM_CC_CPAS_AHB_CLK>, 5420 <&camcc CAM_CC_CCI_2_CLK>; 5421 clock-names = "camnoc_axi", 5422 "cpas_ahb", 5423 "cci"; 5424 assigned-clocks = <&camcc CAM_CC_CCI_2_CLK>; 5425 assigned-clock-rates = <37500000>; 5426 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 5427 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 5428 pinctrl-names = "default", "sleep"; 5429 status = "disabled"; 5430 #address-cells = <1>; 5431 #size-cells = <0>; 5432 5433 cci2_i2c0: i2c-bus@0 { 5434 reg = <0>; 5435 clock-frequency = <1000000>; 5436 #address-cells = <1>; 5437 #size-cells = <0>; 5438 }; 5439 5440 cci2_i2c1: i2c-bus@1 { 5441 reg = <1>; 5442 clock-frequency = <1000000>; 5443 #address-cells = <1>; 5444 #size-cells = <0>; 5445 }; 5446 }; 5447 5448 camss: isp@acb6000 { 5449 compatible = "qcom,sm8650-camss"; 5450 5451 reg = <0 0x0acb6000 0 0x1000>, 5452 <0 0x0acb8000 0 0x1000>, 5453 <0 0x0acba000 0 0x1000>, 5454 <0 0x0acbc000 0 0x1000>, 5455 <0 0x0accb000 0 0x1000>, 5456 <0 0x0acd0000 0 0x1000>, 5457 <0 0x0ace4000 0 0x2000>, 5458 <0 0x0ace6000 0 0x2000>, 5459 <0 0x0ace8000 0 0x2000>, 5460 <0 0x0acea000 0 0x2000>, 5461 <0 0x0acec000 0 0x2000>, 5462 <0 0x0acee000 0 0x2000>, 5463 <0 0x0ac62000 0 0xf000>, 5464 <0 0x0ac71000 0 0xf000>, 5465 <0 0x0ac80000 0 0xf000>, 5466 <0 0x0accc000 0 0x2000>, 5467 <0 0x0acd1000 0 0x2000>; 5468 reg-names = "csid_wrapper", 5469 "csid0", 5470 "csid1", 5471 "csid2", 5472 "csid_lite0", 5473 "csid_lite1", 5474 "csiphy0", 5475 "csiphy1", 5476 "csiphy2", 5477 "csiphy3", 5478 "csiphy4", 5479 "csiphy5", 5480 "vfe0", 5481 "vfe1", 5482 "vfe2", 5483 "vfe_lite0", 5484 "vfe_lite1"; 5485 5486 clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, 5487 <&camcc CAM_CC_CPAS_AHB_CLK>, 5488 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 5489 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 5490 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 5491 <&camcc CAM_CC_CPAS_IFE_2_CLK>, 5492 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 5493 <&camcc CAM_CC_CSID_CLK>, 5494 <&camcc CAM_CC_CSIPHY0_CLK>, 5495 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 5496 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 5497 <&camcc CAM_CC_CSIPHY1_CLK>, 5498 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 5499 <&camcc CAM_CC_CSIPHY2_CLK>, 5500 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 5501 <&camcc CAM_CC_CSIPHY3_CLK>, 5502 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 5503 <&camcc CAM_CC_CSIPHY4_CLK>, 5504 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 5505 <&camcc CAM_CC_CSIPHY5_CLK>, 5506 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 5507 <&gcc GCC_CAMERA_HF_AXI_CLK>, 5508 <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>, 5509 <&camcc CAM_CC_IFE_0_CLK>, 5510 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 5511 <&camcc CAM_CC_IFE_1_CLK>, 5512 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 5513 <&camcc CAM_CC_IFE_2_CLK>, 5514 <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, 5515 <&camcc CAM_CC_IFE_LITE_CLK>, 5516 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 5517 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 5518 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 5519 clock-names = "camnoc_axi", 5520 "cpas_ahb", 5521 "cpas_fast_ahb", 5522 "cpas_vfe0", 5523 "cpas_vfe1", 5524 "cpas_vfe2", 5525 "cpas_vfe_lite", 5526 "csid", 5527 "csiphy0", 5528 "csiphy0_timer", 5529 "csiphy1", 5530 "csiphy1_timer", 5531 "csiphy2", 5532 "csiphy2_timer", 5533 "csiphy3", 5534 "csiphy3_timer", 5535 "csiphy4", 5536 "csiphy4_timer", 5537 "csiphy5", 5538 "csiphy5_timer", 5539 "csiphy_rx", 5540 "gcc_axi_hf", 5541 "qdss_debug_xo", 5542 "vfe0", 5543 "vfe0_fast_ahb", 5544 "vfe1", 5545 "vfe1_fast_ahb", 5546 "vfe2", 5547 "vfe2_fast_ahb", 5548 "vfe_lite", 5549 "vfe_lite_ahb", 5550 "vfe_lite_cphy_rx", 5551 "vfe_lite_csid"; 5552 5553 interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING 0>, 5554 <GIC_SPI 603 IRQ_TYPE_EDGE_RISING 0>, 5555 <GIC_SPI 431 IRQ_TYPE_EDGE_RISING 0>, 5556 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING 0>, 5557 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING 0>, 5558 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>, 5559 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>, 5560 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>, 5561 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING 0>, 5562 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING 0>, 5563 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING 0>, 5564 <GIC_SPI 602 IRQ_TYPE_EDGE_RISING 0>, 5565 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING 0>, 5566 <GIC_SPI 688 IRQ_TYPE_EDGE_RISING 0>, 5567 <GIC_SPI 606 IRQ_TYPE_EDGE_RISING 0>, 5568 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING 0>; 5569 interrupt-names = "csid0", 5570 "csid1", 5571 "csid2", 5572 "csid_lite0", 5573 "csid_lite1", 5574 "csiphy0", 5575 "csiphy1", 5576 "csiphy2", 5577 "csiphy3", 5578 "csiphy4", 5579 "csiphy5", 5580 "vfe0", 5581 "vfe1", 5582 "vfe2", 5583 "vfe_lite0", 5584 "vfe_lite1"; 5585 5586 interconnects = <&gem_noc MASTER_APPSS_PROC 0 5587 &config_noc SLAVE_CAMERA_CFG 0>, 5588 <&mmss_noc MASTER_CAMNOC_HF 0 5589 &mc_virt SLAVE_EBI1 0>; 5590 interconnect-names = "ahb", 5591 "hf_mnoc"; 5592 5593 iommus = <&apps_smmu 0x800 0x20>, 5594 <&apps_smmu 0x18a0 0x40>, 5595 <&apps_smmu 0x1860 0x00>; 5596 5597 power-domains = <&camcc CAM_CC_IFE_0_GDSC>, 5598 <&camcc CAM_CC_IFE_1_GDSC>, 5599 <&camcc CAM_CC_IFE_2_GDSC>, 5600 <&camcc CAM_CC_TITAN_TOP_GDSC>; 5601 power-domain-names = "ife0", "ife1", "ife2", "top"; 5602 5603 status = "disabled"; 5604 5605 ports { 5606 #address-cells = <1>; 5607 #size-cells = <0>; 5608 5609 port@0 { 5610 reg = <0>; 5611 }; 5612 5613 port@1 { 5614 reg = <1>; 5615 }; 5616 5617 port@2 { 5618 reg = <2>; 5619 }; 5620 5621 port@3 { 5622 reg = <3>; 5623 }; 5624 5625 port@4 { 5626 reg = <4>; 5627 }; 5628 5629 port@5 { 5630 reg = <5>; 5631 }; 5632 }; 5633 }; 5634 5635 camcc: clock-controller@ade0000 { 5636 compatible = "qcom,sm8650-camcc"; 5637 reg = <0 0x0ade0000 0 0x20000>; 5638 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 5639 <&bi_tcxo_div2>, 5640 <&bi_tcxo_ao_div2>, 5641 <&sleep_clk>; 5642 power-domains = <&rpmhpd RPMHPD_MMCX>, 5643 <&rpmhpd RPMHPD_MXC>; 5644 #clock-cells = <1>; 5645 #reset-cells = <1>; 5646 #power-domain-cells = <1>; 5647 }; 5648 5649 mdss: display-subsystem@ae00000 { 5650 compatible = "qcom,sm8650-mdss"; 5651 reg = <0 0x0ae00000 0 0x1000>; 5652 reg-names = "mdss"; 5653 5654 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>; 5655 5656 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5657 <&gcc GCC_DISP_HF_AXI_CLK>, 5658 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5659 5660 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5661 5662 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 5663 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5664 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5665 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5666 interconnect-names = "mdp0-mem", 5667 "cpu-cfg"; 5668 5669 power-domains = <&dispcc MDSS_GDSC>; 5670 5671 iommus = <&apps_smmu 0x1c00 0x2>; 5672 5673 interrupt-controller; 5674 #interrupt-cells = <1>; 5675 5676 #address-cells = <2>; 5677 #size-cells = <2>; 5678 ranges; 5679 5680 status = "disabled"; 5681 5682 mdss_mdp: display-controller@ae01000 { 5683 compatible = "qcom,sm8650-dpu"; 5684 reg = <0 0x0ae01000 0 0x8f000>, 5685 <0 0x0aeb0000 0 0x3000>; 5686 reg-names = "mdp", 5687 "vbif"; 5688 5689 interrupts-extended = <&mdss 0>; 5690 5691 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5692 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5693 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5694 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5695 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5696 clock-names = "nrt_bus", 5697 "iface", 5698 "lut", 5699 "core", 5700 "vsync"; 5701 5702 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5703 assigned-clock-rates = <19200000>; 5704 5705 operating-points-v2 = <&mdp_opp_table>; 5706 5707 power-domains = <&rpmhpd RPMHPD_MMCX>; 5708 5709 ports { 5710 #address-cells = <1>; 5711 #size-cells = <0>; 5712 5713 port@0 { 5714 reg = <0>; 5715 5716 dpu_intf1_out: endpoint { 5717 remote-endpoint = <&mdss_dsi0_in>; 5718 }; 5719 }; 5720 5721 port@1 { 5722 reg = <1>; 5723 5724 dpu_intf2_out: endpoint { 5725 remote-endpoint = <&mdss_dsi1_in>; 5726 }; 5727 }; 5728 5729 port@2 { 5730 reg = <2>; 5731 5732 dpu_intf0_out: endpoint { 5733 remote-endpoint = <&mdss_dp0_in>; 5734 }; 5735 }; 5736 }; 5737 5738 mdp_opp_table: opp-table { 5739 compatible = "operating-points-v2"; 5740 5741 opp-200000000 { 5742 opp-hz = /bits/ 64 <200000000>; 5743 required-opps = <&rpmhpd_opp_low_svs>; 5744 }; 5745 5746 opp-325000000 { 5747 opp-hz = /bits/ 64 <325000000>; 5748 required-opps = <&rpmhpd_opp_svs>; 5749 }; 5750 5751 opp-375000000 { 5752 opp-hz = /bits/ 64 <375000000>; 5753 required-opps = <&rpmhpd_opp_svs_l1>; 5754 }; 5755 5756 opp-514000000 { 5757 opp-hz = /bits/ 64 <514000000>; 5758 required-opps = <&rpmhpd_opp_nom>; 5759 }; 5760 }; 5761 }; 5762 5763 mdss_dsi0: dsi@ae94000 { 5764 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5765 reg = <0 0x0ae94000 0 0x400>; 5766 reg-names = "dsi_ctrl"; 5767 5768 interrupts-extended = <&mdss 4>; 5769 5770 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 5771 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 5772 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 5773 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 5774 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5775 <&gcc GCC_DISP_HF_AXI_CLK>; 5776 clock-names = "byte", 5777 "byte_intf", 5778 "pixel", 5779 "core", 5780 "iface", 5781 "bus"; 5782 5783 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 5784 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 5785 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5786 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 5787 5788 operating-points-v2 = <&mdss_dsi_opp_table>; 5789 5790 power-domains = <&rpmhpd RPMHPD_MMCX>; 5791 5792 phys = <&mdss_dsi0_phy>; 5793 phy-names = "dsi"; 5794 5795 #address-cells = <1>; 5796 #size-cells = <0>; 5797 5798 status = "disabled"; 5799 5800 ports { 5801 #address-cells = <1>; 5802 #size-cells = <0>; 5803 5804 port@0 { 5805 reg = <0>; 5806 5807 mdss_dsi0_in: endpoint { 5808 remote-endpoint = <&dpu_intf1_out>; 5809 }; 5810 }; 5811 5812 port@1 { 5813 reg = <1>; 5814 5815 mdss_dsi0_out: endpoint { 5816 }; 5817 }; 5818 }; 5819 5820 mdss_dsi_opp_table: opp-table { 5821 compatible = "operating-points-v2"; 5822 5823 opp-187500000 { 5824 opp-hz = /bits/ 64 <187500000>; 5825 required-opps = <&rpmhpd_opp_low_svs>; 5826 }; 5827 5828 opp-300000000 { 5829 opp-hz = /bits/ 64 <300000000>; 5830 required-opps = <&rpmhpd_opp_svs>; 5831 }; 5832 5833 opp-358000000 { 5834 opp-hz = /bits/ 64 <358000000>; 5835 required-opps = <&rpmhpd_opp_svs_l1>; 5836 }; 5837 }; 5838 }; 5839 5840 mdss_dsi0_phy: phy@ae95000 { 5841 compatible = "qcom,sm8650-dsi-phy-4nm"; 5842 reg = <0 0x0ae95000 0 0x200>, 5843 <0 0x0ae95200 0 0x280>, 5844 <0 0x0ae95500 0 0x400>; 5845 reg-names = "dsi_phy", 5846 "dsi_phy_lane", 5847 "dsi_pll"; 5848 5849 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5850 <&rpmhcc RPMH_CXO_CLK>; 5851 clock-names = "iface", 5852 "ref"; 5853 5854 #clock-cells = <1>; 5855 #phy-cells = <0>; 5856 5857 status = "disabled"; 5858 }; 5859 5860 mdss_dsi1: dsi@ae96000 { 5861 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5862 reg = <0 0x0ae96000 0 0x400>; 5863 reg-names = "dsi_ctrl"; 5864 5865 interrupts-extended = <&mdss 5>; 5866 5867 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 5868 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 5869 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 5870 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 5871 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5872 <&gcc GCC_DISP_HF_AXI_CLK>; 5873 clock-names = "byte", 5874 "byte_intf", 5875 "pixel", 5876 "core", 5877 "iface", 5878 "bus"; 5879 5880 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 5881 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 5882 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 5883 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 5884 5885 operating-points-v2 = <&mdss_dsi_opp_table>; 5886 5887 power-domains = <&rpmhpd RPMHPD_MMCX>; 5888 5889 phys = <&mdss_dsi1_phy>; 5890 phy-names = "dsi"; 5891 5892 #address-cells = <1>; 5893 #size-cells = <0>; 5894 5895 status = "disabled"; 5896 5897 ports { 5898 #address-cells = <1>; 5899 #size-cells = <0>; 5900 5901 port@0 { 5902 reg = <0>; 5903 5904 mdss_dsi1_in: endpoint { 5905 remote-endpoint = <&dpu_intf2_out>; 5906 }; 5907 }; 5908 5909 port@1 { 5910 reg = <1>; 5911 5912 mdss_dsi1_out: endpoint { 5913 }; 5914 }; 5915 }; 5916 }; 5917 5918 mdss_dsi1_phy: phy@ae97000 { 5919 compatible = "qcom,sm8650-dsi-phy-4nm"; 5920 reg = <0 0x0ae97000 0 0x200>, 5921 <0 0x0ae97200 0 0x280>, 5922 <0 0x0ae97500 0 0x400>; 5923 reg-names = "dsi_phy", 5924 "dsi_phy_lane", 5925 "dsi_pll"; 5926 5927 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5928 <&rpmhcc RPMH_CXO_CLK>; 5929 clock-names = "iface", 5930 "ref"; 5931 5932 #clock-cells = <1>; 5933 #phy-cells = <0>; 5934 5935 status = "disabled"; 5936 }; 5937 5938 mdss_dp0: displayport-controller@af54000 { 5939 compatible = "qcom,sm8650-dp"; 5940 reg = <0x0 0x0af54000 0x0 0x200>, 5941 <0x0 0x0af54200 0x0 0x200>, 5942 <0x0 0x0af55000 0x0 0xc00>, 5943 <0x0 0x0af56000 0x0 0x400>, 5944 <0x0 0x0af57000 0x0 0x400>, 5945 <0x0 0x0af58000 0x0 0x400>, 5946 <0x0 0x0af59000 0x0 0x400>, 5947 <0x0 0x0af5a000 0x0 0x600>, 5948 <0x0 0x0af5b000 0x0 0x600>; 5949 5950 interrupts-extended = <&mdss 12>; 5951 5952 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5953 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 5954 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 5955 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5956 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5957 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 5958 clock-names = "core_iface", 5959 "core_aux", 5960 "ctrl_link", 5961 "ctrl_link_iface", 5962 "stream_pixel", 5963 "stream_1_pixel"; 5964 5965 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5966 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5967 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 5968 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5969 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5970 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5971 5972 operating-points-v2 = <&dp_opp_table>; 5973 5974 power-domains = <&rpmhpd RPMHPD_MMCX>; 5975 5976 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 5977 phy-names = "dp"; 5978 5979 #sound-dai-cells = <0>; 5980 sound-name-prefix = "DisplayPort0"; 5981 5982 status = "disabled"; 5983 5984 dp_opp_table: opp-table { 5985 compatible = "operating-points-v2"; 5986 5987 opp-162000000 { 5988 opp-hz = /bits/ 64 <162000000>; 5989 required-opps = <&rpmhpd_opp_low_svs_d1>; 5990 }; 5991 5992 opp-270000000 { 5993 opp-hz = /bits/ 64 <270000000>; 5994 required-opps = <&rpmhpd_opp_low_svs>; 5995 }; 5996 5997 opp-540000000 { 5998 opp-hz = /bits/ 64 <540000000>; 5999 required-opps = <&rpmhpd_opp_svs_l1>; 6000 }; 6001 6002 opp-810000000 { 6003 opp-hz = /bits/ 64 <810000000>; 6004 required-opps = <&rpmhpd_opp_nom>; 6005 }; 6006 }; 6007 6008 ports { 6009 #address-cells = <1>; 6010 #size-cells = <0>; 6011 6012 port@0 { 6013 reg = <0>; 6014 6015 mdss_dp0_in: endpoint { 6016 remote-endpoint = <&dpu_intf0_out>; 6017 }; 6018 }; 6019 6020 port@1 { 6021 reg = <1>; 6022 6023 mdss_dp0_out: endpoint { 6024 data-lanes = <0 1 2 3>; 6025 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 6026 }; 6027 }; 6028 }; 6029 }; 6030 }; 6031 6032 dispcc: clock-controller@af00000 { 6033 compatible = "qcom,sm8650-dispcc"; 6034 reg = <0 0x0af00000 0 0x20000>; 6035 6036 clocks = <&bi_tcxo_div2>, 6037 <&bi_tcxo_ao_div2>, 6038 <&gcc GCC_DISP_AHB_CLK>, 6039 <&sleep_clk>, 6040 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 6041 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 6042 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 6043 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 6044 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 6045 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 6046 <0>, /* dp1 */ 6047 <0>, 6048 <0>, /* dp2 */ 6049 <0>, 6050 <0>, /* dp3 */ 6051 <0>; 6052 6053 power-domains = <&rpmhpd RPMHPD_MMCX>; 6054 required-opps = <&rpmhpd_opp_low_svs>; 6055 6056 #clock-cells = <1>; 6057 #reset-cells = <1>; 6058 #power-domain-cells = <1>; 6059 }; 6060 6061 pdc: interrupt-controller@b220000 { 6062 compatible = "qcom,sm8650-pdc", "qcom,pdc"; 6063 reg = <0 0x0b220000 0 0x10000>, <0 0x174000f0 0 0x64>; 6064 6065 interrupt-parent = <&intc>; 6066 6067 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 6068 <125 63 1>, <126 716 12>, 6069 <138 251 5>, <143 244 4>; 6070 6071 #interrupt-cells = <2>; 6072 interrupt-controller; 6073 }; 6074 6075 tsens0: thermal-sensor@c228000 { 6076 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 6077 reg = <0 0x0c228000 0 0x1000>, /* TM */ 6078 <0 0x0c222000 0 0x1000>; /* SROT */ 6079 6080 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>, 6081 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 6082 interrupt-names = "uplow", 6083 "critical"; 6084 6085 #qcom,sensors = <15>; 6086 6087 #thermal-sensor-cells = <1>; 6088 }; 6089 6090 tsens1: thermal-sensor@c229000 { 6091 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 6092 reg = <0 0x0c229000 0 0x1000>, /* TM */ 6093 <0 0x0c223000 0 0x1000>; /* SROT */ 6094 6095 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>, 6096 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 6097 interrupt-names = "uplow", 6098 "critical"; 6099 6100 #qcom,sensors = <16>; 6101 6102 #thermal-sensor-cells = <1>; 6103 }; 6104 6105 tsens2: thermal-sensor@c22a000 { 6106 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 6107 reg = <0 0x0c22a000 0 0x1000>, /* TM */ 6108 <0 0x0c224000 0 0x1000>; /* SROT */ 6109 6110 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>, 6111 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 6112 interrupt-names = "uplow", 6113 "critical"; 6114 6115 #qcom,sensors = <13>; 6116 6117 #thermal-sensor-cells = <1>; 6118 }; 6119 6120 aoss_qmp: power-management@c300000 { 6121 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; 6122 reg = <0 0x0c300000 0 0x400>; 6123 6124 interrupt-parent = <&ipcc>; 6125 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 6126 IRQ_TYPE_EDGE_RISING>; 6127 6128 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 6129 6130 #clock-cells = <0>; 6131 }; 6132 6133 sram@c3f0000 { 6134 compatible = "qcom,rpmh-stats"; 6135 reg = <0 0x0c3f0000 0 0x400>; 6136 qcom,qmp = <&aoss_qmp>; 6137 }; 6138 6139 spmi_bus: spmi@c400000 { 6140 compatible = "qcom,spmi-pmic-arb"; 6141 reg = <0 0x0c400000 0 0x3000>, 6142 <0 0x0c500000 0 0x400000>, 6143 <0 0x0c440000 0 0x80000>, 6144 <0 0x0c4c0000 0 0x20000>, 6145 <0 0x0c42d000 0 0x4000>; 6146 reg-names = "core", 6147 "chnls", 6148 "obsrvr", 6149 "intr", 6150 "cnfg"; 6151 6152 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 6153 interrupt-names = "periph_irq"; 6154 6155 qcom,ee = <0>; 6156 qcom,channel = <0>; 6157 qcom,bus-id = <0>; 6158 6159 interrupt-controller; 6160 #interrupt-cells = <4>; 6161 6162 #address-cells = <2>; 6163 #size-cells = <0>; 6164 }; 6165 6166 tlmm: pinctrl@f100000 { 6167 compatible = "qcom,sm8650-tlmm"; 6168 reg = <0 0x0f100000 0 0x300000>; 6169 6170 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; 6171 6172 gpio-controller; 6173 #gpio-cells = <2>; 6174 6175 interrupt-controller; 6176 #interrupt-cells = <2>; 6177 6178 gpio-ranges = <&tlmm 0 0 211>; 6179 6180 wakeup-parent = <&pdc>; 6181 6182 cam0_default: cam0-default-state { 6183 pins = "gpio100"; 6184 function = "cam_mclk"; 6185 drive-strength = <2>; 6186 bias-disable; 6187 }; 6188 6189 cam0_sleep: cam0-sleep-state { 6190 pins = "gpio100"; 6191 function = "cam_mclk"; 6192 drive-strength = <2>; 6193 bias-pull-down; 6194 }; 6195 6196 cam1_default: cam1-default-state { 6197 pins = "gpio101"; 6198 function = "cam_mclk"; 6199 drive-strength = <2>; 6200 bias-disable; 6201 }; 6202 6203 cam1_sleep: cam1-sleep-state { 6204 pins = "gpio101"; 6205 function = "cam_mclk"; 6206 drive-strength = <2>; 6207 bias-pull-down; 6208 }; 6209 6210 cam2_default: cam2-default-state { 6211 pins = "gpio102"; 6212 function = "cam_aon_mclk2"; 6213 drive-strength = <2>; 6214 bias-disable; 6215 }; 6216 6217 cam2_sleep: cam2-sleep-state { 6218 pins = "gpio102"; 6219 function = "cam_aon_mclk2"; 6220 drive-strength = <2>; 6221 bias-pull-down; 6222 }; 6223 6224 cam3_default: cam3-default-state { 6225 pins = "gpio103"; 6226 function = "cam_mclk"; 6227 drive-strength = <2>; 6228 bias-disable; 6229 }; 6230 6231 cam3_sleep: cam3-sleep-state { 6232 pins = "gpio103"; 6233 function = "cam_mclk"; 6234 drive-strength = <2>; 6235 bias-pull-down; 6236 }; 6237 6238 cam4_default: cam4-default-state { 6239 pins = "gpio104"; 6240 function = "cam_aon_mclk4"; 6241 drive-strength = <2>; 6242 bias-disable; 6243 }; 6244 6245 cam4_sleep: cam4-sleep-state { 6246 pins = "gpio104"; 6247 function = "cam_aon_mclk4"; 6248 drive-strength = <2>; 6249 bias-pull-down; 6250 }; 6251 6252 cam5_default: cam5-default-state { 6253 pins = "gpio105"; 6254 function = "cam_mclk"; 6255 drive-strength = <2>; 6256 bias-disable; 6257 }; 6258 6259 cam5_sleep: cam5-sleep-state { 6260 pins = "gpio105"; 6261 function = "cam_mclk"; 6262 drive-strength = <2>; 6263 bias-pull-down; 6264 }; 6265 6266 cam6_default: cam6-default-state { 6267 pins = "gpio108"; 6268 function = "cam_mclk"; 6269 drive-strength = <2>; 6270 bias-disable; 6271 }; 6272 6273 cam6_sleep: cam6-sleep-state { 6274 pins = "gpio108"; 6275 function = "cam_mclk"; 6276 drive-strength = <2>; 6277 bias-pull-down; 6278 }; 6279 6280 cam7_default: cam7-default-state { 6281 pins = "gpio106"; 6282 function = "cam_mclk"; 6283 drive-strength = <2>; 6284 bias-disable; 6285 }; 6286 6287 cam7_sleep: cam7-sleep-state { 6288 pins = "gpio106"; 6289 function = "cam_mclk"; 6290 drive-strength = <2>; 6291 bias-pull-down; 6292 }; 6293 6294 cci0_0_default: cci0-0-default-state { 6295 sda-pins { 6296 pins = "gpio113"; 6297 function = "cci_i2c_sda"; 6298 drive-strength = <2>; 6299 bias-pull-up = <2200>; 6300 }; 6301 6302 scl-pins { 6303 pins = "gpio114"; 6304 function = "cci_i2c_scl"; 6305 drive-strength = <2>; 6306 bias-pull-up = <2200>; 6307 }; 6308 }; 6309 6310 cci0_0_sleep: cci0-0-sleep-state { 6311 sda-pins { 6312 pins = "gpio113"; 6313 function = "cci_i2c_sda"; 6314 drive-strength = <2>; 6315 bias-pull-down; 6316 }; 6317 6318 scl-pins { 6319 pins = "gpio114"; 6320 function = "cci_i2c_scl"; 6321 drive-strength = <2>; 6322 bias-pull-down; 6323 }; 6324 }; 6325 6326 cci0_1_default: cci0-1-default-state { 6327 sda-pins { 6328 pins = "gpio115"; 6329 function = "cci_i2c_sda"; 6330 drive-strength = <2>; 6331 bias-pull-up = <2200>; 6332 }; 6333 6334 scl-pins { 6335 pins = "gpio116"; 6336 function = "cci_i2c_scl"; 6337 drive-strength = <2>; 6338 bias-pull-up = <2200>; 6339 }; 6340 }; 6341 6342 cci0_1_sleep: cci0-1-sleep-state { 6343 sda-pins { 6344 pins = "gpio115"; 6345 function = "cci_i2c_sda"; 6346 drive-strength = <2>; 6347 bias-pull-down; 6348 }; 6349 6350 scl-pins { 6351 pins = "gpio116"; 6352 function = "cci_i2c_scl"; 6353 drive-strength = <2>; 6354 bias-pull-down; 6355 }; 6356 }; 6357 6358 cci1_0_default: cci1-0-default-state { 6359 sda-pins { 6360 pins = "gpio117"; 6361 function = "cci_i2c_sda"; 6362 drive-strength = <2>; 6363 bias-pull-up = <2200>; 6364 }; 6365 6366 scl-pins { 6367 pins = "gpio118"; 6368 function = "cci_i2c_scl"; 6369 drive-strength = <2>; 6370 bias-pull-up = <2200>; 6371 }; 6372 }; 6373 6374 cci1_0_sleep: cci1-0-sleep-state { 6375 sda-pins { 6376 pins = "gpio117"; 6377 function = "cci_i2c_sda"; 6378 drive-strength = <2>; 6379 bias-pull-down; 6380 }; 6381 6382 scl-pins { 6383 pins = "gpio118"; 6384 function = "cci_i2c_scl"; 6385 drive-strength = <2>; 6386 bias-pull-down; 6387 }; 6388 }; 6389 6390 cci1_1_default: cci1-1-default-state { 6391 sda-pins { 6392 pins = "gpio12"; 6393 function = "cci_i2c_sda"; 6394 drive-strength = <2>; 6395 bias-pull-up = <2200>; 6396 }; 6397 6398 scl-pins { 6399 pins = "gpio13"; 6400 function = "cci_i2c_scl"; 6401 drive-strength = <2>; 6402 bias-pull-up = <2200>; 6403 }; 6404 }; 6405 6406 cci1_1_sleep: cci1-1-sleep-state { 6407 sda-pins { 6408 pins = "gpio12"; 6409 function = "cci_i2c_sda"; 6410 drive-strength = <2>; 6411 bias-pull-down; 6412 }; 6413 6414 scl-pins { 6415 pins = "gpio13"; 6416 function = "cci_i2c_scl"; 6417 drive-strength = <2>; 6418 bias-pull-down; 6419 }; 6420 }; 6421 6422 cci2_0_default: cci2-0-default-state { 6423 sda-pins { 6424 pins = "gpio112"; 6425 function = "cci_i2c_sda"; 6426 drive-strength = <2>; 6427 bias-pull-up = <2200>; 6428 }; 6429 6430 scl-pins { 6431 pins = "gpio153"; 6432 function = "cci_i2c_scl"; 6433 drive-strength = <2>; 6434 bias-pull-up = <2200>; 6435 }; 6436 }; 6437 6438 cci2_0_sleep: cci2-0-sleep-state { 6439 sda-pins { 6440 pins = "gpio112"; 6441 function = "cci_i2c_sda"; 6442 drive-strength = <2>; 6443 bias-pull-down; 6444 }; 6445 6446 scl-pins { 6447 pins = "gpio153"; 6448 function = "cci_i2c_scl"; 6449 drive-strength = <2>; 6450 bias-pull-down; 6451 }; 6452 }; 6453 6454 cci2_1_default: cci2-1-default-state { 6455 sda-pins { 6456 pins = "gpio119"; 6457 function = "cci_i2c_sda"; 6458 drive-strength = <2>; 6459 bias-pull-up = <2200>; 6460 }; 6461 6462 scl-pins { 6463 pins = "gpio120"; 6464 function = "cci_i2c_scl"; 6465 drive-strength = <2>; 6466 bias-pull-up = <2200>; 6467 }; 6468 }; 6469 6470 cci2_1_sleep: cci2-1-sleep-state { 6471 sda-pins { 6472 pins = "gpio119"; 6473 function = "cci_i2c_sda"; 6474 drive-strength = <2>; 6475 bias-pull-down; 6476 }; 6477 6478 scl-pins { 6479 pins = "gpio120"; 6480 function = "cci_i2c_scl"; 6481 drive-strength = <2>; 6482 bias-pull-down; 6483 }; 6484 }; 6485 6486 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 6487 /* SDA, SCL */ 6488 pins = "gpio64", "gpio65"; 6489 function = "i2chub0_se0"; 6490 drive-strength = <2>; 6491 bias-pull-up; 6492 }; 6493 6494 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 6495 /* SDA, SCL */ 6496 pins = "gpio66", "gpio67"; 6497 function = "i2chub0_se1"; 6498 drive-strength = <2>; 6499 bias-pull-up; 6500 }; 6501 6502 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 6503 /* SDA, SCL */ 6504 pins = "gpio68", "gpio69"; 6505 function = "i2chub0_se2"; 6506 drive-strength = <2>; 6507 bias-pull-up; 6508 }; 6509 6510 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 6511 /* SDA, SCL */ 6512 pins = "gpio70", "gpio71"; 6513 function = "i2chub0_se3"; 6514 drive-strength = <2>; 6515 bias-pull-up; 6516 }; 6517 6518 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 6519 /* SDA, SCL */ 6520 pins = "gpio72", "gpio73"; 6521 function = "i2chub0_se4"; 6522 drive-strength = <2>; 6523 bias-pull-up; 6524 }; 6525 6526 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 6527 /* SDA, SCL */ 6528 pins = "gpio74", "gpio75"; 6529 function = "i2chub0_se5"; 6530 drive-strength = <2>; 6531 bias-pull-up; 6532 }; 6533 6534 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 6535 /* SDA, SCL */ 6536 pins = "gpio76", "gpio77"; 6537 function = "i2chub0_se6"; 6538 drive-strength = <2>; 6539 bias-pull-up; 6540 }; 6541 6542 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 6543 /* SDA, SCL */ 6544 pins = "gpio78", "gpio79"; 6545 function = "i2chub0_se7"; 6546 drive-strength = <2>; 6547 bias-pull-up; 6548 }; 6549 6550 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 6551 /* SDA, SCL */ 6552 pins = "gpio206", "gpio207"; 6553 function = "i2chub0_se8"; 6554 drive-strength = <2>; 6555 bias-pull-up; 6556 }; 6557 6558 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 6559 /* SDA, SCL */ 6560 pins = "gpio80", "gpio81"; 6561 function = "i2chub0_se9"; 6562 drive-strength = <2>; 6563 bias-pull-up; 6564 }; 6565 6566 pcie0_default_state: pcie0-default-state { 6567 perst-pins { 6568 pins = "gpio94"; 6569 function = "gpio"; 6570 drive-strength = <2>; 6571 bias-pull-down; 6572 }; 6573 6574 clkreq-pins { 6575 pins = "gpio95"; 6576 function = "pcie0_clk_req_n"; 6577 drive-strength = <2>; 6578 bias-pull-up; 6579 }; 6580 6581 wake-pins { 6582 pins = "gpio96"; 6583 function = "gpio"; 6584 drive-strength = <2>; 6585 bias-pull-up; 6586 }; 6587 }; 6588 6589 pcie1_default_state: pcie1-default-state { 6590 perst-pins { 6591 pins = "gpio97"; 6592 function = "gpio"; 6593 drive-strength = <2>; 6594 bias-pull-down; 6595 }; 6596 6597 clkreq-pins { 6598 pins = "gpio98"; 6599 function = "pcie1_clk_req_n"; 6600 drive-strength = <2>; 6601 bias-pull-up; 6602 }; 6603 6604 wake-pins { 6605 pins = "gpio99"; 6606 function = "gpio"; 6607 drive-strength = <2>; 6608 bias-pull-up; 6609 }; 6610 }; 6611 6612 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 6613 /* SDA, SCL */ 6614 pins = "gpio32", "gpio33"; 6615 function = "qup1_se0"; 6616 drive-strength = <2>; 6617 bias-pull-up; 6618 }; 6619 6620 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 6621 /* SDA, SCL */ 6622 pins = "gpio36", "gpio37"; 6623 function = "qup1_se1"; 6624 drive-strength = <2>; 6625 bias-pull-up; 6626 }; 6627 6628 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 6629 /* SDA, SCL */ 6630 pins = "gpio40", "gpio41"; 6631 function = "qup1_se2"; 6632 drive-strength = <2>; 6633 bias-pull-up; 6634 }; 6635 6636 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 6637 /* SDA, SCL */ 6638 pins = "gpio44", "gpio45"; 6639 function = "qup1_se3"; 6640 drive-strength = <2>; 6641 bias-pull-up; 6642 }; 6643 6644 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 6645 /* SDA, SCL */ 6646 pins = "gpio48", "gpio49"; 6647 function = "qup1_se4"; 6648 drive-strength = <2>; 6649 bias-pull-up; 6650 }; 6651 6652 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 6653 /* SDA, SCL */ 6654 pins = "gpio52", "gpio53"; 6655 function = "qup1_se5"; 6656 drive-strength = <2>; 6657 bias-pull-up; 6658 }; 6659 6660 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 6661 /* SDA, SCL */ 6662 pins = "gpio56", "gpio57"; 6663 function = "qup1_se6"; 6664 drive-strength = <2>; 6665 bias-pull-up; 6666 }; 6667 6668 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 6669 /* SDA, SCL */ 6670 pins = "gpio60", "gpio61"; 6671 function = "qup1_se7"; 6672 drive-strength = <2>; 6673 bias-pull-up; 6674 }; 6675 6676 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 6677 /* SDA, SCL */ 6678 pins = "gpio0", "gpio1"; 6679 function = "qup2_se0"; 6680 drive-strength = <2>; 6681 bias-pull-up; 6682 }; 6683 6684 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 6685 /* SDA, SCL */ 6686 pins = "gpio4", "gpio5"; 6687 function = "qup2_se1"; 6688 drive-strength = <2>; 6689 bias-pull-up; 6690 }; 6691 6692 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 6693 /* SDA, SCL */ 6694 pins = "gpio8", "gpio9"; 6695 function = "qup2_se2"; 6696 drive-strength = <2>; 6697 bias-pull-up; 6698 }; 6699 6700 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 6701 /* SDA, SCL */ 6702 pins = "gpio12", "gpio13"; 6703 function = "qup2_se3"; 6704 drive-strength = <2>; 6705 bias-pull-up; 6706 }; 6707 6708 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 6709 /* SDA, SCL */ 6710 pins = "gpio16", "gpio17"; 6711 function = "qup2_se4"; 6712 drive-strength = <2>; 6713 bias-pull-up; 6714 }; 6715 6716 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 6717 /* SDA, SCL */ 6718 pins = "gpio20", "gpio21"; 6719 function = "qup2_se5"; 6720 drive-strength = <2>; 6721 bias-pull-up; 6722 }; 6723 6724 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 6725 /* SDA, SCL */ 6726 pins = "gpio24", "gpio25"; 6727 function = "qup2_se6"; 6728 drive-strength = <2>; 6729 bias-pull-up; 6730 }; 6731 6732 qup_spi0_cs: qup-spi0-cs-state { 6733 pins = "gpio35"; 6734 function = "qup1_se0"; 6735 drive-strength = <6>; 6736 bias-disable; 6737 }; 6738 6739 qup_spi0_data_clk: qup-spi0-data-clk-state { 6740 /* MISO, MOSI, CLK */ 6741 pins = "gpio32", "gpio33", "gpio34"; 6742 function = "qup1_se0"; 6743 drive-strength = <6>; 6744 bias-disable; 6745 }; 6746 6747 qup_spi1_cs: qup-spi1-cs-state { 6748 pins = "gpio39"; 6749 function = "qup1_se1"; 6750 drive-strength = <6>; 6751 bias-disable; 6752 }; 6753 6754 qup_spi1_data_clk: qup-spi1-data-clk-state { 6755 /* MISO, MOSI, CLK */ 6756 pins = "gpio36", "gpio37", "gpio38"; 6757 function = "qup1_se1"; 6758 drive-strength = <6>; 6759 bias-disable; 6760 }; 6761 6762 qup_spi2_cs: qup-spi2-cs-state { 6763 pins = "gpio43"; 6764 function = "qup1_se2"; 6765 drive-strength = <6>; 6766 bias-disable; 6767 }; 6768 6769 qup_spi2_data_clk: qup-spi2-data-clk-state { 6770 /* MISO, MOSI, CLK */ 6771 pins = "gpio40", "gpio41", "gpio42"; 6772 function = "qup1_se2"; 6773 drive-strength = <6>; 6774 bias-disable; 6775 }; 6776 6777 qup_spi3_cs: qup-spi3-cs-state { 6778 pins = "gpio47"; 6779 function = "qup1_se3"; 6780 drive-strength = <6>; 6781 bias-disable; 6782 }; 6783 6784 qup_spi3_data_clk: qup-spi3-data-clk-state { 6785 /* MISO, MOSI, CLK */ 6786 pins = "gpio44", "gpio45", "gpio46"; 6787 function = "qup1_se3"; 6788 drive-strength = <6>; 6789 bias-disable; 6790 }; 6791 6792 qup_spi4_cs: qup-spi4-cs-state { 6793 pins = "gpio51"; 6794 function = "qup1_se4"; 6795 drive-strength = <6>; 6796 bias-disable; 6797 }; 6798 6799 qup_spi4_data_clk: qup-spi4-data-clk-state { 6800 /* MISO, MOSI, CLK */ 6801 pins = "gpio48", "gpio49", "gpio50"; 6802 function = "qup1_se4"; 6803 drive-strength = <6>; 6804 bias-disable; 6805 }; 6806 6807 qup_spi5_cs: qup-spi5-cs-state { 6808 pins = "gpio55"; 6809 function = "qup1_se5"; 6810 drive-strength = <6>; 6811 bias-disable; 6812 }; 6813 6814 qup_spi5_data_clk: qup-spi5-data-clk-state { 6815 /* MISO, MOSI, CLK */ 6816 pins = "gpio52", "gpio53", "gpio54"; 6817 function = "qup1_se5"; 6818 drive-strength = <6>; 6819 bias-disable; 6820 }; 6821 6822 qup_spi6_cs: qup-spi6-cs-state { 6823 pins = "gpio59"; 6824 function = "qup1_se6"; 6825 drive-strength = <6>; 6826 bias-disable; 6827 }; 6828 6829 qup_spi6_data_clk: qup-spi6-data-clk-state { 6830 /* MISO, MOSI, CLK */ 6831 pins = "gpio56", "gpio57", "gpio58"; 6832 function = "qup1_se6"; 6833 drive-strength = <6>; 6834 bias-disable; 6835 }; 6836 6837 qup_spi7_cs: qup-spi7-cs-state { 6838 pins = "gpio63"; 6839 function = "qup1_se7"; 6840 drive-strength = <6>; 6841 bias-disable; 6842 }; 6843 6844 qup_spi7_data_clk: qup-spi7-data-clk-state { 6845 /* MISO, MOSI, CLK */ 6846 pins = "gpio60", "gpio61", "gpio62"; 6847 function = "qup1_se7"; 6848 drive-strength = <6>; 6849 bias-disable; 6850 }; 6851 6852 qup_spi8_cs: qup-spi8-cs-state { 6853 pins = "gpio3"; 6854 function = "qup2_se0"; 6855 drive-strength = <6>; 6856 bias-disable; 6857 }; 6858 6859 qup_spi8_data_clk: qup-spi8-data-clk-state { 6860 /* MISO, MOSI, CLK */ 6861 pins = "gpio0", "gpio1", "gpio2"; 6862 function = "qup2_se0"; 6863 drive-strength = <6>; 6864 bias-disable; 6865 }; 6866 6867 qup_spi9_cs: qup-spi9-cs-state { 6868 pins = "gpio7"; 6869 function = "qup2_se1"; 6870 drive-strength = <6>; 6871 bias-disable; 6872 }; 6873 6874 qup_spi9_data_clk: qup-spi9-data-clk-state { 6875 /* MISO, MOSI, CLK */ 6876 pins = "gpio4", "gpio5", "gpio6"; 6877 function = "qup2_se1"; 6878 drive-strength = <6>; 6879 bias-disable; 6880 }; 6881 6882 qup_spi10_cs: qup-spi10-cs-state { 6883 pins = "gpio11"; 6884 function = "qup2_se2"; 6885 drive-strength = <6>; 6886 bias-disable; 6887 }; 6888 6889 qup_spi10_data_clk: qup-spi10-data-clk-state { 6890 /* MISO, MOSI, CLK */ 6891 pins = "gpio8", "gpio9", "gpio10"; 6892 function = "qup2_se2"; 6893 drive-strength = <6>; 6894 bias-disable; 6895 }; 6896 6897 qup_spi11_cs: qup-spi11-cs-state { 6898 pins = "gpio15"; 6899 function = "qup2_se3"; 6900 drive-strength = <6>; 6901 bias-disable; 6902 }; 6903 6904 qup_spi11_data_clk: qup-spi11-data-clk-state { 6905 /* MISO, MOSI, CLK */ 6906 pins = "gpio12", "gpio13", "gpio14"; 6907 function = "qup2_se3"; 6908 drive-strength = <6>; 6909 bias-disable; 6910 }; 6911 6912 qup_spi12_cs: qup-spi12-cs-state { 6913 pins = "gpio19"; 6914 function = "qup2_se4"; 6915 drive-strength = <6>; 6916 bias-disable; 6917 }; 6918 6919 qup_spi12_data_clk: qup-spi12-data-clk-state { 6920 /* MISO, MOSI, CLK */ 6921 pins = "gpio16", "gpio17", "gpio18"; 6922 function = "qup2_se4"; 6923 drive-strength = <6>; 6924 bias-disable; 6925 }; 6926 6927 qup_spi13_cs: qup-spi13-cs-state { 6928 pins = "gpio23"; 6929 function = "qup2_se5"; 6930 drive-strength = <6>; 6931 bias-disable; 6932 }; 6933 6934 qup_spi13_data_clk: qup-spi13-data-clk-state { 6935 /* MISO, MOSI, CLK */ 6936 pins = "gpio20", "gpio21", "gpio22"; 6937 function = "qup2_se5"; 6938 drive-strength = <6>; 6939 bias-disable; 6940 }; 6941 6942 qup_spi14_cs: qup-spi14-cs-state { 6943 pins = "gpio27"; 6944 function = "qup2_se6"; 6945 drive-strength = <6>; 6946 bias-disable; 6947 }; 6948 6949 qup_spi14_data_clk: qup-spi14-data-clk-state { 6950 /* MISO, MOSI, CLK */ 6951 pins = "gpio24", "gpio25", "gpio26"; 6952 function = "qup2_se6"; 6953 drive-strength = <6>; 6954 bias-disable; 6955 }; 6956 6957 qup_uart14_default: qup-uart14-default-state { 6958 /* TX, RX */ 6959 pins = "gpio26", "gpio27"; 6960 function = "qup2_se6"; 6961 drive-strength = <2>; 6962 bias-pull-up; 6963 }; 6964 6965 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 6966 /* CTS, RTS */ 6967 pins = "gpio24", "gpio25"; 6968 function = "qup2_se6"; 6969 drive-strength = <2>; 6970 bias-pull-down; 6971 }; 6972 6973 qup_uart15_default: qup-uart15-default-state { 6974 /* TX, RX */ 6975 pins = "gpio30", "gpio31"; 6976 function = "qup2_se7"; 6977 drive-strength = <2>; 6978 bias-disable; 6979 }; 6980 6981 sdc2_sleep: sdc2-sleep-state { 6982 clk-pins { 6983 pins = "sdc2_clk"; 6984 drive-strength = <2>; 6985 bias-disable; 6986 }; 6987 6988 cmd-pins { 6989 pins = "sdc2_cmd"; 6990 drive-strength = <2>; 6991 bias-pull-up; 6992 }; 6993 6994 data-pins { 6995 pins = "sdc2_data"; 6996 drive-strength = <2>; 6997 bias-pull-up; 6998 }; 6999 }; 7000 7001 sdc2_default: sdc2-default-state { 7002 clk-pins { 7003 pins = "sdc2_clk"; 7004 drive-strength = <16>; 7005 bias-disable; 7006 }; 7007 7008 cmd-pins { 7009 pins = "sdc2_cmd"; 7010 drive-strength = <10>; 7011 bias-pull-up; 7012 }; 7013 7014 data-pins { 7015 pins = "sdc2_data"; 7016 drive-strength = <10>; 7017 bias-pull-up; 7018 }; 7019 }; 7020 }; 7021 7022 funnel@10042000 { 7023 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7024 7025 reg = <0x0 0x10042000 0x0 0x1000>; 7026 7027 clocks = <&aoss_qmp>; 7028 clock-names = "apb_pclk"; 7029 7030 in-ports { 7031 #address-cells = <1>; 7032 #size-cells = <0>; 7033 7034 port@4 { 7035 reg = <4>; 7036 7037 funnel_in1_in_funnel_apss: endpoint { 7038 remote-endpoint = <&funnel_apss_out_funnel_in1>; 7039 }; 7040 }; 7041 }; 7042 7043 out-ports { 7044 port { 7045 funnel_in1_out_funnel_qdss: endpoint { 7046 remote-endpoint = <&funnel_qdss_in_funnel_in1>; 7047 }; 7048 }; 7049 }; 7050 }; 7051 7052 funnel@10045000 { 7053 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7054 7055 reg = <0x0 0x10045000 0x0 0x1000>; 7056 7057 clocks = <&aoss_qmp>; 7058 clock-names = "apb_pclk"; 7059 7060 in-ports { 7061 #address-cells = <1>; 7062 #size-cells = <0>; 7063 7064 port@1 { 7065 reg = <1>; 7066 7067 funnel_qdss_in_funnel_in1: endpoint { 7068 remote-endpoint = <&funnel_in1_out_funnel_qdss>; 7069 }; 7070 }; 7071 }; 7072 7073 out-ports { 7074 port { 7075 funnel_qdss_out_funnel_aoss: endpoint { 7076 remote-endpoint = <&funnel_aoss_in_funnel_qdss>; 7077 }; 7078 }; 7079 }; 7080 }; 7081 7082 funnel@10b04000 { 7083 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7084 7085 reg = <0x0 0x10b04000 0x0 0x1000>; 7086 7087 clocks = <&aoss_qmp>; 7088 clock-names = "apb_pclk"; 7089 7090 in-ports { 7091 #address-cells = <1>; 7092 #size-cells = <0>; 7093 7094 port@7 { 7095 reg = <7>; 7096 7097 funnel_aoss_in_funnel_qdss: endpoint { 7098 remote-endpoint = <&funnel_qdss_out_funnel_aoss>; 7099 }; 7100 }; 7101 }; 7102 7103 out-ports { 7104 port { 7105 funnel_aoss_out_tmc_etf: endpoint { 7106 remote-endpoint = <&tmc_etf_in_funnel_aoss>; 7107 }; 7108 }; 7109 }; 7110 }; 7111 7112 tmc@10b05000 { 7113 compatible = "arm,coresight-tmc", "arm,primecell"; 7114 7115 reg = <0x0 0x10b05000 0x0 0x1000>; 7116 7117 clocks = <&aoss_qmp>; 7118 clock-names = "apb_pclk"; 7119 7120 in-ports { 7121 port { 7122 tmc_etf_in_funnel_aoss: endpoint { 7123 remote-endpoint = <&funnel_aoss_out_tmc_etf>; 7124 }; 7125 }; 7126 }; 7127 }; 7128 7129 funnel@13810000 { 7130 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7131 7132 reg = <0x0 0x13810000 0x0 0x1000>; 7133 7134 clocks = <&aoss_qmp>; 7135 clock-names = "apb_pclk"; 7136 7137 in-ports { 7138 port { 7139 funnel_apss_in_funnel_ete: endpoint { 7140 remote-endpoint = <&funnel_ete_out_funnel_apss>; 7141 }; 7142 }; 7143 }; 7144 7145 out-ports { 7146 port { 7147 funnel_apss_out_funnel_in1: endpoint { 7148 remote-endpoint = <&funnel_in1_in_funnel_apss>; 7149 }; 7150 }; 7151 }; 7152 }; 7153 7154 sram@14680000 { 7155 compatible = "qcom,sm8650-imem", "syscon", "simple-mfd"; 7156 reg = <0 0x14680000 0 0x2c000>; 7157 7158 #address-cells = <1>; 7159 #size-cells = <1>; 7160 7161 ranges = <0 0 0x14680000 0x2c000>; 7162 7163 ipa_modem_tables: modem-tables@3000 { 7164 reg = <0x3000 0x2000>; 7165 }; 7166 }; 7167 7168 apps_smmu: iommu@15000000 { 7169 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 7170 reg = <0 0x15000000 0 0x100000>; 7171 7172 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, 7173 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, 7174 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, 7175 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, 7176 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, 7177 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 7178 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, 7179 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 7180 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 7181 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, 7182 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, 7183 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 7184 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 7185 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 7186 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, 7187 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, 7188 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, 7189 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, 7190 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 7191 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, 7192 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, 7193 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, 7194 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, 7195 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, 7196 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, 7197 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, 7198 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, 7199 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, 7200 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, 7201 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, 7202 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, 7203 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, 7204 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, 7205 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, 7206 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, 7207 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, 7208 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, 7209 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, 7210 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, 7211 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, 7212 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, 7213 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, 7214 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, 7215 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, 7216 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, 7217 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, 7218 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, 7219 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, 7220 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, 7221 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, 7222 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, 7223 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, 7224 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, 7225 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, 7226 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, 7227 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, 7228 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, 7229 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, 7230 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, 7231 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, 7232 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, 7233 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>, 7234 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>, 7235 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>, 7236 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>, 7237 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>, 7238 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>, 7239 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 7240 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 7241 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>, 7242 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>, 7243 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>, 7244 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>, 7245 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>, 7246 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>, 7247 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>, 7248 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>, 7249 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>, 7250 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, 7251 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, 7252 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, 7253 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, 7254 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, 7255 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>, 7256 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>, 7257 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>, 7258 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>, 7259 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>, 7260 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>, 7261 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>, 7262 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>, 7263 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>, 7264 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>, 7265 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>, 7266 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>, 7267 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>, 7268 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>; 7269 7270 #iommu-cells = <2>; 7271 #global-interrupts = <1>; 7272 7273 dma-coherent; 7274 }; 7275 7276 intc: interrupt-controller@17100000 { 7277 compatible = "arm,gic-v3"; 7278 reg = <0 0x17100000 0 0x10000>, /* GICD */ 7279 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 7280 7281 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>; 7282 7283 #interrupt-cells = <4>; 7284 interrupt-controller; 7285 7286 #redistributor-regions = <1>; 7287 redistributor-stride = <0 0x40000>; 7288 7289 #address-cells = <2>; 7290 #size-cells = <2>; 7291 ranges; 7292 7293 ppi-partitions { 7294 ppi_cluster0: interrupt-partition-0 { 7295 affinity = <&cpu0 &cpu1>; 7296 }; 7297 7298 ppi_cluster1: interrupt-partition-1 { 7299 affinity = <&cpu2 &cpu3 &cpu4 &cpu5 &cpu6>; 7300 }; 7301 7302 ppi_cluster2: interrupt-partition-2 { 7303 affinity = <&cpu7>; 7304 }; 7305 }; 7306 7307 gic_its: msi-controller@17140000 { 7308 compatible = "arm,gic-v3-its"; 7309 reg = <0 0x17140000 0 0x40000>; 7310 7311 msi-controller; 7312 #msi-cells = <1>; 7313 }; 7314 }; 7315 7316 timer@17420000 { 7317 compatible = "arm,armv7-timer-mem"; 7318 reg = <0 0x17420000 0 0x1000>; 7319 7320 ranges = <0 0 0 0x20000000>; 7321 #address-cells = <1>; 7322 #size-cells = <1>; 7323 7324 frame@17421000 { 7325 reg = <0x17421000 0x1000>, 7326 <0x17422000 0x1000>; 7327 7328 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, 7329 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 7330 7331 frame-number = <0>; 7332 }; 7333 7334 frame@17423000 { 7335 reg = <0x17423000 0x1000>; 7336 7337 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 7338 7339 frame-number = <1>; 7340 7341 status = "disabled"; 7342 }; 7343 7344 frame@17425000 { 7345 reg = <0x17425000 0x1000>; 7346 7347 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 7348 7349 frame-number = <2>; 7350 7351 status = "disabled"; 7352 }; 7353 7354 frame@17427000 { 7355 reg = <0x17427000 0x1000>; 7356 7357 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 7358 7359 frame-number = <3>; 7360 7361 status = "disabled"; 7362 }; 7363 7364 frame@17429000 { 7365 reg = <0x17429000 0x1000>; 7366 7367 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 7368 7369 frame-number = <4>; 7370 7371 status = "disabled"; 7372 }; 7373 7374 frame@1742b000 { 7375 reg = <0x1742b000 0x1000>; 7376 7377 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; 7378 7379 frame-number = <5>; 7380 7381 status = "disabled"; 7382 }; 7383 7384 frame@1742d000 { 7385 reg = <0x1742d000 0x1000>; 7386 7387 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 7388 7389 frame-number = <6>; 7390 7391 status = "disabled"; 7392 }; 7393 }; 7394 7395 apps_rsc: rsc@17a00000 { 7396 compatible = "qcom,rpmh-rsc"; 7397 reg = <0 0x17a00000 0 0x10000>, 7398 <0 0x17a10000 0 0x10000>, 7399 <0 0x17a20000 0 0x10000>; 7400 reg-names = "drv-0", 7401 "drv-1", 7402 "drv-2"; 7403 7404 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, 7405 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, 7406 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; 7407 7408 power-domains = <&cluster_pd>; 7409 7410 qcom,tcs-offset = <0xd00>; 7411 qcom,drv-id = <2>; 7412 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 7413 <WAKE_TCS 2>, <CONTROL_TCS 0>; 7414 7415 label = "apps_rsc"; 7416 7417 apps_bcm_voter: bcm-voter { 7418 compatible = "qcom,bcm-voter"; 7419 }; 7420 7421 rpmhcc: clock-controller { 7422 compatible = "qcom,sm8650-rpmh-clk"; 7423 7424 clocks = <&xo_board>; 7425 clock-names = "xo"; 7426 7427 #clock-cells = <1>; 7428 }; 7429 7430 rpmhpd: power-controller { 7431 compatible = "qcom,sm8650-rpmhpd"; 7432 7433 operating-points-v2 = <&rpmhpd_opp_table>; 7434 7435 #power-domain-cells = <1>; 7436 7437 rpmhpd_opp_table: opp-table { 7438 compatible = "operating-points-v2"; 7439 7440 rpmhpd_opp_ret: opp-16 { 7441 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 7442 }; 7443 7444 rpmhpd_opp_min_svs: opp-48 { 7445 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 7446 }; 7447 7448 rpmhpd_opp_low_svs_d2: opp-52 { 7449 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 7450 }; 7451 7452 rpmhpd_opp_low_svs_d1: opp-56 { 7453 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 7454 }; 7455 7456 rpmhpd_opp_low_svs_d0: opp-60 { 7457 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 7458 }; 7459 7460 rpmhpd_opp_low_svs: opp-64 { 7461 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 7462 }; 7463 7464 rpmhpd_opp_low_svs_l1: opp-80 { 7465 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 7466 }; 7467 7468 rpmhpd_opp_svs: opp-128 { 7469 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 7470 }; 7471 7472 rpmhpd_opp_svs_l0: opp-144 { 7473 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 7474 }; 7475 7476 rpmhpd_opp_svs_l1: opp-192 { 7477 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 7478 }; 7479 7480 rpmhpd_opp_nom: opp-256 { 7481 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 7482 }; 7483 7484 rpmhpd_opp_nom_l1: opp-320 { 7485 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 7486 }; 7487 7488 rpmhpd_opp_nom_l2: opp-336 { 7489 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 7490 }; 7491 7492 rpmhpd_opp_turbo: opp-384 { 7493 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 7494 }; 7495 7496 rpmhpd_opp_turbo_l1: opp-416 { 7497 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 7498 }; 7499 }; 7500 }; 7501 }; 7502 7503 epss_l3: interconnect@17d90000 { 7504 compatible = "qcom,sm8650-epss-l3", "qcom,epss-l3"; 7505 reg = <0 0x17d90000 0 0x1000>; 7506 7507 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 7508 clock-names = "xo", "alternate"; 7509 7510 #interconnect-cells = <1>; 7511 }; 7512 7513 cpufreq_hw: cpufreq@17d91000 { 7514 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss"; 7515 reg = <0 0x17d91000 0 0x1000>, 7516 <0 0x17d92000 0 0x1000>, 7517 <0 0x17d93000 0 0x1000>, 7518 <0 0x17d94000 0 0x1000>; 7519 reg-names = "freq-domain0", 7520 "freq-domain1", 7521 "freq-domain2", 7522 "freq-domain3"; 7523 7524 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, 7525 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>, 7526 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, 7527 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH 0>; 7528 interrupt-names = "dcvsh-irq-0", 7529 "dcvsh-irq-1", 7530 "dcvsh-irq-2", 7531 "dcvsh-irq-3"; 7532 7533 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 7534 clock-names = "xo", "alternate"; 7535 7536 #freq-domain-cells = <1>; 7537 #clock-cells = <1>; 7538 }; 7539 7540 pmu@24091000 { 7541 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 7542 reg = <0 0x24091000 0 0x1000>; 7543 7544 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 7545 7546 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 7547 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 7548 7549 operating-points-v2 = <&llcc_bwmon_opp_table>; 7550 7551 llcc_bwmon_opp_table: opp-table { 7552 compatible = "operating-points-v2"; 7553 7554 opp-0 { 7555 opp-peak-kBps = <2086000>; 7556 }; 7557 7558 opp-1 { 7559 opp-peak-kBps = <2929000>; 7560 }; 7561 7562 opp-2 { 7563 opp-peak-kBps = <5931000>; 7564 }; 7565 7566 opp-3 { 7567 opp-peak-kBps = <6515000>; 7568 }; 7569 7570 opp-4 { 7571 opp-peak-kBps = <7980000>; 7572 }; 7573 7574 opp-5 { 7575 opp-peak-kBps = <10437000>; 7576 }; 7577 7578 opp-6 { 7579 opp-peak-kBps = <12157000>; 7580 }; 7581 7582 opp-7 { 7583 opp-peak-kBps = <14060000>; 7584 }; 7585 7586 opp-8 { 7587 opp-peak-kBps = <16113000>; 7588 }; 7589 }; 7590 }; 7591 7592 pmu@240b7400 { 7593 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; 7594 reg = <0 0x240b7400 0 0x600>; 7595 7596 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>; 7597 7598 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 7599 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 7600 7601 operating-points-v2 = <&cpu_bwmon_opp_table>; 7602 7603 cpu_bwmon_opp_table: opp-table { 7604 compatible = "operating-points-v2"; 7605 7606 opp-0 { 7607 opp-peak-kBps = <4577000>; 7608 }; 7609 7610 opp-1 { 7611 opp-peak-kBps = <7110000>; 7612 }; 7613 7614 opp-2 { 7615 opp-peak-kBps = <9155000>; 7616 }; 7617 7618 opp-3 { 7619 opp-peak-kBps = <12298000>; 7620 }; 7621 7622 opp-4 { 7623 opp-peak-kBps = <14236000>; 7624 }; 7625 7626 opp-5 { 7627 opp-peak-kBps = <16265000>; 7628 }; 7629 }; 7630 }; 7631 7632 gem_noc: interconnect@24100000 { 7633 compatible = "qcom,sm8650-gem-noc"; 7634 reg = <0 0x24100000 0 0xc5080>; 7635 7636 qcom,bcm-voters = <&apps_bcm_voter>; 7637 7638 #interconnect-cells = <2>; 7639 }; 7640 7641 system-cache-controller@25000000 { 7642 compatible = "qcom,sm8650-llcc"; 7643 reg = <0 0x25000000 0 0x200000>, 7644 <0 0x25400000 0 0x200000>, 7645 <0 0x25200000 0 0x200000>, 7646 <0 0x25600000 0 0x200000>, 7647 <0 0x25800000 0 0x200000>, 7648 <0 0x25a00000 0 0x200000>; 7649 reg-names = "llcc0_base", 7650 "llcc1_base", 7651 "llcc2_base", 7652 "llcc3_base", 7653 "llcc_broadcast_base", 7654 "llcc_broadcast_and_base"; 7655 7656 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH 0>; 7657 }; 7658 7659 nsp_noc: interconnect@320c0000 { 7660 compatible = "qcom,sm8650-nsp-noc"; 7661 reg = <0 0x320c0000 0 0xf080>; 7662 7663 qcom,bcm-voters = <&apps_bcm_voter>; 7664 7665 #interconnect-cells = <2>; 7666 }; 7667 7668 remoteproc_cdsp: remoteproc@32300000 { 7669 compatible = "qcom,sm8650-cdsp-pas"; 7670 reg = <0x0 0x32300000 0x0 0x10000>; 7671 7672 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, 7673 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 7674 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 7675 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 7676 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 7677 interrupt-names = "wdog", 7678 "fatal", 7679 "ready", 7680 "handover", 7681 "stop-ack"; 7682 7683 clocks = <&rpmhcc RPMH_CXO_CLK>; 7684 clock-names = "xo"; 7685 7686 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 7687 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7688 7689 power-domains = <&rpmhpd RPMHPD_CX>, 7690 <&rpmhpd RPMHPD_MXC>, 7691 <&rpmhpd RPMHPD_NSP>; 7692 power-domain-names = "cx", 7693 "mxc", 7694 "nsp"; 7695 7696 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; 7697 7698 qcom,qmp = <&aoss_qmp>; 7699 7700 qcom,smem-states = <&smp2p_cdsp_out 0>; 7701 qcom,smem-state-names = "stop"; 7702 7703 status = "disabled"; 7704 7705 glink-edge { 7706 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 7707 IPCC_MPROC_SIGNAL_GLINK_QMP 7708 IRQ_TYPE_EDGE_RISING>; 7709 7710 mboxes = <&ipcc IPCC_CLIENT_CDSP 7711 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7712 7713 qcom,remote-pid = <5>; 7714 7715 label = "cdsp"; 7716 7717 fastrpc { 7718 compatible = "qcom,fastrpc"; 7719 7720 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7721 7722 label = "cdsp"; 7723 7724 qcom,non-secure-domain; 7725 7726 #address-cells = <1>; 7727 #size-cells = <0>; 7728 7729 compute-cb@1 { 7730 compatible = "qcom,fastrpc-compute-cb"; 7731 reg = <1>; 7732 7733 iommus = <&apps_smmu 0x1961 0x0>, 7734 <&apps_smmu 0x0c01 0x20>, 7735 <&apps_smmu 0x19c1 0x0>; 7736 dma-coherent; 7737 }; 7738 7739 compute-cb@2 { 7740 compatible = "qcom,fastrpc-compute-cb"; 7741 reg = <2>; 7742 7743 iommus = <&apps_smmu 0x1962 0x0>, 7744 <&apps_smmu 0x0c02 0x20>, 7745 <&apps_smmu 0x19c2 0x0>; 7746 dma-coherent; 7747 }; 7748 7749 compute-cb@3 { 7750 compatible = "qcom,fastrpc-compute-cb"; 7751 reg = <3>; 7752 7753 iommus = <&apps_smmu 0x1963 0x0>, 7754 <&apps_smmu 0x0c03 0x20>, 7755 <&apps_smmu 0x19c3 0x0>; 7756 dma-coherent; 7757 }; 7758 7759 compute-cb@4 { 7760 compatible = "qcom,fastrpc-compute-cb"; 7761 reg = <4>; 7762 7763 iommus = <&apps_smmu 0x1964 0x0>, 7764 <&apps_smmu 0x0c04 0x20>, 7765 <&apps_smmu 0x19c4 0x0>; 7766 dma-coherent; 7767 }; 7768 7769 compute-cb@5 { 7770 compatible = "qcom,fastrpc-compute-cb"; 7771 reg = <5>; 7772 7773 iommus = <&apps_smmu 0x1965 0x0>, 7774 <&apps_smmu 0x0c05 0x20>, 7775 <&apps_smmu 0x19c5 0x0>; 7776 dma-coherent; 7777 }; 7778 7779 compute-cb@6 { 7780 compatible = "qcom,fastrpc-compute-cb"; 7781 reg = <6>; 7782 7783 iommus = <&apps_smmu 0x1966 0x0>, 7784 <&apps_smmu 0x0c06 0x20>, 7785 <&apps_smmu 0x19c6 0x0>; 7786 dma-coherent; 7787 }; 7788 7789 compute-cb@7 { 7790 compatible = "qcom,fastrpc-compute-cb"; 7791 reg = <7>; 7792 7793 iommus = <&apps_smmu 0x1967 0x0>, 7794 <&apps_smmu 0x0c07 0x20>, 7795 <&apps_smmu 0x19c7 0x0>; 7796 dma-coherent; 7797 }; 7798 7799 compute-cb@8 { 7800 compatible = "qcom,fastrpc-compute-cb"; 7801 reg = <8>; 7802 7803 iommus = <&apps_smmu 0x1968 0x0>, 7804 <&apps_smmu 0x0c08 0x20>, 7805 <&apps_smmu 0x19c8 0x0>; 7806 dma-coherent; 7807 }; 7808 7809 /* note: secure cb9 in downstream */ 7810 7811 compute-cb@12 { 7812 compatible = "qcom,fastrpc-compute-cb"; 7813 reg = <12>; 7814 7815 iommus = <&apps_smmu 0x196c 0x0>, 7816 <&apps_smmu 0x0c0c 0x20>, 7817 <&apps_smmu 0x19cc 0x0>; 7818 dma-coherent; 7819 }; 7820 7821 compute-cb@13 { 7822 compatible = "qcom,fastrpc-compute-cb"; 7823 reg = <13>; 7824 7825 iommus = <&apps_smmu 0x196d 0x0>, 7826 <&apps_smmu 0x0c0d 0x20>, 7827 <&apps_smmu 0x19cd 0x0>; 7828 dma-coherent; 7829 }; 7830 7831 compute-cb@14 { 7832 compatible = "qcom,fastrpc-compute-cb"; 7833 reg = <14>; 7834 7835 iommus = <&apps_smmu 0x196e 0x0>, 7836 <&apps_smmu 0x0c0e 0x20>, 7837 <&apps_smmu 0x19ce 0x0>; 7838 dma-coherent; 7839 }; 7840 }; 7841 }; 7842 }; 7843 }; 7844 7845 thermal-zones { 7846 aoss0-thermal { 7847 thermal-sensors = <&tsens0 0>; 7848 7849 trips { 7850 aoss0-hot { 7851 temperature = <110000>; 7852 hysteresis = <1000>; 7853 type = "hot"; 7854 }; 7855 7856 aoss0-critical { 7857 temperature = <115000>; 7858 hysteresis = <0>; 7859 type = "critical"; 7860 }; 7861 }; 7862 }; 7863 7864 cpuss0-thermal { 7865 thermal-sensors = <&tsens0 1>; 7866 7867 trips { 7868 cpuss0-hot { 7869 temperature = <110000>; 7870 hysteresis = <1000>; 7871 type = "hot"; 7872 }; 7873 7874 cpuss0-critical { 7875 temperature = <115000>; 7876 hysteresis = <0>; 7877 type = "critical"; 7878 }; 7879 }; 7880 }; 7881 7882 cpuss1-thermal { 7883 thermal-sensors = <&tsens0 2>; 7884 7885 trips { 7886 cpuss1-hot { 7887 temperature = <110000>; 7888 hysteresis = <1000>; 7889 type = "hot"; 7890 }; 7891 7892 cpuss1-critical { 7893 temperature = <115000>; 7894 hysteresis = <0>; 7895 type = "critical"; 7896 }; 7897 }; 7898 }; 7899 7900 cpuss2-thermal { 7901 thermal-sensors = <&tsens0 3>; 7902 7903 trips { 7904 cpuss2-hot { 7905 temperature = <110000>; 7906 hysteresis = <1000>; 7907 type = "hot"; 7908 }; 7909 7910 cpuss2-critical { 7911 temperature = <115000>; 7912 hysteresis = <0>; 7913 type = "critical"; 7914 }; 7915 }; 7916 }; 7917 7918 cpuss3-thermal { 7919 thermal-sensors = <&tsens0 4>; 7920 7921 trips { 7922 cpuss3-hot { 7923 temperature = <110000>; 7924 hysteresis = <1000>; 7925 type = "hot"; 7926 }; 7927 7928 cpuss3-critical { 7929 temperature = <115000>; 7930 hysteresis = <0>; 7931 type = "critical"; 7932 }; 7933 }; 7934 }; 7935 7936 cpu2_top_thermal: cpu2-top-thermal { 7937 thermal-sensors = <&tsens0 5>; 7938 7939 trips { 7940 cpu2-critical { 7941 temperature = <110000>; 7942 hysteresis = <1000>; 7943 type = "critical"; 7944 }; 7945 }; 7946 }; 7947 7948 cpu2-bottom-thermal { 7949 thermal-sensors = <&tsens0 6>; 7950 7951 trips { 7952 cpu2-critical { 7953 temperature = <110000>; 7954 hysteresis = <1000>; 7955 type = "critical"; 7956 }; 7957 }; 7958 }; 7959 7960 cpu3_top_thermal: cpu3-top-thermal { 7961 thermal-sensors = <&tsens0 7>; 7962 7963 trips { 7964 cpu3-critical { 7965 temperature = <110000>; 7966 hysteresis = <1000>; 7967 type = "critical"; 7968 }; 7969 }; 7970 }; 7971 7972 cpu3-bottom-thermal { 7973 thermal-sensors = <&tsens0 8>; 7974 7975 trips { 7976 cpu3-critical { 7977 temperature = <110000>; 7978 hysteresis = <1000>; 7979 type = "critical"; 7980 }; 7981 }; 7982 }; 7983 7984 cpu4_top_thermal: cpu4-top-thermal { 7985 thermal-sensors = <&tsens0 9>; 7986 7987 trips { 7988 cpu4-critical { 7989 temperature = <110000>; 7990 hysteresis = <1000>; 7991 type = "critical"; 7992 }; 7993 }; 7994 }; 7995 7996 cpu4-bottom-thermal { 7997 thermal-sensors = <&tsens0 10>; 7998 7999 trips { 8000 cpu4-critical { 8001 temperature = <110000>; 8002 hysteresis = <1000>; 8003 type = "critical"; 8004 }; 8005 }; 8006 }; 8007 8008 cpu5_top_thermal: cpu5-top-thermal { 8009 thermal-sensors = <&tsens0 11>; 8010 8011 trips { 8012 cpu5-critical { 8013 temperature = <110000>; 8014 hysteresis = <1000>; 8015 type = "critical"; 8016 }; 8017 }; 8018 }; 8019 8020 cpu5-bottom-thermal { 8021 thermal-sensors = <&tsens0 12>; 8022 8023 trips { 8024 cpu5-critical { 8025 temperature = <110000>; 8026 hysteresis = <1000>; 8027 type = "critical"; 8028 }; 8029 }; 8030 }; 8031 8032 cpu6_top_thermal: cpu6-top-thermal { 8033 thermal-sensors = <&tsens0 13>; 8034 8035 trips { 8036 cpu6-critical { 8037 temperature = <110000>; 8038 hysteresis = <1000>; 8039 type = "critical"; 8040 }; 8041 }; 8042 }; 8043 8044 cpu6-bottom-thermal { 8045 thermal-sensors = <&tsens0 14>; 8046 8047 trips { 8048 cpu6-critical { 8049 temperature = <110000>; 8050 hysteresis = <1000>; 8051 type = "critical"; 8052 }; 8053 }; 8054 }; 8055 8056 aoss1-thermal { 8057 thermal-sensors = <&tsens1 0>; 8058 8059 trips { 8060 aoss1-hot { 8061 temperature = <110000>; 8062 hysteresis = <1000>; 8063 type = "hot"; 8064 }; 8065 8066 aoss1-critical { 8067 temperature = <115000>; 8068 hysteresis = <0>; 8069 type = "critical"; 8070 }; 8071 }; 8072 }; 8073 8074 cpu7_top_thermal: cpu7-top-thermal { 8075 thermal-sensors = <&tsens1 1>; 8076 8077 trips { 8078 cpu7-critical { 8079 temperature = <110000>; 8080 hysteresis = <1000>; 8081 type = "critical"; 8082 }; 8083 }; 8084 }; 8085 8086 cpu7-middle-thermal { 8087 thermal-sensors = <&tsens1 2>; 8088 8089 trips { 8090 cpu7-critical { 8091 temperature = <110000>; 8092 hysteresis = <1000>; 8093 type = "critical"; 8094 }; 8095 }; 8096 }; 8097 8098 cpu7-bottom-thermal { 8099 thermal-sensors = <&tsens1 3>; 8100 8101 trips { 8102 cpu7-critical { 8103 temperature = <110000>; 8104 hysteresis = <1000>; 8105 type = "critical"; 8106 }; 8107 }; 8108 }; 8109 8110 cpu0-thermal { 8111 thermal-sensors = <&tsens1 4>; 8112 8113 trips { 8114 cpu0-critical { 8115 temperature = <110000>; 8116 hysteresis = <1000>; 8117 type = "critical"; 8118 }; 8119 }; 8120 }; 8121 8122 cpu1-thermal { 8123 thermal-sensors = <&tsens1 5>; 8124 8125 trips { 8126 cpu1-critical { 8127 temperature = <110000>; 8128 hysteresis = <1000>; 8129 type = "critical"; 8130 }; 8131 }; 8132 }; 8133 8134 nsphvx0-thermal { 8135 thermal-sensors = <&tsens2 6>; 8136 8137 trips { 8138 nsphvx0-hot { 8139 temperature = <110000>; 8140 hysteresis = <1000>; 8141 type = "hot"; 8142 }; 8143 8144 nsphvx0-critical { 8145 temperature = <115000>; 8146 hysteresis = <0>; 8147 type = "critical"; 8148 }; 8149 }; 8150 }; 8151 8152 nsphvx1-thermal { 8153 thermal-sensors = <&tsens2 7>; 8154 8155 trips { 8156 nsphvx1-hot { 8157 temperature = <110000>; 8158 hysteresis = <1000>; 8159 type = "hot"; 8160 }; 8161 8162 nsphvx1-critical { 8163 temperature = <115000>; 8164 hysteresis = <0>; 8165 type = "critical"; 8166 }; 8167 }; 8168 }; 8169 8170 nsphmx0-thermal { 8171 thermal-sensors = <&tsens2 8>; 8172 8173 trips { 8174 nsphmx0-hot { 8175 temperature = <110000>; 8176 hysteresis = <1000>; 8177 type = "hot"; 8178 }; 8179 8180 nsphmx0-critical { 8181 temperature = <115000>; 8182 hysteresis = <0>; 8183 type = "critical"; 8184 }; 8185 }; 8186 }; 8187 8188 nsphmx1-thermal { 8189 thermal-sensors = <&tsens2 9>; 8190 8191 trips { 8192 nsphmx1-hot { 8193 temperature = <110000>; 8194 hysteresis = <1000>; 8195 type = "hot"; 8196 }; 8197 8198 nsphmx1-critical { 8199 temperature = <115000>; 8200 hysteresis = <0>; 8201 type = "critical"; 8202 }; 8203 }; 8204 }; 8205 8206 nsphmx2-thermal { 8207 thermal-sensors = <&tsens2 10>; 8208 8209 trips { 8210 nsphmx2-hot { 8211 temperature = <110000>; 8212 hysteresis = <1000>; 8213 type = "hot"; 8214 }; 8215 8216 nsphmx2-critical { 8217 temperature = <115000>; 8218 hysteresis = <0>; 8219 type = "critical"; 8220 }; 8221 }; 8222 }; 8223 8224 nsphmx3-thermal { 8225 thermal-sensors = <&tsens2 11>; 8226 8227 trips { 8228 nsphmx3-hot { 8229 temperature = <110000>; 8230 hysteresis = <1000>; 8231 type = "hot"; 8232 }; 8233 8234 nsphmx3-critical { 8235 temperature = <115000>; 8236 hysteresis = <0>; 8237 type = "critical"; 8238 }; 8239 }; 8240 }; 8241 8242 video-thermal { 8243 thermal-sensors = <&tsens1 12>; 8244 8245 trips { 8246 video-hot { 8247 temperature = <110000>; 8248 hysteresis = <1000>; 8249 type = "hot"; 8250 }; 8251 8252 video-critical { 8253 temperature = <115000>; 8254 hysteresis = <0>; 8255 type = "critical"; 8256 }; 8257 }; 8258 }; 8259 8260 ddr-thermal { 8261 thermal-sensors = <&tsens1 13>; 8262 8263 trips { 8264 ddr-hot { 8265 temperature = <110000>; 8266 hysteresis = <1000>; 8267 type = "hot"; 8268 }; 8269 8270 ddr-critical { 8271 temperature = <115000>; 8272 hysteresis = <0>; 8273 type = "critical"; 8274 }; 8275 }; 8276 }; 8277 8278 camera0-thermal { 8279 thermal-sensors = <&tsens1 14>; 8280 8281 trips { 8282 camera0-hot { 8283 temperature = <110000>; 8284 hysteresis = <1000>; 8285 type = "hot"; 8286 }; 8287 8288 camera0-critical { 8289 temperature = <115000>; 8290 hysteresis = <0>; 8291 type = "critical"; 8292 }; 8293 }; 8294 }; 8295 8296 camera1-thermal { 8297 thermal-sensors = <&tsens1 15>; 8298 8299 trips { 8300 camera1-hot { 8301 temperature = <110000>; 8302 hysteresis = <1000>; 8303 type = "hot"; 8304 }; 8305 8306 camera1-critical { 8307 temperature = <115000>; 8308 hysteresis = <0>; 8309 type = "critical"; 8310 }; 8311 }; 8312 }; 8313 8314 aoss2-thermal { 8315 thermal-sensors = <&tsens2 0>; 8316 8317 trips { 8318 aoss2-hot { 8319 temperature = <110000>; 8320 hysteresis = <1000>; 8321 type = "hot"; 8322 }; 8323 8324 aoss2-critical { 8325 temperature = <115000>; 8326 hysteresis = <0>; 8327 type = "critical"; 8328 }; 8329 }; 8330 }; 8331 8332 gpuss0-thermal { 8333 polling-delay-passive = <10>; 8334 8335 thermal-sensors = <&tsens2 1>; 8336 8337 gpu0_cooling_maps: cooling-maps { 8338 map0 { 8339 trip = <&gpu0_alert0>; 8340 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8341 }; 8342 }; 8343 8344 gpu0_trips: trips { 8345 gpu0_alert0: trip-point0 { 8346 temperature = <95000>; 8347 hysteresis = <1000>; 8348 type = "passive"; 8349 }; 8350 8351 trip-point1 { 8352 temperature = <110000>; 8353 hysteresis = <1000>; 8354 type = "hot"; 8355 }; 8356 8357 trip-point2 { 8358 temperature = <115000>; 8359 hysteresis = <0>; 8360 type = "critical"; 8361 }; 8362 }; 8363 }; 8364 8365 gpuss1-thermal { 8366 polling-delay-passive = <10>; 8367 8368 thermal-sensors = <&tsens2 2>; 8369 8370 gpu1_cooling_maps: cooling-maps { 8371 map0 { 8372 trip = <&gpu1_alert0>; 8373 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8374 }; 8375 }; 8376 8377 gpu1_trips: trips { 8378 gpu1_alert0: trip-point0 { 8379 temperature = <95000>; 8380 hysteresis = <1000>; 8381 type = "passive"; 8382 }; 8383 8384 trip-point1 { 8385 temperature = <110000>; 8386 hysteresis = <1000>; 8387 type = "hot"; 8388 }; 8389 8390 trip-point2 { 8391 temperature = <115000>; 8392 hysteresis = <0>; 8393 type = "critical"; 8394 }; 8395 }; 8396 }; 8397 8398 gpuss2-thermal { 8399 polling-delay-passive = <10>; 8400 8401 thermal-sensors = <&tsens2 3>; 8402 8403 gpu2_cooling_maps: cooling-maps { 8404 map0 { 8405 trip = <&gpu2_alert0>; 8406 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8407 }; 8408 }; 8409 8410 gpu2_trips: trips { 8411 gpu2_alert0: trip-point0 { 8412 temperature = <95000>; 8413 hysteresis = <1000>; 8414 type = "passive"; 8415 }; 8416 8417 trip-point1 { 8418 temperature = <110000>; 8419 hysteresis = <1000>; 8420 type = "hot"; 8421 }; 8422 8423 trip-point2 { 8424 temperature = <115000>; 8425 hysteresis = <0>; 8426 type = "critical"; 8427 }; 8428 }; 8429 }; 8430 8431 gpuss3-thermal { 8432 polling-delay-passive = <10>; 8433 8434 thermal-sensors = <&tsens2 4>; 8435 8436 gpu3_cooling_maps: cooling-maps { 8437 map0 { 8438 trip = <&gpu3_alert0>; 8439 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8440 }; 8441 }; 8442 8443 gpu3_trips: trips { 8444 gpu3_alert0: trip-point0 { 8445 temperature = <95000>; 8446 hysteresis = <1000>; 8447 type = "passive"; 8448 }; 8449 8450 trip-point1 { 8451 temperature = <110000>; 8452 hysteresis = <1000>; 8453 type = "hot"; 8454 }; 8455 8456 trip-point2 { 8457 temperature = <115000>; 8458 hysteresis = <0>; 8459 type = "critical"; 8460 }; 8461 }; 8462 }; 8463 8464 gpuss4-thermal { 8465 polling-delay-passive = <10>; 8466 8467 thermal-sensors = <&tsens2 5>; 8468 8469 gpu4_cooling_maps: cooling-maps { 8470 map0 { 8471 trip = <&gpu4_alert0>; 8472 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8473 }; 8474 }; 8475 8476 gpu4_trips: trips { 8477 gpu4_alert0: trip-point0 { 8478 temperature = <95000>; 8479 hysteresis = <1000>; 8480 type = "passive"; 8481 }; 8482 8483 trip-point1 { 8484 temperature = <110000>; 8485 hysteresis = <1000>; 8486 type = "hot"; 8487 }; 8488 8489 trip-point2 { 8490 temperature = <115000>; 8491 hysteresis = <0>; 8492 type = "critical"; 8493 }; 8494 }; 8495 }; 8496 8497 gpuss5-thermal { 8498 polling-delay-passive = <10>; 8499 8500 thermal-sensors = <&tsens2 6>; 8501 8502 gpu5_cooling_maps: cooling-maps { 8503 map0 { 8504 trip = <&gpu5_alert0>; 8505 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8506 }; 8507 }; 8508 8509 gpu5_trips: trips { 8510 gpu5_alert0: trip-point0 { 8511 temperature = <95000>; 8512 hysteresis = <1000>; 8513 type = "passive"; 8514 }; 8515 8516 trip-point1 { 8517 temperature = <110000>; 8518 hysteresis = <1000>; 8519 type = "hot"; 8520 }; 8521 8522 trip-point2 { 8523 temperature = <115000>; 8524 hysteresis = <0>; 8525 type = "critical"; 8526 }; 8527 }; 8528 }; 8529 8530 gpuss6-thermal { 8531 polling-delay-passive = <10>; 8532 8533 thermal-sensors = <&tsens2 7>; 8534 8535 gpu6_cooling_maps: cooling-maps { 8536 map0 { 8537 trip = <&gpu6_alert0>; 8538 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8539 }; 8540 }; 8541 8542 gpu6_trips: trips { 8543 gpu6_alert0: trip-point0 { 8544 temperature = <95000>; 8545 hysteresis = <1000>; 8546 type = "passive"; 8547 }; 8548 8549 trip-point1 { 8550 temperature = <110000>; 8551 hysteresis = <1000>; 8552 type = "hot"; 8553 }; 8554 8555 trip-point2 { 8556 temperature = <115000>; 8557 hysteresis = <0>; 8558 type = "critical"; 8559 }; 8560 }; 8561 }; 8562 8563 gpuss7-thermal { 8564 polling-delay-passive = <10>; 8565 8566 thermal-sensors = <&tsens2 8>; 8567 8568 gpu7_cooling_maps: cooling-maps { 8569 map0 { 8570 trip = <&gpu7_alert0>; 8571 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8572 }; 8573 }; 8574 8575 gpu7_trips: trips { 8576 gpu7_alert0: trip-point0 { 8577 temperature = <95000>; 8578 hysteresis = <1000>; 8579 type = "passive"; 8580 }; 8581 8582 trip-point1 { 8583 temperature = <110000>; 8584 hysteresis = <1000>; 8585 type = "hot"; 8586 }; 8587 8588 trip-point2 { 8589 temperature = <115000>; 8590 hysteresis = <0>; 8591 type = "critical"; 8592 }; 8593 }; 8594 }; 8595 8596 modem0-thermal { 8597 thermal-sensors = <&tsens2 9>; 8598 8599 trips { 8600 modem0-hot { 8601 temperature = <110000>; 8602 hysteresis = <1000>; 8603 type = "hot"; 8604 }; 8605 8606 modem0-critical { 8607 temperature = <115000>; 8608 hysteresis = <0>; 8609 type = "critical"; 8610 }; 8611 }; 8612 }; 8613 8614 modem1-thermal { 8615 thermal-sensors = <&tsens2 10>; 8616 8617 trips { 8618 modem1-hot { 8619 temperature = <110000>; 8620 hysteresis = <1000>; 8621 type = "hot"; 8622 }; 8623 8624 modem1-critical { 8625 temperature = <115000>; 8626 hysteresis = <0>; 8627 type = "critical"; 8628 }; 8629 }; 8630 }; 8631 8632 modem2-thermal { 8633 thermal-sensors = <&tsens2 11>; 8634 8635 trips { 8636 modem2-hot { 8637 temperature = <110000>; 8638 hysteresis = <1000>; 8639 type = "hot"; 8640 }; 8641 8642 modem2-critical { 8643 temperature = <115000>; 8644 hysteresis = <0>; 8645 type = "critical"; 8646 }; 8647 }; 8648 }; 8649 8650 modem3-thermal { 8651 thermal-sensors = <&tsens2 12>; 8652 8653 trips { 8654 modem3-hot { 8655 temperature = <110000>; 8656 hysteresis = <1000>; 8657 type = "hot"; 8658 }; 8659 8660 modem3-critical { 8661 temperature = <115000>; 8662 hysteresis = <0>; 8663 type = "critical"; 8664 }; 8665 }; 8666 }; 8667 }; 8668 8669 timer { 8670 compatible = "arm,armv8-timer"; 8671 8672 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 8673 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 8674 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 8675 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 8676 }; 8677}; 8678