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Searched +full:exynos5433 +full:- +full:i2s (Results 1 – 8 of 8) sorted by relevance

/linux/Documentation/devicetree/bindings/mfd/
H A Dsamsung,exynos5433-lpass.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/samsung,exynos5433-lpass.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 const: samsung,exynos5433-lpass
17 '#address-cells':
23 clock-names:
25 - const: sfr0_ctrl
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/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC device tree source
7 * Samsung's Exynos5433 SoC device nodes are listed in this file.
8 * Exynos5433 based board files can include this file and provide
12 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 compatible = "samsung,exynos5433";
21 #address-cells = <2>;
22 #size-cells = <2>;
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H A Dexynos5433-tm2-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5433 TM2 board device tree source
8 * which are based on Samsung Exynos5433 SoC.
11 /dts-v1/;
12 #include "exynos5433.dtsi"
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/sound/samsung-i2s.h>
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/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos5433-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5433 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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/linux/Documentation/devicetree/bindings/sound/
H A Dsamsung-i2s.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC I2S controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - $ref: dai-common.yaml#
19 samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
21 samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with
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H A Dsamsung,tm2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5433 TM2(E) audio complex with WM5110 codec
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - $ref: sound-card-common.yaml#
18 const: samsung,tm2-audio
20 audio-amplifier:
24 audio-codec:
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/linux/drivers/mfd/
H A Dexynos-lpass.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd.
11 * devices for IP blocks like DMAC, I2S, UART.
23 #include <linux/soc/samsung/exynos-regs-pmu.h>
61 regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val); in exynos_lpass_core_sw_reset()
64 regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); in exynos_lpass_core_sw_reset()
69 regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); in exynos_lpass_core_sw_reset()
74 clk_prepare_enable(lpass->sfr0_clk); in exynos_lpass_enable()
76 /* Unmask SFR, DMA and I2S interrupt */ in exynos_lpass_enable()
77 regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, in exynos_lpass_enable()
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/linux/drivers/clk/samsung/
H A Dclk-exynos5433.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Common Clock Framework support for Exynos5433 SoC.
10 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/exynos5433.h>
20 #include "clk-cpu.h"
21 #include "clk-exynos-arm64.h"
22 #include "clk-pll.h"
264 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
792 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
794 PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
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