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Searched +full:exynos5250 +full:- +full:wdt (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/watchdog/
H A Dsamsung-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/watchdog/samsung-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 after a preset amount of time during which the WDT reset event has not
20 - enum:
21 - google,gs101-wdt # for Google gs101
22 - samsung,s3c2410-wdt # for S3C2410
23 - samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
28 arm_a7_pmu: arm-a7-pmu {
29 compatible = "arm,cortex-a7-pmu";
30 interrupt-parent = <&gic>;
38 arm_a15_pmu: arm-a15-pmu {
39 compatible = "arm,cortex-a15-pmu";
40 interrupt-parent = <&combiner>;
49 compatible = "arm,armv7-timer";
54 clock-frequency = <24000000>;
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H A Dexynos5250.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5250 SoC device tree source
8 * Samsung Exynos5250 SoC device nodes are listed in this file.
9 * Exynos5250 based board files can include this file and provide
13 * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
17 #include <dt-bindings/clock/exynos5250.h>
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5250", "samsung,exynos5";
46 #address-cells = <1>;
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H A Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
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/linux/drivers/watchdog/
H A Ds3c2410_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
29 #include <linux/soc/samsung/exynos-pmu.h>
80 * DOC: Quirk flags for different Samsung watchdog IP-cores
85 * differences in both watchdog and PMU IP-cores should be accounted for. Quirk
92 * write-only, writing any values to this register clears the interrupt, but
96 * WDT reset request. On old SoCs it's usually called MASK_WDT_RESET_REQUEST,
106 * register. If 'mask_bit' bit is set, PMU will disable WDT reset when
149 * struct s3c2410_wdt_variant - Per-variant config data
161 * @cnt_en_reg: Offset in pmureg for the register that enables WDT counter.
181 struct clk *src_clk; /* for WDT counter */
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/linux/drivers/clk/samsung/
H A Dclk-exynos5250.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Common Clock Framework support for Exynos5250 SoC.
10 #include <dt-bindings/clock/exynos5250.h>
11 #include <linux/clk-provider.h>
17 #include "clk-cpu.h"
18 #include "clk-exynos5-subcmu.h"
629 GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
785 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
805 hws = ctx->clk_data.hws; in exynos5250_clk_init()
863 pr_info("Exynos5250: clock setup completed, armclk=%ld\n", in exynos5250_clk_init()
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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