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/linux/Documentation/devicetree/bindings/clock/
H A Dnvidia,tegra124-car.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Clock and Reset Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The Clock and Reset (CAR) is the HW module responsible for muxing and gating
18 the clock source programming and most of the clock dividers.
20 CLKGEN input signals include the external clock for the reference frequency
[all …]
H A Dsamsung,exynos-ext-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos-ext-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC external/osc/XXTI/XusbXTI clock
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Samsung SoCs require an external clock supplied through XXTI or XusbXTI pins.
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H A Dsamsung,s5pv210-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
[all …]
H A Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
16 connected with an external fixed rate oscillator, which signal is transformed
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
[all …]
H A Dpwm-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/pwm-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: An external clock signal driven by a PWM pin.
10 - Philipp Zabel <p.zabel@pengutronix.de>
14 const: pwm-clock
16 '#clock-cells':
19 clock-frequency:
20 description: Exact output frequency, in case the PWM period is not exact
[all …]
/linux/Documentation/devicetree/bindings/net/can/
H A Dcc770.txt8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
14 - interrupts : property with a value describing the interrupt source
19 - bosch,external-clock-frequency : frequency of the external oscillator
20 clock in Hz. Note that the internal clock frequency used by the
24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
31 - bosch,disconnect-rx0-input : see data sheet.
33 - bosch,disconnect-rx1-input : see data sheet.
35 - bosch,disconnect-tx1-output : see data sheet.
[all …]
H A Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - const: renesas,r9a06g032-sja1000 # RZ/N1D
20 - const: renesas,rzn1-sja1000 # RZ/N1
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
15 interface external sigma delta modulators to STM32 micro controllers.
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
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/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adrf6780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adi,adrf6780.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 radio designs operating in the 5.9 GHz to 23.6 GHz frequency range.
21 - adi,adrf6780
26 spi-max-frequency:
31 Definition of the external clock.
34 clock-names:
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/linux/Documentation/devicetree/bindings/spi/
H A Dnxp,sc18is.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - nxp,sc18is602
16 - nxp,sc18is602b
17 - nxp,sc18is603
22 clock-frequency:
26 external oscillator clock frequency. The clock-frequency property is
27 relevant and needed only if the chip has an external oscillator
[all …]
/linux/Documentation/devicetree/bindings/ptp/
H A Dfsl,ptp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
19 - items:
[all …]
/linux/Documentation/driver-api/
H A Dptp.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PTP hardware clock infrastructure for Linux
10 programs, synchronizing Linux with external clocks, and using the
13 A new class driver exports a kernel interface for specific clock
15 complete set of PTP hardware clock functionality.
17 + Basic clock operations
18 - Set time
19 - Get time
20 - Shift the clock by a given offset atomically
21 - Adjust clock frequency
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/linux/arch/xtensa/boot/dts/
H A Dxtfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 compatible = "cdns,xtensa-xtfpga";
4 #address-cells = <1>;
5 #size-cells = <1>;
6 interrupt-parent = <&pic>;
18 #address-cells = <1>;
19 #size-cells = <0>;
21 compatible = "cdns,xtensa-cpu";
28 compatible = "cdns,xtensa-pic";
31 * second cell == 1: external irq number
[all …]
/linux/Documentation/devicetree/bindings/mips/cavium/
H A Ductl.txt4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
17 frequency in Hz.
19 - refclk-type: A string describing the reference clock connection
20 either "crystal" or "external".
24 compatible = "cavium,octeon-6335-uctl";
[all …]
/linux/arch/powerpc/boot/dts/
H A Dtqm8xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <16>; // 16 bytes
32 i-cache-line-size = <16>; // 16 bytes
33 d-cache-size = <0x1000>; // L1, 4K
34 i-cache-size = <0x1000>; // L1, 4K
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-skov-cpu.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
10 stdout-path = &uart2;
19 mdio-gpio0 = &mdio;
28 iio-hwmon {
29 compatible = "iio-hwmon";
30 io-channels = <&adc 0>, /* 24V */
35 compatible = "gpio-leds";
37 led-0 {
[all …]
H A Dimx6q-skov-reve-mi1010ait-1cp1.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 /dts-v1/;
7 #include "imx6qdl-skov-cpu.dtsi"
11 compatible = "skov,imx6q-skov-reve-mi1010ait-1cp1", "fsl,imx6q";
14 compatible = "pwm-backlight";
15 pinctrl-names = "default";
16 pinctrl-0 = <&pinctrl_backlight>;
17 enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>;
19 brightness-levels = <0 255>;
20 num-interpolated-steps = <17>;
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra20-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 SoC External Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
17 various performance-affecting settings beyond the obvious SDRAM configuration
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpc5200.txt2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
[all …]
/linux/drivers/media/dvb-frontends/
H A Dlgs8gxx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Support for Legend Silicon GB20600 (a.k.a DMB-TH) demodulator
7 * Copyright (C) 2007-2009 David T.L. Wong <davidtlwong@gmail.com>
39 /* transport stream clock gated by ts_valid */
42 /* A/D Clock frequency */
45 /* IF frequency */
48 /*Use External ADC*/
51 /*External ADC output two's complement*/
57 /*IF use Negative center frequency*/
/linux/Documentation/devicetree/bindings/iio/filter/
H A Dadi,admv8818.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ADMV8818 Digitally Tunable, High-Pass and Low-Pass Filter
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 features a digitally selectable frequency of operation.
15 The device features four independently controlled high-pass
16 filters (HPFs) and four independently controlled low-pass filters
17 (LPFs) that span the 2 GHz to 18 GHz frequency range.
24 - adi,admv8818
[all …]
/linux/Documentation/devicetree/bindings/net/ieee802154/
H A Dca8210.txt4 - compatible: Should be "cascoda,ca8210"
5 - reg: Controlling chip select
6 - spi-max-frequency: Maximum clock speed, should be *less than*
8 - spi-cpol: Requires inverted clock polarity
9 - reset-gpio: GPIO attached to reset
10 - irq-gpio: GPIO attached to IRQ
12 - extclock-enable: Include for the ca8210 to route its 16MHz clock
14 - extclock-freq: Frequency in Hz of the external clock
15 - extclock-gpio: GPIO of the ca8210 to output the clock on
21 spi-max-frequency = <3000000>;
[all …]
/linux/Documentation/devicetree/bindings/rtc/
H A Dallwinner,sun6i-a31-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/allwinner,sun6i-a31-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#clock-cells":
19 - enum:
20 - allwinner,sun6i-a31-rtc
21 - allwinner,sun8i-a23-rtc
[all …]
/linux/sound/aoa/soundbus/i2sbus/
H A Dinterface.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * i2sbus driver -- interface register definitions
61 * - clock source
62 * - MClk divisor
63 * - SClk divisor
64 * - SClk master flag
65 * - serial format (sony, i2s 64x, i2s 32x, dav, silabs)
66 * - external sample frequency interrupt (don't understand)
67 * - external sample frequency
70 /* clock source. You get either 18.432, 45.1584 or 49.1520 MHz */
[all …]
/linux/Documentation/devicetree/bindings/net/wireless/
H A Dti,wlcore.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
14 Note that the *-clock-frequency properties assume internal clocks. In case
15 of external clocks, new bindings (for parsing the clock nodes) have to be
21 - ti,wl1271
22 - ti,wl1273
23 - ti,wl1281
24 - ti,wl1283
[all …]

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