| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
6 External clocks:
10 clk_sysbypck are inputs to the clock controller.
11 clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
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| H A D | nvidia,tegra124-car.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-ca
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| H A D | nvidia,tegra124-car.txt | 1 NVIDIA Tegra124 and Tegra132 Clock And Reset Controller
3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the
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| H A D | samsung,s5pv210-clock.txt | 1 * Samsung S5P6442/S5PC110/S5PV210 Clock Controller
3 Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
4 controller, which generates and supplies clock to various controllers
9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
23 External clocks:
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| H A D | samsung,exynos-ext-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos-ext-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC external/osc/XXTI/XusbXTI clock
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Samsung SoCs require an external clock supplied through XXTI or XusbXTI pins.
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| H A D | samsung,s5pv210-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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| H A D | st,stm32-rcc.txt | 1 STMicroelectronics STM32 Reset and Clock Controller
4 The RCC IP is both a reset and a clock controller.
6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
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| /freebsd/sys/contrib/device-tree/Bindings/iio/imu/ |
| H A D | adi,adis16480.txt | 6 - compatible: Must be one of
12 * "adi,adis16495-1"
13 * "adi,adis16495-2"
14 * "adi,adis16495-3"
15 * "adi,adis16497-1"
16 * "adi,adis16497-2"
17 * "adi,adis16497-3"
18 - reg: SPI chip select number for the device
19 - spi-max-frequency: Max SPI frequency to use
20 see: Documentation/devicetree/bindings/spi/spi-bus.txt
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| H A D | adi,adis16480.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
15 - adi,adis16375
16 - adi,adis16480
17 - adi,adis16485
18 - adi,adis16488
19 - adi,adis16490
20 - adi,adis16495-1
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| /freebsd/sys/contrib/device-tree/Bindings/media/i2c/ |
| H A D | toshiba,et8ek8.txt | 6 Documentation/devicetree/bindings/media/video-interfaces.txt .
10 --------------------
12 - compatible: "toshiba,et8ek8"
13 - reg: I2C address (0x3e, or an alternative address)
14 - vana-supply: Analogue voltage supply (VANA), 2.8 volts
15 - clocks: External clock to the sensor
16 - clock-frequency: Frequency of the external clock to the sensor. Camera
17 driver will set this frequency on the external clock. The clock frequency is
18 a pre-determined frequency known to be suitable to the board.
19 - reset-gpios: XSHUTDOWN GPIO. The XSHUTDOWN signal is active low. The sensor
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| H A D | nokia,smia.txt | 8 Documentation/devicetree/bindings/media/video-interfaces.txt .
12 Documentation/devicetree/bindings/media/video-interfaces.txt .
15 --------------------
17 - compatible: "nokia,smia"
18 - reg: I2C address (0x10, or an alternative address)
19 - vana-supply: Analogue voltage supply (VANA), typically 2,8 volts (sensor
21 - clocks: External clock to the sensor
22 - clock-frequency: Frequency of the external clock to the sensor
23 - link-frequencies: List of allowed data link frequencies. An array of
24 64-bit elements.
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| H A D | mipi-ccs.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2014--2020 Intel Corporation
4 ---
5 $id: http://devicetree.org/schemas/media/i2c/mipi-ccs.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sakari Ailus <sakari.ailus@linux.intel.com>
17 <URL:https://www.mipi.org/specifications/camera-command-set>.
24 Documentation/devicetree/bindings/media/video-interfaces.txt .
29 - items:
30 - const: mipi-ccs-1.1
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| /freebsd/sys/contrib/device-tree/Bindings/net/can/ |
| H A D | cc770.txt | 8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
14 - interrupts : property with a value describing the interrupt source
19 - bosch,external-clock-frequency : frequency o
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| H A D | sja1000.txt | 5 - compatible : should be one of "nxp,sja1000", "technologic,sja1000".
7 - reg : should specify the chip select, address offset and size required
10 - interrupts: property with a value describing the interrupt source
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
20 - nxp,external-clock-frequency : Frequency of the external oscillator
21 clock in Hz. Note that the internal clock frequency used by the
25 - nxp,tx-output-mode : operation mode of the TX output control logic:
26 <0x0> : bi-phase output mode
29 <0x3> : clock output mode
31 - nxp,tx-output-config : TX output pin configuration:
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| H A D | nxp,sja1000.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
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| /freebsd/contrib/ntp/html/ |
| H A D | extern.html | 1 <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
6 <title>External Clock Discipline and the Local Clock Driver</title>
10 <h3>External Clock Discipline and the Local Clock Driver</h3>
12 <!-- #BeginDate format:En2m -->9-May-2014 04:46<!-- #EndDate -->
15 <p>The NTPv4 implementation includes provisions for an external clock, where
16 the system clock is implemented by some external hardware device.
22 A third implementation might be a completely separate clock discipline algorithm
25 …external clocks are used in conjunction with NTP service, some way needs to be provided for the ex…
26 …external clock and driver are implemented using the <a href="drivers/driver1.html">Local Clock (ty…
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-sc18is602.txt | 4 - compatible : Should be one of
8 - reg: I2C bus address
11 - clock-frequency : external oscillator clock frequency. If not
12 specified, the SC18IS602 default frequency (7372000) will be used.
14 The clock-frequency property is relevant and needed only if the chip has an
15 external oscillator (SC18IS603).
22 clock-frequency = <14744000>;
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| H A D | nxp,sc18is.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - nxp,sc18is602
16 - nxp,sc18is602b
17 - nxp,sc18is603
22 clock-frequency:
26 external oscillator clock frequency. The clock-frequency property is
27 relevant and needed only if the chip has an external oscillator
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| /freebsd/sys/contrib/device-tree/src/riscv/starfive/ |
| H A D | jh7110-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include "jh7110-pinfunc.h"
10 #include <dt-bindings/gpio/gpio.h>
25 stdout-path = "serial0:115200n8";
33 gpio-restart {
34 compatible = "gpio-restart";
39 pwmdac_codec: audio-codec {
40 compatible = "linux,spdif-dit";
41 #sound-dai-cells = <0>;
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| /freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | st,stm32-dfsdm-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
15 interface external sigma delta modulators to STM32 micro controllers.
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
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| /freebsd/sys/contrib/device-tree/Bindings/ptp/ |
| H A D | ptp-qoriq.txt | 1 * Freescale QorIQ 1588 timer based PTP clock
5 - compatible Should be "fsl,etsec-ptp" for eTSEC
6 Should be "fsl,fman-ptp-timer" for DPAA FMan
7 Should be "fsl,dpaa2-ptp" for DPAA2
8 Should be "fsl,enetc-ptp" for ENETC
9 - reg Offset and length of the register set for the device
10 - interrupts There should be at least two interrupts. Some devices
13 Clock Properties:
15 - fsl,cksel Timer reference clock source.
16 - fsl,tclk-period Timer reference clock period in nanoseconds.
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| H A D | fsl,ptp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
19 - items:
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| /freebsd/sys/contrib/device-tree/Bindings/iio/frequency/ |
| H A D | adi,adrf6780.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adi,adrf6780.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 radio designs operating in the 5.9 GHz to 23.6 GHz frequency range.
21 - adi,adrf6780
26 spi-max-frequency:
31 Definition of the external clock.
34 clock-names:
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| /freebsd/sys/dts/arm/ |
| H A D | annapurna-alpine.dts | 1 /*-
28 /dts-v1/;
32 #address-cells = <1>;
33 #size-cells = <1>;
40 #address-cells = <1>;
41 #size-cells = <0>;
45 compatible = "arm,cortex-a15";
47 d-cache-line-size = <64>; // 64 bytes
48 i-cache-line-size = <64>; // 64 bytes
49 d-cache-size = <0x8000>; // L1, 32K
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| /freebsd/lib/libsys/ |
| H A D | ntp_adjtime.2 | 55 function is used by the NTP daemon to adjust the system clock to an
61 to adjust the phase and frequency of the phase- or frequency-lock loop
62 (PLL resp. FLL) which controls the system clock.
78 .Bd -literal
80 unsigned int modes; /* clock mode bits (wo) */
82 long freq; /* frequency offset (scaled ppm) (rw) */
85 int status; /* clock status bits (rw) */
87 long precision; /* clock precision (us) (ro) */
88 long tolerance; /* clock frequency tolerance (scaled
91 * The following read-only structure members are implemented
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