1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2020 Nuvoton Technology corporation.
3
4 #include <linux/bits.h>
5 #include <linux/device.h>
6 #include <linux/gpio/driver.h>
7 #include <linux/gpio/generic.h>
8 #include <linux/interrupt.h>
9 #include <linux/irq.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/module.h>
12 #include <linux/debugfs.h>
13 #include <linux/seq_file.h>
14 #include <linux/pinctrl/machine.h>
15 #include <linux/pinctrl/pinconf.h>
16 #include <linux/pinctrl/pinconf-generic.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/platform_device.h>
21 #include <linux/property.h>
22 #include <linux/regmap.h>
23
24 /* GCR registers */
25 #define NPCM8XX_GCR_SRCNT 0x068
26 #define NPCM8XX_GCR_FLOCKR1 0x074
27 #define NPCM8XX_GCR_DSCNT 0x078
28 #define NPCM8XX_GCR_INTCR4 0x0c0
29 #define NPCM8XX_GCR_I2CSEGSEL 0x0e0
30 #define NPCM8XX_GCR_MFSEL1 0x260
31 #define NPCM8XX_GCR_MFSEL2 0x264
32 #define NPCM8XX_GCR_MFSEL3 0x268
33 #define NPCM8XX_GCR_MFSEL4 0x26c
34 #define NPCM8XX_GCR_MFSEL5 0x270
35 #define NPCM8XX_GCR_MFSEL6 0x274
36 #define NPCM8XX_GCR_MFSEL7 0x278
37
38 #define SRCNT_ESPI BIT(3)
39
40 /* GPIO registers */
41 #define NPCM8XX_GP_N_TLOCK1 0x00
42 #define NPCM8XX_GP_N_DIN 0x04
43 #define NPCM8XX_GP_N_POL 0x08
44 #define NPCM8XX_GP_N_DOUT 0x0c
45 #define NPCM8XX_GP_N_OE 0x10
46 #define NPCM8XX_GP_N_OTYP 0x14
47 #define NPCM8XX_GP_N_MP 0x18
48 #define NPCM8XX_GP_N_PU 0x1c
49 #define NPCM8XX_GP_N_PD 0x20
50 #define NPCM8XX_GP_N_DBNC 0x24
51 #define NPCM8XX_GP_N_EVTYP 0x28
52 #define NPCM8XX_GP_N_EVBE 0x2c
53 #define NPCM8XX_GP_N_OBL0 0x30
54 #define NPCM8XX_GP_N_OBL1 0x34
55 #define NPCM8XX_GP_N_OBL2 0x38
56 #define NPCM8XX_GP_N_OBL3 0x3c
57 #define NPCM8XX_GP_N_EVEN 0x40
58 #define NPCM8XX_GP_N_EVENS 0x44
59 #define NPCM8XX_GP_N_EVENC 0x48
60 #define NPCM8XX_GP_N_EVST 0x4c
61 #define NPCM8XX_GP_N_SPLCK 0x50
62 #define NPCM8XX_GP_N_MPLCK 0x54
63 #define NPCM8XX_GP_N_IEM 0x58
64 #define NPCM8XX_GP_N_OSRC 0x5c
65 #define NPCM8XX_GP_N_ODSC 0x60
66 #define NPCM8XX_GP_N_DOS 0x68
67 #define NPCM8XX_GP_N_DOC 0x6c
68 #define NPCM8XX_GP_N_OES 0x70
69 #define NPCM8XX_GP_N_OEC 0x74
70 #define NPCM8XX_GP_N_DBNCS0 0x80
71 #define NPCM8XX_GP_N_DBNCS1 0x84
72 #define NPCM8XX_GP_N_DBNCP0 0x88
73 #define NPCM8XX_GP_N_DBNCP1 0x8c
74 #define NPCM8XX_GP_N_DBNCP2 0x90
75 #define NPCM8XX_GP_N_DBNCP3 0x94
76 #define NPCM8XX_GP_N_TLOCK2 0xac
77
78 #define NPCM8XX_GPIO_PER_BANK 32
79 #define NPCM8XX_GPIO_BANK_NUM 8
80 #define NPCM8XX_GCR_NONE 0
81 #define NPCM8XX_INTCR4_R1_RMII_EN BIT(12)
82 #define NPCM8XX_INTCR4_R2_RMII_EN BIT(13)
83 #define NPCM8XX_INTCR4_RMII3_EN BIT(14)
84 #define NPCM8XX_GCR_DSCNT_RG2DS_SHIFT 6
85 #define NPCM8XX_GCR_DSCNT_RG2DS_MASK GENMASK(7, 6)
86
87 #define NPCM8XX_DEBOUNCE_MAX 4
88 #define NPCM8XX_DEBOUNCE_NSEC 40
89 #define NPCM8XX_DEBOUNCE_VAL_MASK GENMASK(23, 4)
90 #define NPCM8XX_DEBOUNCE_MAX_VAL 0xFFFFF7
91
92 /* Structure for register banks */
93 struct debounce_time {
94 bool set_val[NPCM8XX_DEBOUNCE_MAX];
95 u32 nanosec_val[NPCM8XX_DEBOUNCE_MAX];
96 };
97
98 struct npcm8xx_gpio {
99 struct gpio_generic_chip chip;
100 void __iomem *base;
101 struct debounce_time debounce;
102 int irqbase;
103 int irq;
104 struct irq_chip irq_chip;
105 u32 pinctrl_id;
106 int (*direction_input)(struct gpio_chip *chip, unsigned int offset);
107 int (*direction_output)(struct gpio_chip *chip, unsigned int offset,
108 int value);
109 int (*request)(struct gpio_chip *chip, unsigned int offset);
110 void (*free)(struct gpio_chip *chip, unsigned int offset);
111 };
112
113 struct npcm8xx_pinctrl {
114 struct pinctrl_dev *pctldev;
115 struct device *dev;
116 struct npcm8xx_gpio gpio_bank[NPCM8XX_GPIO_BANK_NUM];
117 struct irq_domain *domain;
118 struct regmap *gcr_regmap;
119 void __iomem *regs;
120 u32 bank_num;
121 };
122
123 /* GPIO handling in the pinctrl driver */
npcm_gpio_set(struct gpio_generic_chip * chip,void __iomem * reg,unsigned int pinmask)124 static void npcm_gpio_set(struct gpio_generic_chip *chip, void __iomem *reg,
125 unsigned int pinmask)
126 {
127 guard(gpio_generic_lock_irqsave)(chip);
128
129 iowrite32(ioread32(reg) | pinmask, reg);
130 }
131
npcm_gpio_clr(struct gpio_generic_chip * chip,void __iomem * reg,unsigned int pinmask)132 static void npcm_gpio_clr(struct gpio_generic_chip *chip, void __iomem *reg,
133 unsigned int pinmask)
134 {
135 guard(gpio_generic_lock_irqsave)(chip);
136
137 iowrite32(ioread32(reg) & ~pinmask, reg);
138 }
139
npcmgpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)140 static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
141 {
142 struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
143
144 seq_printf(s, "DIN :%.8x DOUT:%.8x IE :%.8x OE :%.8x\n",
145 ioread32(bank->base + NPCM8XX_GP_N_DIN),
146 ioread32(bank->base + NPCM8XX_GP_N_DOUT),
147 ioread32(bank->base + NPCM8XX_GP_N_IEM),
148 ioread32(bank->base + NPCM8XX_GP_N_OE));
149 seq_printf(s, "PU :%.8x PD :%.8x DB :%.8x POL :%.8x\n",
150 ioread32(bank->base + NPCM8XX_GP_N_PU),
151 ioread32(bank->base + NPCM8XX_GP_N_PD),
152 ioread32(bank->base + NPCM8XX_GP_N_DBNC),
153 ioread32(bank->base + NPCM8XX_GP_N_POL));
154 seq_printf(s, "ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n",
155 ioread32(bank->base + NPCM8XX_GP_N_EVTYP),
156 ioread32(bank->base + NPCM8XX_GP_N_EVBE),
157 ioread32(bank->base + NPCM8XX_GP_N_EVEN),
158 ioread32(bank->base + NPCM8XX_GP_N_EVST));
159 seq_printf(s, "OTYP:%.8x OSRC:%.8x ODSC:%.8x\n",
160 ioread32(bank->base + NPCM8XX_GP_N_OTYP),
161 ioread32(bank->base + NPCM8XX_GP_N_OSRC),
162 ioread32(bank->base + NPCM8XX_GP_N_ODSC));
163 seq_printf(s, "OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n",
164 ioread32(bank->base + NPCM8XX_GP_N_OBL0),
165 ioread32(bank->base + NPCM8XX_GP_N_OBL1),
166 ioread32(bank->base + NPCM8XX_GP_N_OBL2),
167 ioread32(bank->base + NPCM8XX_GP_N_OBL3));
168 seq_printf(s, "SLCK:%.8x MLCK:%.8x\n",
169 ioread32(bank->base + NPCM8XX_GP_N_SPLCK),
170 ioread32(bank->base + NPCM8XX_GP_N_MPLCK));
171 }
172
npcmgpio_direction_input(struct gpio_chip * chip,unsigned int offset)173 static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)
174 {
175 struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
176 int ret;
177
178 ret = pinctrl_gpio_direction_input(chip, offset);
179 if (ret)
180 return ret;
181
182 return bank->direction_input(chip, offset);
183 }
184
npcmgpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)185 static int npcmgpio_direction_output(struct gpio_chip *chip,
186 unsigned int offset, int value)
187 {
188 struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
189 int ret;
190
191 ret = pinctrl_gpio_direction_output(chip, offset);
192 if (ret)
193 return ret;
194
195 return bank->direction_output(chip, offset, value);
196 }
197
npcmgpio_gpio_request(struct gpio_chip * chip,unsigned int offset)198 static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset)
199 {
200 struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
201 int ret;
202
203 ret = pinctrl_gpio_request(chip, offset);
204 if (ret)
205 return ret;
206
207 return bank->request(chip, offset);
208 }
209
npcmgpio_irq_handler(struct irq_desc * desc)210 static void npcmgpio_irq_handler(struct irq_desc *desc)
211 {
212 unsigned long sts, en, bit;
213 struct npcm8xx_gpio *bank;
214 struct irq_chip *chip;
215 struct gpio_chip *gc;
216
217 gc = irq_desc_get_handler_data(desc);
218 bank = gpiochip_get_data(gc);
219 chip = irq_desc_get_chip(desc);
220
221 chained_irq_enter(chip, desc);
222 sts = ioread32(bank->base + NPCM8XX_GP_N_EVST);
223 en = ioread32(bank->base + NPCM8XX_GP_N_EVEN);
224 sts &= en;
225 for_each_set_bit(bit, &sts, NPCM8XX_GPIO_PER_BANK)
226 generic_handle_domain_irq(gc->irq.domain, bit);
227 chained_irq_exit(chip, desc);
228 }
229
npcmgpio_set_irq_type(struct irq_data * d,unsigned int type)230 static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)
231 {
232 struct npcm8xx_gpio *bank =
233 gpiochip_get_data(irq_data_get_irq_chip_data(d));
234 unsigned int gpio = BIT(irqd_to_hwirq(d));
235
236 switch (type) {
237 case IRQ_TYPE_EDGE_RISING:
238 npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio);
239 npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);
240 break;
241 case IRQ_TYPE_EDGE_FALLING:
242 npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio);
243 npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);
244 break;
245 case IRQ_TYPE_EDGE_BOTH:
246 npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);
247 npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio);
248 break;
249 case IRQ_TYPE_LEVEL_LOW:
250 npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);
251 break;
252 case IRQ_TYPE_LEVEL_HIGH:
253 npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);
254 break;
255 default:
256 return -EINVAL;
257 }
258
259 if (type & IRQ_TYPE_LEVEL_MASK) {
260 npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVTYP, gpio);
261 irq_set_handler_locked(d, handle_level_irq);
262 } else if (type & IRQ_TYPE_EDGE_BOTH) {
263 npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_EVTYP, gpio);
264 irq_set_handler_locked(d, handle_edge_irq);
265 }
266
267 return 0;
268 }
269
npcmgpio_irq_ack(struct irq_data * d)270 static void npcmgpio_irq_ack(struct irq_data *d)
271 {
272 struct npcm8xx_gpio *bank =
273 gpiochip_get_data(irq_data_get_irq_chip_data(d));
274 unsigned int gpio = irqd_to_hwirq(d);
275
276 iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVST);
277 }
278
npcmgpio_irq_mask(struct irq_data * d)279 static void npcmgpio_irq_mask(struct irq_data *d)
280 {
281 struct npcm8xx_gpio *bank =
282 gpiochip_get_data(irq_data_get_irq_chip_data(d));
283 unsigned int gpio = irqd_to_hwirq(d);
284
285 iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENC);
286 }
287
npcmgpio_irq_unmask(struct irq_data * d)288 static void npcmgpio_irq_unmask(struct irq_data *d)
289 {
290 struct npcm8xx_gpio *bank =
291 gpiochip_get_data(irq_data_get_irq_chip_data(d));
292 unsigned int gpio = irqd_to_hwirq(d);
293
294 iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENS);
295 }
296
npcmgpio_irq_startup(struct irq_data * d)297 static unsigned int npcmgpio_irq_startup(struct irq_data *d)
298 {
299 npcmgpio_irq_ack(d);
300 npcmgpio_irq_unmask(d);
301
302 return 0;
303 }
304
npcmgpio_irq_request_resources(struct irq_data * d)305 static int npcmgpio_irq_request_resources(struct irq_data *d)
306 {
307 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
308 unsigned int gpio = irqd_to_hwirq(d);
309 int ret;
310
311 ret = npcmgpio_direction_input(gc, gpio);
312 if (ret)
313 return ret;
314
315 return gpiochip_reqres_irq(gc, gpio);
316 }
317
npcmgpio_irq_release_resources(struct irq_data * d)318 static void npcmgpio_irq_release_resources(struct irq_data *d)
319 {
320 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
321 unsigned int gpio = irqd_to_hwirq(d);
322
323 gpiochip_relres_irq(gc, gpio);
324 }
325
326 static struct irq_chip npcmgpio_irqchip = {
327 .name = "NPCM8XX-GPIO-IRQ",
328 .irq_ack = npcmgpio_irq_ack,
329 .irq_unmask = npcmgpio_irq_unmask,
330 .irq_mask = npcmgpio_irq_mask,
331 .irq_set_type = npcmgpio_set_irq_type,
332 .irq_startup = npcmgpio_irq_startup,
333 .irq_request_resources = npcmgpio_irq_request_resources,
334 .irq_release_resources = npcmgpio_irq_release_resources,
335 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
336 };
337
338 static const int gpi36_pins[] = { 36 };
339 static const int gpi35_pins[] = { 35 };
340
341 static const int tp_jtag3_pins[] = { 44, 62, 45, 46 };
342 static const int tp_uart_pins[] = { 50, 51 };
343
344 static const int tp_smb2_pins[] = { 24, 25 };
345 static const int tp_smb1_pins[] = { 142, 143 };
346
347 static const int tp_gpio7_pins[] = { 96 };
348 static const int tp_gpio6_pins[] = { 97 };
349 static const int tp_gpio5_pins[] = { 98 };
350 static const int tp_gpio4_pins[] = { 99 };
351 static const int tp_gpio3_pins[] = { 100 };
352 static const int tp_gpio2_pins[] = { 16 };
353 static const int tp_gpio1_pins[] = { 9 };
354 static const int tp_gpio0_pins[] = { 8 };
355
356 static const int tp_gpio2b_pins[] = { 101 };
357 static const int tp_gpio1b_pins[] = { 92 };
358 static const int tp_gpio0b_pins[] = { 91 };
359
360 static const int vgadig_pins[] = { 102, 103, 104, 105 };
361
362 static const int nbu1crts_pins[] = { 44, 62 };
363
364 static const int fm2_pins[] = { 224, 225, 226, 227, 228, 229, 230 };
365 static const int fm1_pins[] = { 175, 176, 177, 203, 191, 192, 233 };
366 static const int fm0_pins[] = { 194, 195, 196, 202, 199, 198, 197 };
367
368 static const int gpio1836_pins[] = { 183, 184, 185, 186 };
369 static const int gpio1889_pins[] = { 188, 189 };
370 static const int gpo187_pins[] = { 187 };
371
372 static const int cp1urxd_pins[] = { 41 };
373 static const int r3rxer_pins[] = { 212 };
374
375 static const int cp1gpio2c_pins[] = { 101 };
376 static const int cp1gpio3c_pins[] = { 100 };
377
378 static const int cp1gpio0b_pins[] = { 127 };
379 static const int cp1gpio1b_pins[] = { 126 };
380 static const int cp1gpio2b_pins[] = { 125 };
381 static const int cp1gpio3b_pins[] = { 124 };
382 static const int cp1gpio4b_pins[] = { 99 };
383 static const int cp1gpio5b_pins[] = { 98 };
384 static const int cp1gpio6b_pins[] = { 97 };
385 static const int cp1gpio7b_pins[] = { 96 };
386
387 static const int cp1gpio0_pins[] = { };
388 static const int cp1gpio1_pins[] = { };
389 static const int cp1gpio2_pins[] = { };
390 static const int cp1gpio3_pins[] = { };
391 static const int cp1gpio4_pins[] = { };
392 static const int cp1gpio5_pins[] = { 17 };
393 static const int cp1gpio6_pins[] = { 91 };
394 static const int cp1gpio7_pins[] = { 92 };
395
396 static const int cp1utxd_pins[] = { 42 };
397
398 static const int spi1cs3_pins[] = { 192 };
399 static const int spi1cs2_pins[] = { 191 };
400 static const int spi1cs1_pins[] = { 233 };
401 static const int spi1cs0_pins[] = { 203 };
402
403 static const int spi1d23_pins[] = { 191, 192 };
404
405 static const int j2j3_pins[] = { 44, 62, 45, 46 };
406
407 static const int r3oen_pins[] = { 213 };
408 static const int r2oen_pins[] = { 90 };
409 static const int r1oen_pins[] = { 56 };
410 static const int bu4b_pins[] = { 98, 99 };
411 static const int bu4_pins[] = { 54, 55 };
412 static const int bu5b_pins[] = { 100, 101 };
413 static const int bu5_pins[] = { 52, 53 };
414 static const int bu6_pins[] = { 50, 51 };
415 static const int rmii3_pins[] = { 110, 111, 209, 211, 210, 214, 215 };
416
417 static const int jm1_pins[] = { 136, 137, 138, 139, 140 };
418 static const int jm2_pins[] = { 251 };
419
420 static const int tpgpio5b_pins[] = { 58 };
421 static const int tpgpio4b_pins[] = { 57 };
422
423 static const int clkrun_pins[] = { 162 };
424
425 static const int i3c5_pins[] = { 106, 107 };
426 static const int i3c4_pins[] = { 33, 34 };
427 static const int i3c3_pins[] = { 246, 247 };
428 static const int i3c2_pins[] = { 244, 245 };
429 static const int i3c1_pins[] = { 242, 243 };
430 static const int i3c0_pins[] = { 240, 241 };
431
432 static const int hsi1a_pins[] = { 43, 63 };
433 static const int hsi2a_pins[] = { 48, 49 };
434 static const int hsi1b_pins[] = { 44, 62 };
435 static const int hsi2b_pins[] = { 50, 51 };
436 static const int hsi1c_pins[] = { 45, 46, 47, 61 };
437 static const int hsi2c_pins[] = { 45, 46, 47, 61 };
438
439 static const int smb0_pins[] = { 115, 114 };
440 static const int smb0b_pins[] = { 195, 194 };
441 static const int smb0c_pins[] = { 202, 196 };
442 static const int smb0d_pins[] = { 198, 199 };
443 static const int smb0den_pins[] = { 197 };
444 static const int smb1_pins[] = { 117, 116 };
445 static const int smb1b_pins[] = { 126, 127 };
446 static const int smb1c_pins[] = { 124, 125 };
447 static const int smb1d_pins[] = { 4, 5 };
448 static const int smb2_pins[] = { 119, 118 };
449 static const int smb2b_pins[] = { 122, 123 };
450 static const int smb2c_pins[] = { 120, 121 };
451 static const int smb2d_pins[] = { 6, 7 };
452 static const int smb3_pins[] = { 30, 31 };
453 static const int smb3b_pins[] = { 39, 40 };
454 static const int smb3c_pins[] = { 37, 38 };
455 static const int smb3d_pins[] = { 59, 60 };
456 static const int smb4_pins[] = { 28, 29 };
457 static const int smb4b_pins[] = { 18, 19 };
458 static const int smb4c_pins[] = { 20, 21 };
459 static const int smb4d_pins[] = { 22, 23 };
460 static const int smb5_pins[] = { 26, 27 };
461 static const int smb5b_pins[] = { 13, 12 };
462 static const int smb5c_pins[] = { 15, 14 };
463 static const int smb5d_pins[] = { 94, 93 };
464 static const int ga20kbc_pins[] = { 94, 93 };
465
466 static const int smb6_pins[] = { 172, 171 };
467 static const int smb6b_pins[] = { 2, 3 };
468 static const int smb6c_pins[] = { 0, 1 };
469 static const int smb6d_pins[] = { 10, 11 };
470 static const int smb7_pins[] = { 174, 173 };
471 static const int smb7b_pins[] = { 16, 141 };
472 static const int smb7c_pins[] = { 24, 25 };
473 static const int smb7d_pins[] = { 142, 143 };
474 static const int smb8_pins[] = { 129, 128 };
475 static const int smb9_pins[] = { 131, 130 };
476 static const int smb10_pins[] = { 133, 132 };
477 static const int smb11_pins[] = { 135, 134 };
478 static const int smb12_pins[] = { 221, 220 };
479 static const int smb13_pins[] = { 223, 222 };
480 static const int smb14_pins[] = { 22, 23 };
481 static const int smb14b_pins[] = { 32, 187 };
482 static const int smb15_pins[] = { 20, 21 };
483 static const int smb15b_pins[] = { 192, 191 };
484
485 static const int smb16_pins[] = { 10, 11 };
486 static const int smb16b_pins[] = { 218, 219 };
487 static const int smb17_pins[] = { 3, 2 };
488 static const int smb18_pins[] = { 0, 1 };
489 static const int smb19_pins[] = { 60, 59 };
490 static const int smb20_pins[] = { 234, 235 };
491 static const int smb21_pins[] = { 169, 170 };
492 static const int smb22_pins[] = { 40, 39 };
493 static const int smb23_pins[] = { 38, 37 };
494 static const int smb23b_pins[] = { 134, 135 };
495
496 static const int fanin0_pins[] = { 64 };
497 static const int fanin1_pins[] = { 65 };
498 static const int fanin2_pins[] = { 66 };
499 static const int fanin3_pins[] = { 67 };
500 static const int fanin4_pins[] = { 68 };
501 static const int fanin5_pins[] = { 69 };
502 static const int fanin6_pins[] = { 70 };
503 static const int fanin7_pins[] = { 71 };
504 static const int fanin8_pins[] = { 72 };
505 static const int fanin9_pins[] = { 73 };
506 static const int fanin10_pins[] = { 74 };
507 static const int fanin11_pins[] = { 75 };
508 static const int fanin12_pins[] = { 76 };
509 static const int fanin13_pins[] = { 77 };
510 static const int fanin14_pins[] = { 78 };
511 static const int fanin15_pins[] = { 79 };
512 static const int faninx_pins[] = { 175, 176, 177, 203 };
513
514 static const int pwm0_pins[] = { 80 };
515 static const int pwm1_pins[] = { 81 };
516 static const int pwm2_pins[] = { 82 };
517 static const int pwm3_pins[] = { 83 };
518 static const int pwm4_pins[] = { 144 };
519 static const int pwm5_pins[] = { 145 };
520 static const int pwm6_pins[] = { 146 };
521 static const int pwm7_pins[] = { 147 };
522 static const int pwm8_pins[] = { 220 };
523 static const int pwm9_pins[] = { 221 };
524 static const int pwm10_pins[] = { 234 };
525 static const int pwm11_pins[] = { 235 };
526
527 static const int uart1_pins[] = { 43, 45, 46, 47, 61, 62, 63 };
528 static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
529
530 static const int sg1mdio_pins[] = { 108, 109 };
531
532 static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
533 213, 214, 215 };
534 static const int rg2mdio_pins[] = { 216, 217 };
535
536 static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
537 213, 214, 215, 216, 217, 250 };
538
539 static const int iox1_pins[] = { 0, 1, 2, 3 };
540 static const int iox2_pins[] = { 4, 5, 6, 7 };
541 static const int ioxh_pins[] = { 10, 11, 24, 25 };
542
543 static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 };
544 static const int mmcwp_pins[] = { 153 };
545 static const int mmccd_pins[] = { 155 };
546 static const int mmcrst_pins[] = { 155 };
547 static const int mmc8_pins[] = { 148, 149, 150, 151 };
548
549 static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 };
550 static const int r1err_pins[] = { 56 };
551 static const int r1md_pins[] = { 57, 58 };
552 static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 };
553 static const int r2err_pins[] = { 90 };
554 static const int r2md_pins[] = { 91, 92 };
555 static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 };
556 static const int sd1pwr_pins[] = { 143 };
557
558 static const int wdog1_pins[] = { 218 };
559 static const int wdog2_pins[] = { 219 };
560
561 static const int bmcuart0a_pins[] = { 41, 42 };
562 static const int bmcuart0b_pins[] = { 48, 49 };
563 static const int bmcuart1_pins[] = { 43, 63 };
564
565 static const int scipme_pins[] = { 169 };
566 static const int smi_pins[] = { 170 };
567 static const int serirq_pins[] = { 168 };
568
569 static const int clkout_pins[] = { 160 };
570 static const int clkreq_pins[] = { 231 };
571
572 static const int jtag2_pins[] = { 43, 44, 45, 46, 47 };
573 static const int gspi_pins[] = { 12, 13, 14, 15 };
574
575 static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 };
576 static const int spixcs1_pins[] = { 228 };
577
578 static const int spi1_pins[] = { 175, 176, 177 };
579 static const int pspi_pins[] = { 17, 18, 19 };
580
581 static const int spi0cs1_pins[] = { 32 };
582
583 static const int spi3_pins[] = { 183, 184, 185, 186 };
584 static const int spi3cs1_pins[] = { 187 };
585 static const int spi3quad_pins[] = { 188, 189 };
586 static const int spi3cs2_pins[] = { 188 };
587 static const int spi3cs3_pins[] = { 189 };
588
589 static const int ddc_pins[] = { 204, 205, 206, 207 };
590
591 static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
592 static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
593
594 static const int lkgpo0_pins[] = { 16 };
595 static const int lkgpo1_pins[] = { 8 };
596 static const int lkgpo2_pins[] = { 9 };
597
598 static const int nprd_smi_pins[] = { 190 };
599
600 static const int hgpio0_pins[] = { 20 };
601 static const int hgpio1_pins[] = { 21 };
602 static const int hgpio2_pins[] = { 22 };
603 static const int hgpio3_pins[] = { 23 };
604 static const int hgpio4_pins[] = { 24 };
605 static const int hgpio5_pins[] = { 25 };
606 static const int hgpio6_pins[] = { 59 };
607 static const int hgpio7_pins[] = { 60 };
608
609 #define NPCM8XX_GRPS \
610 NPCM8XX_GRP(gpi36), \
611 NPCM8XX_GRP(gpi35), \
612 NPCM8XX_GRP(tp_jtag3), \
613 NPCM8XX_GRP(tp_uart), \
614 NPCM8XX_GRP(tp_smb2), \
615 NPCM8XX_GRP(tp_smb1), \
616 NPCM8XX_GRP(tp_gpio7), \
617 NPCM8XX_GRP(tp_gpio6), \
618 NPCM8XX_GRP(tp_gpio5), \
619 NPCM8XX_GRP(tp_gpio4), \
620 NPCM8XX_GRP(tp_gpio3), \
621 NPCM8XX_GRP(tp_gpio2), \
622 NPCM8XX_GRP(tp_gpio1), \
623 NPCM8XX_GRP(tp_gpio0), \
624 NPCM8XX_GRP(tp_gpio2b), \
625 NPCM8XX_GRP(tp_gpio1b), \
626 NPCM8XX_GRP(tp_gpio0b), \
627 NPCM8XX_GRP(vgadig), \
628 NPCM8XX_GRP(nbu1crts), \
629 NPCM8XX_GRP(fm2), \
630 NPCM8XX_GRP(fm1), \
631 NPCM8XX_GRP(fm0), \
632 NPCM8XX_GRP(gpio1836), \
633 NPCM8XX_GRP(gpio1889), \
634 NPCM8XX_GRP(gpo187), \
635 NPCM8XX_GRP(cp1urxd), \
636 NPCM8XX_GRP(r3rxer), \
637 NPCM8XX_GRP(cp1gpio2c), \
638 NPCM8XX_GRP(cp1gpio3c), \
639 NPCM8XX_GRP(cp1gpio0b), \
640 NPCM8XX_GRP(cp1gpio1b), \
641 NPCM8XX_GRP(cp1gpio2b), \
642 NPCM8XX_GRP(cp1gpio3b), \
643 NPCM8XX_GRP(cp1gpio4b), \
644 NPCM8XX_GRP(cp1gpio5b), \
645 NPCM8XX_GRP(cp1gpio6b), \
646 NPCM8XX_GRP(cp1gpio7b), \
647 NPCM8XX_GRP(cp1gpio0), \
648 NPCM8XX_GRP(cp1gpio1), \
649 NPCM8XX_GRP(cp1gpio2), \
650 NPCM8XX_GRP(cp1gpio3), \
651 NPCM8XX_GRP(cp1gpio4), \
652 NPCM8XX_GRP(cp1gpio5), \
653 NPCM8XX_GRP(cp1gpio6), \
654 NPCM8XX_GRP(cp1gpio7), \
655 NPCM8XX_GRP(cp1utxd), \
656 NPCM8XX_GRP(spi1cs3), \
657 NPCM8XX_GRP(spi1cs2), \
658 NPCM8XX_GRP(spi1cs1), \
659 NPCM8XX_GRP(spi1cs0), \
660 NPCM8XX_GRP(spi1d23), \
661 NPCM8XX_GRP(j2j3), \
662 NPCM8XX_GRP(r3oen), \
663 NPCM8XX_GRP(r2oen), \
664 NPCM8XX_GRP(r1oen), \
665 NPCM8XX_GRP(bu4b), \
666 NPCM8XX_GRP(bu4), \
667 NPCM8XX_GRP(bu5b), \
668 NPCM8XX_GRP(bu5), \
669 NPCM8XX_GRP(bu6), \
670 NPCM8XX_GRP(rmii3), \
671 NPCM8XX_GRP(jm1), \
672 NPCM8XX_GRP(jm2), \
673 NPCM8XX_GRP(tpgpio5b), \
674 NPCM8XX_GRP(tpgpio4b), \
675 NPCM8XX_GRP(clkrun), \
676 NPCM8XX_GRP(i3c5), \
677 NPCM8XX_GRP(i3c4), \
678 NPCM8XX_GRP(i3c3), \
679 NPCM8XX_GRP(i3c2), \
680 NPCM8XX_GRP(i3c1), \
681 NPCM8XX_GRP(i3c0), \
682 NPCM8XX_GRP(hsi1a), \
683 NPCM8XX_GRP(hsi2a), \
684 NPCM8XX_GRP(hsi1b), \
685 NPCM8XX_GRP(hsi2b), \
686 NPCM8XX_GRP(hsi1c), \
687 NPCM8XX_GRP(hsi2c), \
688 NPCM8XX_GRP(smb0), \
689 NPCM8XX_GRP(smb0b), \
690 NPCM8XX_GRP(smb0c), \
691 NPCM8XX_GRP(smb0d), \
692 NPCM8XX_GRP(smb0den), \
693 NPCM8XX_GRP(smb1), \
694 NPCM8XX_GRP(smb1b), \
695 NPCM8XX_GRP(smb1c), \
696 NPCM8XX_GRP(smb1d), \
697 NPCM8XX_GRP(smb2), \
698 NPCM8XX_GRP(smb2b), \
699 NPCM8XX_GRP(smb2c), \
700 NPCM8XX_GRP(smb2d), \
701 NPCM8XX_GRP(smb3), \
702 NPCM8XX_GRP(smb3b), \
703 NPCM8XX_GRP(smb3c), \
704 NPCM8XX_GRP(smb3d), \
705 NPCM8XX_GRP(smb4), \
706 NPCM8XX_GRP(smb4b), \
707 NPCM8XX_GRP(smb4c), \
708 NPCM8XX_GRP(smb4d), \
709 NPCM8XX_GRP(smb5), \
710 NPCM8XX_GRP(smb5b), \
711 NPCM8XX_GRP(smb5c), \
712 NPCM8XX_GRP(smb5d), \
713 NPCM8XX_GRP(ga20kbc), \
714 NPCM8XX_GRP(smb6), \
715 NPCM8XX_GRP(smb6b), \
716 NPCM8XX_GRP(smb6c), \
717 NPCM8XX_GRP(smb6d), \
718 NPCM8XX_GRP(smb7), \
719 NPCM8XX_GRP(smb7b), \
720 NPCM8XX_GRP(smb7c), \
721 NPCM8XX_GRP(smb7d), \
722 NPCM8XX_GRP(smb8), \
723 NPCM8XX_GRP(smb9), \
724 NPCM8XX_GRP(smb10), \
725 NPCM8XX_GRP(smb11), \
726 NPCM8XX_GRP(smb12), \
727 NPCM8XX_GRP(smb13), \
728 NPCM8XX_GRP(smb14), \
729 NPCM8XX_GRP(smb14b), \
730 NPCM8XX_GRP(smb15), \
731 NPCM8XX_GRP(smb15b), \
732 NPCM8XX_GRP(smb16), \
733 NPCM8XX_GRP(smb16b), \
734 NPCM8XX_GRP(smb17), \
735 NPCM8XX_GRP(smb18), \
736 NPCM8XX_GRP(smb19), \
737 NPCM8XX_GRP(smb20), \
738 NPCM8XX_GRP(smb21), \
739 NPCM8XX_GRP(smb22), \
740 NPCM8XX_GRP(smb23), \
741 NPCM8XX_GRP(smb23b), \
742 NPCM8XX_GRP(fanin0), \
743 NPCM8XX_GRP(fanin1), \
744 NPCM8XX_GRP(fanin2), \
745 NPCM8XX_GRP(fanin3), \
746 NPCM8XX_GRP(fanin4), \
747 NPCM8XX_GRP(fanin5), \
748 NPCM8XX_GRP(fanin6), \
749 NPCM8XX_GRP(fanin7), \
750 NPCM8XX_GRP(fanin8), \
751 NPCM8XX_GRP(fanin9), \
752 NPCM8XX_GRP(fanin10), \
753 NPCM8XX_GRP(fanin11), \
754 NPCM8XX_GRP(fanin12), \
755 NPCM8XX_GRP(fanin13), \
756 NPCM8XX_GRP(fanin14), \
757 NPCM8XX_GRP(fanin15), \
758 NPCM8XX_GRP(faninx), \
759 NPCM8XX_GRP(pwm0), \
760 NPCM8XX_GRP(pwm1), \
761 NPCM8XX_GRP(pwm2), \
762 NPCM8XX_GRP(pwm3), \
763 NPCM8XX_GRP(pwm4), \
764 NPCM8XX_GRP(pwm5), \
765 NPCM8XX_GRP(pwm6), \
766 NPCM8XX_GRP(pwm7), \
767 NPCM8XX_GRP(pwm8), \
768 NPCM8XX_GRP(pwm9), \
769 NPCM8XX_GRP(pwm10), \
770 NPCM8XX_GRP(pwm11), \
771 NPCM8XX_GRP(sg1mdio), \
772 NPCM8XX_GRP(rg2), \
773 NPCM8XX_GRP(rg2mdio), \
774 NPCM8XX_GRP(ddr), \
775 NPCM8XX_GRP(uart1), \
776 NPCM8XX_GRP(uart2), \
777 NPCM8XX_GRP(bmcuart0a), \
778 NPCM8XX_GRP(bmcuart0b), \
779 NPCM8XX_GRP(bmcuart1), \
780 NPCM8XX_GRP(iox1), \
781 NPCM8XX_GRP(iox2), \
782 NPCM8XX_GRP(ioxh), \
783 NPCM8XX_GRP(gspi), \
784 NPCM8XX_GRP(mmc), \
785 NPCM8XX_GRP(mmcwp), \
786 NPCM8XX_GRP(mmccd), \
787 NPCM8XX_GRP(mmcrst), \
788 NPCM8XX_GRP(mmc8), \
789 NPCM8XX_GRP(r1), \
790 NPCM8XX_GRP(r1err), \
791 NPCM8XX_GRP(r1md), \
792 NPCM8XX_GRP(r2), \
793 NPCM8XX_GRP(r2err), \
794 NPCM8XX_GRP(r2md), \
795 NPCM8XX_GRP(sd1), \
796 NPCM8XX_GRP(sd1pwr), \
797 NPCM8XX_GRP(wdog1), \
798 NPCM8XX_GRP(wdog2), \
799 NPCM8XX_GRP(scipme), \
800 NPCM8XX_GRP(smi), \
801 NPCM8XX_GRP(serirq), \
802 NPCM8XX_GRP(jtag2), \
803 NPCM8XX_GRP(spix), \
804 NPCM8XX_GRP(spixcs1), \
805 NPCM8XX_GRP(spi1), \
806 NPCM8XX_GRP(pspi), \
807 NPCM8XX_GRP(ddc), \
808 NPCM8XX_GRP(clkreq), \
809 NPCM8XX_GRP(clkout), \
810 NPCM8XX_GRP(spi3), \
811 NPCM8XX_GRP(spi3cs1), \
812 NPCM8XX_GRP(spi3quad), \
813 NPCM8XX_GRP(spi3cs2), \
814 NPCM8XX_GRP(spi3cs3), \
815 NPCM8XX_GRP(spi0cs1), \
816 NPCM8XX_GRP(lpc), \
817 NPCM8XX_GRP(espi), \
818 NPCM8XX_GRP(lkgpo0), \
819 NPCM8XX_GRP(lkgpo1), \
820 NPCM8XX_GRP(lkgpo2), \
821 NPCM8XX_GRP(nprd_smi), \
822 NPCM8XX_GRP(hgpio0), \
823 NPCM8XX_GRP(hgpio1), \
824 NPCM8XX_GRP(hgpio2), \
825 NPCM8XX_GRP(hgpio3), \
826 NPCM8XX_GRP(hgpio4), \
827 NPCM8XX_GRP(hgpio5), \
828 NPCM8XX_GRP(hgpio6), \
829 NPCM8XX_GRP(hgpio7), \
830 \
831
832 enum {
833 #define NPCM8XX_GRP(x) fn_ ## x
834 NPCM8XX_GRPS
835 NPCM8XX_GRP(none),
836 NPCM8XX_GRP(gpio),
837 #undef NPCM8XX_GRP
838 };
839
840 static struct pingroup npcm8xx_pingroups[] = {
841 #define NPCM8XX_GRP(x) PINCTRL_PINGROUP(#x, x ## _pins, ARRAY_SIZE(x ## _pins))
842 NPCM8XX_GRPS
843 #undef NPCM8XX_GRP
844 };
845
846 #define NPCM8XX_SFUNC(a) NPCM8XX_FUNC(a, #a)
847 #define NPCM8XX_FUNC(a, b...) static const char *a ## _grp[] = { b }
848
849 NPCM8XX_SFUNC(gpi36);
850 NPCM8XX_SFUNC(gpi35);
851 NPCM8XX_SFUNC(tp_jtag3);
852 NPCM8XX_SFUNC(tp_uart);
853 NPCM8XX_SFUNC(tp_smb2);
854 NPCM8XX_SFUNC(tp_smb1);
855 NPCM8XX_SFUNC(tp_gpio7);
856 NPCM8XX_SFUNC(tp_gpio6);
857 NPCM8XX_SFUNC(tp_gpio5);
858 NPCM8XX_SFUNC(tp_gpio4);
859 NPCM8XX_SFUNC(tp_gpio3);
860 NPCM8XX_SFUNC(tp_gpio2);
861 NPCM8XX_SFUNC(tp_gpio1);
862 NPCM8XX_SFUNC(tp_gpio0);
863 NPCM8XX_SFUNC(tp_gpio2b);
864 NPCM8XX_SFUNC(tp_gpio1b);
865 NPCM8XX_SFUNC(tp_gpio0b);
866 NPCM8XX_SFUNC(vgadig);
867 NPCM8XX_SFUNC(nbu1crts);
868 NPCM8XX_SFUNC(fm2);
869 NPCM8XX_SFUNC(fm1);
870 NPCM8XX_SFUNC(fm0);
871 NPCM8XX_SFUNC(gpio1836);
872 NPCM8XX_SFUNC(gpio1889);
873 NPCM8XX_SFUNC(gpo187);
874 NPCM8XX_SFUNC(cp1urxd);
875 NPCM8XX_SFUNC(r3rxer);
876 NPCM8XX_SFUNC(cp1gpio2c);
877 NPCM8XX_SFUNC(cp1gpio3c);
878 NPCM8XX_SFUNC(cp1gpio0b);
879 NPCM8XX_SFUNC(cp1gpio1b);
880 NPCM8XX_SFUNC(cp1gpio2b);
881 NPCM8XX_SFUNC(cp1gpio3b);
882 NPCM8XX_SFUNC(cp1gpio4b);
883 NPCM8XX_SFUNC(cp1gpio5b);
884 NPCM8XX_SFUNC(cp1gpio6b);
885 NPCM8XX_SFUNC(cp1gpio7b);
886 NPCM8XX_SFUNC(cp1gpio0);
887 NPCM8XX_SFUNC(cp1gpio1);
888 NPCM8XX_SFUNC(cp1gpio2);
889 NPCM8XX_SFUNC(cp1gpio3);
890 NPCM8XX_SFUNC(cp1gpio4);
891 NPCM8XX_SFUNC(cp1gpio5);
892 NPCM8XX_SFUNC(cp1gpio6);
893 NPCM8XX_SFUNC(cp1gpio7);
894 NPCM8XX_SFUNC(cp1utxd);
895 NPCM8XX_SFUNC(spi1cs3);
896 NPCM8XX_SFUNC(spi1cs2);
897 NPCM8XX_SFUNC(spi1cs1);
898 NPCM8XX_SFUNC(spi1cs0);
899 NPCM8XX_SFUNC(spi1d23);
900 NPCM8XX_SFUNC(j2j3);
901 NPCM8XX_SFUNC(r3oen);
902 NPCM8XX_SFUNC(r2oen);
903 NPCM8XX_SFUNC(r1oen);
904 NPCM8XX_SFUNC(bu4b);
905 NPCM8XX_SFUNC(bu4);
906 NPCM8XX_SFUNC(bu5b);
907 NPCM8XX_SFUNC(bu5);
908 NPCM8XX_SFUNC(bu6);
909 NPCM8XX_SFUNC(rmii3);
910 NPCM8XX_SFUNC(jm1);
911 NPCM8XX_SFUNC(jm2);
912 NPCM8XX_SFUNC(tpgpio5b);
913 NPCM8XX_SFUNC(tpgpio4b);
914 NPCM8XX_SFUNC(clkrun);
915 NPCM8XX_SFUNC(i3c5);
916 NPCM8XX_SFUNC(i3c4);
917 NPCM8XX_SFUNC(i3c3);
918 NPCM8XX_SFUNC(i3c2);
919 NPCM8XX_SFUNC(i3c1);
920 NPCM8XX_SFUNC(i3c0);
921 NPCM8XX_SFUNC(hsi1a);
922 NPCM8XX_SFUNC(hsi2a);
923 NPCM8XX_SFUNC(hsi1b);
924 NPCM8XX_SFUNC(hsi2b);
925 NPCM8XX_SFUNC(hsi1c);
926 NPCM8XX_SFUNC(hsi2c);
927 NPCM8XX_SFUNC(smb0);
928 NPCM8XX_SFUNC(smb0b);
929 NPCM8XX_SFUNC(smb0c);
930 NPCM8XX_SFUNC(smb0d);
931 NPCM8XX_SFUNC(smb0den);
932 NPCM8XX_SFUNC(smb1);
933 NPCM8XX_SFUNC(smb1b);
934 NPCM8XX_SFUNC(smb1c);
935 NPCM8XX_SFUNC(smb1d);
936 NPCM8XX_SFUNC(smb2);
937 NPCM8XX_SFUNC(smb2b);
938 NPCM8XX_SFUNC(smb2c);
939 NPCM8XX_SFUNC(smb2d);
940 NPCM8XX_SFUNC(smb3);
941 NPCM8XX_SFUNC(smb3b);
942 NPCM8XX_SFUNC(smb3c);
943 NPCM8XX_SFUNC(smb3d);
944 NPCM8XX_SFUNC(smb4);
945 NPCM8XX_SFUNC(smb4b);
946 NPCM8XX_SFUNC(smb4c);
947 NPCM8XX_SFUNC(smb4d);
948 NPCM8XX_SFUNC(smb5);
949 NPCM8XX_SFUNC(smb5b);
950 NPCM8XX_SFUNC(smb5c);
951 NPCM8XX_SFUNC(smb5d);
952 NPCM8XX_SFUNC(ga20kbc);
953 NPCM8XX_SFUNC(smb6);
954 NPCM8XX_SFUNC(smb6b);
955 NPCM8XX_SFUNC(smb6c);
956 NPCM8XX_SFUNC(smb6d);
957 NPCM8XX_SFUNC(smb7);
958 NPCM8XX_SFUNC(smb7b);
959 NPCM8XX_SFUNC(smb7c);
960 NPCM8XX_SFUNC(smb7d);
961 NPCM8XX_SFUNC(smb8);
962 NPCM8XX_SFUNC(smb9);
963 NPCM8XX_SFUNC(smb10);
964 NPCM8XX_SFUNC(smb11);
965 NPCM8XX_SFUNC(smb12);
966 NPCM8XX_SFUNC(smb13);
967 NPCM8XX_SFUNC(smb14);
968 NPCM8XX_SFUNC(smb14b);
969 NPCM8XX_SFUNC(smb15);
970 NPCM8XX_SFUNC(smb16);
971 NPCM8XX_SFUNC(smb16b);
972 NPCM8XX_SFUNC(smb17);
973 NPCM8XX_SFUNC(smb18);
974 NPCM8XX_SFUNC(smb19);
975 NPCM8XX_SFUNC(smb20);
976 NPCM8XX_SFUNC(smb21);
977 NPCM8XX_SFUNC(smb22);
978 NPCM8XX_SFUNC(smb23);
979 NPCM8XX_SFUNC(smb23b);
980 NPCM8XX_SFUNC(fanin0);
981 NPCM8XX_SFUNC(fanin1);
982 NPCM8XX_SFUNC(fanin2);
983 NPCM8XX_SFUNC(fanin3);
984 NPCM8XX_SFUNC(fanin4);
985 NPCM8XX_SFUNC(fanin5);
986 NPCM8XX_SFUNC(fanin6);
987 NPCM8XX_SFUNC(fanin7);
988 NPCM8XX_SFUNC(fanin8);
989 NPCM8XX_SFUNC(fanin9);
990 NPCM8XX_SFUNC(fanin10);
991 NPCM8XX_SFUNC(fanin11);
992 NPCM8XX_SFUNC(fanin12);
993 NPCM8XX_SFUNC(fanin13);
994 NPCM8XX_SFUNC(fanin14);
995 NPCM8XX_SFUNC(fanin15);
996 NPCM8XX_SFUNC(faninx);
997 NPCM8XX_SFUNC(pwm0);
998 NPCM8XX_SFUNC(pwm1);
999 NPCM8XX_SFUNC(pwm2);
1000 NPCM8XX_SFUNC(pwm3);
1001 NPCM8XX_SFUNC(pwm4);
1002 NPCM8XX_SFUNC(pwm5);
1003 NPCM8XX_SFUNC(pwm6);
1004 NPCM8XX_SFUNC(pwm7);
1005 NPCM8XX_SFUNC(pwm8);
1006 NPCM8XX_SFUNC(pwm9);
1007 NPCM8XX_SFUNC(pwm10);
1008 NPCM8XX_SFUNC(pwm11);
1009 NPCM8XX_SFUNC(sg1mdio);
1010 NPCM8XX_SFUNC(rg2);
1011 NPCM8XX_SFUNC(rg2mdio);
1012 NPCM8XX_SFUNC(ddr);
1013 NPCM8XX_SFUNC(uart1);
1014 NPCM8XX_SFUNC(uart2);
1015 NPCM8XX_SFUNC(bmcuart0a);
1016 NPCM8XX_SFUNC(bmcuart0b);
1017 NPCM8XX_SFUNC(bmcuart1);
1018 NPCM8XX_SFUNC(iox1);
1019 NPCM8XX_SFUNC(iox2);
1020 NPCM8XX_SFUNC(ioxh);
1021 NPCM8XX_SFUNC(gspi);
1022 NPCM8XX_SFUNC(mmc);
1023 NPCM8XX_SFUNC(mmcwp);
1024 NPCM8XX_SFUNC(mmccd);
1025 NPCM8XX_SFUNC(mmcrst);
1026 NPCM8XX_SFUNC(mmc8);
1027 NPCM8XX_SFUNC(r1);
1028 NPCM8XX_SFUNC(r1err);
1029 NPCM8XX_SFUNC(r1md);
1030 NPCM8XX_SFUNC(r2);
1031 NPCM8XX_SFUNC(r2err);
1032 NPCM8XX_SFUNC(r2md);
1033 NPCM8XX_SFUNC(sd1);
1034 NPCM8XX_SFUNC(sd1pwr);
1035 NPCM8XX_SFUNC(wdog1);
1036 NPCM8XX_SFUNC(wdog2);
1037 NPCM8XX_SFUNC(scipme);
1038 NPCM8XX_SFUNC(smi);
1039 NPCM8XX_SFUNC(serirq);
1040 NPCM8XX_SFUNC(jtag2);
1041 NPCM8XX_SFUNC(spix);
1042 NPCM8XX_SFUNC(spixcs1);
1043 NPCM8XX_SFUNC(spi1);
1044 NPCM8XX_SFUNC(pspi);
1045 NPCM8XX_SFUNC(ddc);
1046 NPCM8XX_SFUNC(clkreq);
1047 NPCM8XX_SFUNC(clkout);
1048 NPCM8XX_SFUNC(spi3);
1049 NPCM8XX_SFUNC(spi3cs1);
1050 NPCM8XX_SFUNC(spi3quad);
1051 NPCM8XX_SFUNC(spi3cs2);
1052 NPCM8XX_SFUNC(spi3cs3);
1053 NPCM8XX_SFUNC(spi0cs1);
1054 NPCM8XX_SFUNC(lpc);
1055 NPCM8XX_SFUNC(espi);
1056 NPCM8XX_SFUNC(lkgpo0);
1057 NPCM8XX_SFUNC(lkgpo1);
1058 NPCM8XX_SFUNC(lkgpo2);
1059 NPCM8XX_SFUNC(nprd_smi);
1060 NPCM8XX_SFUNC(hgpio0);
1061 NPCM8XX_SFUNC(hgpio1);
1062 NPCM8XX_SFUNC(hgpio2);
1063 NPCM8XX_SFUNC(hgpio3);
1064 NPCM8XX_SFUNC(hgpio4);
1065 NPCM8XX_SFUNC(hgpio5);
1066 NPCM8XX_SFUNC(hgpio6);
1067 NPCM8XX_SFUNC(hgpio7);
1068
1069 /* Function names */
1070 static struct pinfunction npcm8xx_funcs[] = {
1071 #define NPCM8XX_MKFUNC(nm) PINCTRL_PINFUNCTION(#nm, nm ## _grp, ARRAY_SIZE(nm ## _grp))
1072 NPCM8XX_MKFUNC(gpi36),
1073 NPCM8XX_MKFUNC(gpi35),
1074 NPCM8XX_MKFUNC(tp_jtag3),
1075 NPCM8XX_MKFUNC(tp_uart),
1076 NPCM8XX_MKFUNC(tp_smb2),
1077 NPCM8XX_MKFUNC(tp_smb1),
1078 NPCM8XX_MKFUNC(tp_gpio7),
1079 NPCM8XX_MKFUNC(tp_gpio6),
1080 NPCM8XX_MKFUNC(tp_gpio5),
1081 NPCM8XX_MKFUNC(tp_gpio4),
1082 NPCM8XX_MKFUNC(tp_gpio3),
1083 NPCM8XX_MKFUNC(tp_gpio2),
1084 NPCM8XX_MKFUNC(tp_gpio1),
1085 NPCM8XX_MKFUNC(tp_gpio0),
1086 NPCM8XX_MKFUNC(tp_gpio2b),
1087 NPCM8XX_MKFUNC(tp_gpio1b),
1088 NPCM8XX_MKFUNC(tp_gpio0b),
1089 NPCM8XX_MKFUNC(vgadig),
1090 NPCM8XX_MKFUNC(nbu1crts),
1091 NPCM8XX_MKFUNC(fm2),
1092 NPCM8XX_MKFUNC(fm1),
1093 NPCM8XX_MKFUNC(fm0),
1094 NPCM8XX_MKFUNC(gpio1836),
1095 NPCM8XX_MKFUNC(gpio1889),
1096 NPCM8XX_MKFUNC(gpo187),
1097 NPCM8XX_MKFUNC(cp1urxd),
1098 NPCM8XX_MKFUNC(r3rxer),
1099 NPCM8XX_MKFUNC(cp1gpio2c),
1100 NPCM8XX_MKFUNC(cp1gpio3c),
1101 NPCM8XX_MKFUNC(cp1gpio0b),
1102 NPCM8XX_MKFUNC(cp1gpio1b),
1103 NPCM8XX_MKFUNC(cp1gpio2b),
1104 NPCM8XX_MKFUNC(cp1gpio3b),
1105 NPCM8XX_MKFUNC(cp1gpio4b),
1106 NPCM8XX_MKFUNC(cp1gpio5b),
1107 NPCM8XX_MKFUNC(cp1gpio6b),
1108 NPCM8XX_MKFUNC(cp1gpio7b),
1109 NPCM8XX_MKFUNC(cp1gpio0),
1110 NPCM8XX_MKFUNC(cp1gpio1),
1111 NPCM8XX_MKFUNC(cp1gpio2),
1112 NPCM8XX_MKFUNC(cp1gpio3),
1113 NPCM8XX_MKFUNC(cp1gpio4),
1114 NPCM8XX_MKFUNC(cp1gpio5),
1115 NPCM8XX_MKFUNC(cp1gpio6),
1116 NPCM8XX_MKFUNC(cp1gpio7),
1117 NPCM8XX_MKFUNC(cp1utxd),
1118 NPCM8XX_MKFUNC(spi1cs3),
1119 NPCM8XX_MKFUNC(spi1cs2),
1120 NPCM8XX_MKFUNC(spi1cs1),
1121 NPCM8XX_MKFUNC(spi1cs0),
1122 NPCM8XX_MKFUNC(spi1d23),
1123 NPCM8XX_MKFUNC(j2j3),
1124 NPCM8XX_MKFUNC(r3oen),
1125 NPCM8XX_MKFUNC(r2oen),
1126 NPCM8XX_MKFUNC(r1oen),
1127 NPCM8XX_MKFUNC(bu4b),
1128 NPCM8XX_MKFUNC(bu4),
1129 NPCM8XX_MKFUNC(bu5b),
1130 NPCM8XX_MKFUNC(bu5),
1131 NPCM8XX_MKFUNC(bu6),
1132 NPCM8XX_MKFUNC(rmii3),
1133 NPCM8XX_MKFUNC(jm1),
1134 NPCM8XX_MKFUNC(jm2),
1135 NPCM8XX_MKFUNC(tpgpio5b),
1136 NPCM8XX_MKFUNC(tpgpio4b),
1137 NPCM8XX_MKFUNC(clkrun),
1138 NPCM8XX_MKFUNC(i3c5),
1139 NPCM8XX_MKFUNC(i3c4),
1140 NPCM8XX_MKFUNC(i3c3),
1141 NPCM8XX_MKFUNC(i3c2),
1142 NPCM8XX_MKFUNC(i3c1),
1143 NPCM8XX_MKFUNC(i3c0),
1144 NPCM8XX_MKFUNC(hsi1a),
1145 NPCM8XX_MKFUNC(hsi2a),
1146 NPCM8XX_MKFUNC(hsi1b),
1147 NPCM8XX_MKFUNC(hsi2b),
1148 NPCM8XX_MKFUNC(hsi1c),
1149 NPCM8XX_MKFUNC(hsi2c),
1150 NPCM8XX_MKFUNC(smb0),
1151 NPCM8XX_MKFUNC(smb0b),
1152 NPCM8XX_MKFUNC(smb0c),
1153 NPCM8XX_MKFUNC(smb0d),
1154 NPCM8XX_MKFUNC(smb0den),
1155 NPCM8XX_MKFUNC(smb1),
1156 NPCM8XX_MKFUNC(smb1b),
1157 NPCM8XX_MKFUNC(smb1c),
1158 NPCM8XX_MKFUNC(smb1d),
1159 NPCM8XX_MKFUNC(smb2),
1160 NPCM8XX_MKFUNC(smb2b),
1161 NPCM8XX_MKFUNC(smb2c),
1162 NPCM8XX_MKFUNC(smb2d),
1163 NPCM8XX_MKFUNC(smb3),
1164 NPCM8XX_MKFUNC(smb3b),
1165 NPCM8XX_MKFUNC(smb3c),
1166 NPCM8XX_MKFUNC(smb3d),
1167 NPCM8XX_MKFUNC(smb4),
1168 NPCM8XX_MKFUNC(smb4b),
1169 NPCM8XX_MKFUNC(smb4c),
1170 NPCM8XX_MKFUNC(smb4d),
1171 NPCM8XX_MKFUNC(smb5),
1172 NPCM8XX_MKFUNC(smb5b),
1173 NPCM8XX_MKFUNC(smb5c),
1174 NPCM8XX_MKFUNC(smb5d),
1175 NPCM8XX_MKFUNC(ga20kbc),
1176 NPCM8XX_MKFUNC(smb6),
1177 NPCM8XX_MKFUNC(smb6b),
1178 NPCM8XX_MKFUNC(smb6c),
1179 NPCM8XX_MKFUNC(smb6d),
1180 NPCM8XX_MKFUNC(smb7),
1181 NPCM8XX_MKFUNC(smb7b),
1182 NPCM8XX_MKFUNC(smb7c),
1183 NPCM8XX_MKFUNC(smb7d),
1184 NPCM8XX_MKFUNC(smb8),
1185 NPCM8XX_MKFUNC(smb9),
1186 NPCM8XX_MKFUNC(smb10),
1187 NPCM8XX_MKFUNC(smb11),
1188 NPCM8XX_MKFUNC(smb12),
1189 NPCM8XX_MKFUNC(smb13),
1190 NPCM8XX_MKFUNC(smb14),
1191 NPCM8XX_MKFUNC(smb14b),
1192 NPCM8XX_MKFUNC(smb15),
1193 NPCM8XX_MKFUNC(smb16),
1194 NPCM8XX_MKFUNC(smb16b),
1195 NPCM8XX_MKFUNC(smb17),
1196 NPCM8XX_MKFUNC(smb18),
1197 NPCM8XX_MKFUNC(smb19),
1198 NPCM8XX_MKFUNC(smb20),
1199 NPCM8XX_MKFUNC(smb21),
1200 NPCM8XX_MKFUNC(smb22),
1201 NPCM8XX_MKFUNC(smb23),
1202 NPCM8XX_MKFUNC(smb23b),
1203 NPCM8XX_MKFUNC(fanin0),
1204 NPCM8XX_MKFUNC(fanin1),
1205 NPCM8XX_MKFUNC(fanin2),
1206 NPCM8XX_MKFUNC(fanin3),
1207 NPCM8XX_MKFUNC(fanin4),
1208 NPCM8XX_MKFUNC(fanin5),
1209 NPCM8XX_MKFUNC(fanin6),
1210 NPCM8XX_MKFUNC(fanin7),
1211 NPCM8XX_MKFUNC(fanin8),
1212 NPCM8XX_MKFUNC(fanin9),
1213 NPCM8XX_MKFUNC(fanin10),
1214 NPCM8XX_MKFUNC(fanin11),
1215 NPCM8XX_MKFUNC(fanin12),
1216 NPCM8XX_MKFUNC(fanin13),
1217 NPCM8XX_MKFUNC(fanin14),
1218 NPCM8XX_MKFUNC(fanin15),
1219 NPCM8XX_MKFUNC(faninx),
1220 NPCM8XX_MKFUNC(pwm0),
1221 NPCM8XX_MKFUNC(pwm1),
1222 NPCM8XX_MKFUNC(pwm2),
1223 NPCM8XX_MKFUNC(pwm3),
1224 NPCM8XX_MKFUNC(pwm4),
1225 NPCM8XX_MKFUNC(pwm5),
1226 NPCM8XX_MKFUNC(pwm6),
1227 NPCM8XX_MKFUNC(pwm7),
1228 NPCM8XX_MKFUNC(pwm8),
1229 NPCM8XX_MKFUNC(pwm9),
1230 NPCM8XX_MKFUNC(pwm10),
1231 NPCM8XX_MKFUNC(pwm11),
1232 NPCM8XX_MKFUNC(sg1mdio),
1233 NPCM8XX_MKFUNC(rg2),
1234 NPCM8XX_MKFUNC(rg2mdio),
1235 NPCM8XX_MKFUNC(ddr),
1236 NPCM8XX_MKFUNC(uart1),
1237 NPCM8XX_MKFUNC(uart2),
1238 NPCM8XX_MKFUNC(bmcuart0a),
1239 NPCM8XX_MKFUNC(bmcuart0b),
1240 NPCM8XX_MKFUNC(bmcuart1),
1241 NPCM8XX_MKFUNC(iox1),
1242 NPCM8XX_MKFUNC(iox2),
1243 NPCM8XX_MKFUNC(ioxh),
1244 NPCM8XX_MKFUNC(gspi),
1245 NPCM8XX_MKFUNC(mmc),
1246 NPCM8XX_MKFUNC(mmcwp),
1247 NPCM8XX_MKFUNC(mmccd),
1248 NPCM8XX_MKFUNC(mmcrst),
1249 NPCM8XX_MKFUNC(mmc8),
1250 NPCM8XX_MKFUNC(r1),
1251 NPCM8XX_MKFUNC(r1err),
1252 NPCM8XX_MKFUNC(r1md),
1253 NPCM8XX_MKFUNC(r2),
1254 NPCM8XX_MKFUNC(r2err),
1255 NPCM8XX_MKFUNC(r2md),
1256 NPCM8XX_MKFUNC(sd1),
1257 NPCM8XX_MKFUNC(sd1pwr),
1258 NPCM8XX_MKFUNC(wdog1),
1259 NPCM8XX_MKFUNC(wdog2),
1260 NPCM8XX_MKFUNC(scipme),
1261 NPCM8XX_MKFUNC(smi),
1262 NPCM8XX_MKFUNC(serirq),
1263 NPCM8XX_MKFUNC(jtag2),
1264 NPCM8XX_MKFUNC(spix),
1265 NPCM8XX_MKFUNC(spixcs1),
1266 NPCM8XX_MKFUNC(spi1),
1267 NPCM8XX_MKFUNC(pspi),
1268 NPCM8XX_MKFUNC(ddc),
1269 NPCM8XX_MKFUNC(clkreq),
1270 NPCM8XX_MKFUNC(clkout),
1271 NPCM8XX_MKFUNC(spi3),
1272 NPCM8XX_MKFUNC(spi3cs1),
1273 NPCM8XX_MKFUNC(spi3quad),
1274 NPCM8XX_MKFUNC(spi3cs2),
1275 NPCM8XX_MKFUNC(spi3cs3),
1276 NPCM8XX_MKFUNC(spi0cs1),
1277 NPCM8XX_MKFUNC(lpc),
1278 NPCM8XX_MKFUNC(espi),
1279 NPCM8XX_MKFUNC(lkgpo0),
1280 NPCM8XX_MKFUNC(lkgpo1),
1281 NPCM8XX_MKFUNC(lkgpo2),
1282 NPCM8XX_MKFUNC(nprd_smi),
1283 NPCM8XX_MKFUNC(hgpio0),
1284 NPCM8XX_MKFUNC(hgpio1),
1285 NPCM8XX_MKFUNC(hgpio2),
1286 NPCM8XX_MKFUNC(hgpio3),
1287 NPCM8XX_MKFUNC(hgpio4),
1288 NPCM8XX_MKFUNC(hgpio5),
1289 NPCM8XX_MKFUNC(hgpio6),
1290 NPCM8XX_MKFUNC(hgpio7),
1291 #undef NPCM8XX_MKFUNC
1292 };
1293
1294 #define NPCM8XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q) \
1295 [a] = { \
1296 .flag = q, \
1297 .fn0 = fn_ ## b, .reg0 = NPCM8XX_GCR_ ## c, .bit0 = d, \
1298 .fn1 = fn_ ## e, .reg1 = NPCM8XX_GCR_ ## f, .bit1 = g, \
1299 .fn2 = fn_ ## h, .reg2 = NPCM8XX_GCR_ ## i, .bit2 = j, \
1300 .fn3 = fn_ ## k, .reg3 = NPCM8XX_GCR_ ## l, .bit3 = m, \
1301 .fn4 = fn_ ## n, .reg4 = NPCM8XX_GCR_ ## o, .bit4 = p, \
1302 }
1303
1304 /* Drive strength controlled by NPCM8XX_GP_N_ODSC */
1305 #define DRIVE_STRENGTH_LO_SHIFT 8
1306 #define DRIVE_STRENGTH_HI_SHIFT 12
1307 #define DRIVE_STRENGTH_MASK GENMASK(15, 8)
1308 #define DSTR_RG2 BIT(16)
1309
1310 #define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
1311 ((hi) << DRIVE_STRENGTH_HI_SHIFT))
1312 #define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & GENMASK(3, 0))
1313 #define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & GENMASK(3, 0))
1314
1315 #define GPI BIT(0) /* Not GPO */
1316 #define GPO BIT(1) /* Not GPI */
1317 #define SLEW BIT(2) /* Has Slew Control, NPCM8XX_GP_N_OSRC */
1318 #define SLEWLPC BIT(3) /* Has Slew Control, SRCNT.3 */
1319
1320 struct npcm8xx_pincfg {
1321 int flag;
1322 int fn0, reg0, bit0;
1323 int fn1, reg1, bit1;
1324 int fn2, reg2, bit2;
1325 int fn3, reg3, bit3;
1326 int fn4, reg4, bit4;
1327 };
1328
1329 static const struct npcm8xx_pincfg pincfg[] = {
1330 /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FUNCTION 4 FUNCTION 5 FLAGS */
1331 NPCM8XX_PINCFG(0, iox1, MFSEL1, 30, smb6c, I2CSEGSEL, 25, smb18, MFSEL5, 26, none, NONE, 0, none, NONE, 0, SLEW),
1332 NPCM8XX_PINCFG(1, iox1, MFSEL1, 30, smb6c, I2CSEGSEL, 25, smb18, MFSEL5, 26, none, NONE, 0, none, NONE, 0, SLEW),
1333 NPCM8XX_PINCFG(2, iox1, MFSEL1, 30, smb6b, I2CSEGSEL, 24, smb17, MFSEL5, 25, none, NONE, 0, none, NONE, 0, SLEW),
1334 NPCM8XX_PINCFG(3, iox1, MFSEL1, 30, smb6b, I2CSEGSEL, 24, smb17, MFSEL5, 25, none, NONE, 0, none, NONE, 0, SLEW),
1335 NPCM8XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1336 NPCM8XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1337 NPCM8XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1338 NPCM8XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1339 NPCM8XX_PINCFG(8, lkgpo1, FLOCKR1, 4, tp_gpio0b, MFSEL7, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1340 NPCM8XX_PINCFG(9, lkgpo2, FLOCKR1, 8, tp_gpio1b, MFSEL7, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1341 NPCM8XX_PINCFG(10, ioxh, MFSEL3, 18, smb6d, I2CSEGSEL, 26, smb16, MFSEL5, 24, none, NONE, 0, none, NONE, 0, SLEW),
1342 NPCM8XX_PINCFG(11, ioxh, MFSEL3, 18, smb6d, I2CSEGSEL, 26, smb16, MFSEL5, 24, none, NONE, 0, none, NONE, 0, SLEW),
1343 NPCM8XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1344 NPCM8XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1345 NPCM8XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1346 NPCM8XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1347 NPCM8XX_PINCFG(16, lkgpo0, FLOCKR1, 0, smb7b, I2CSEGSEL, 27, tp_gpio2b, MFSEL7, 10, none, NONE, 0, none, NONE, 0, SLEW),
1348 NPCM8XX_PINCFG(17, pspi, MFSEL3, 13, cp1gpio5, MFSEL6, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1349 NPCM8XX_PINCFG(18, pspi, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1350 NPCM8XX_PINCFG(19, pspi, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1351 NPCM8XX_PINCFG(20, hgpio0, MFSEL2, 24, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, none, NONE, 0, none, NONE, 0, SLEW),
1352 NPCM8XX_PINCFG(21, hgpio1, MFSEL2, 25, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, none, NONE, 0, none, NONE, 0, SLEW),
1353 NPCM8XX_PINCFG(22, hgpio2, MFSEL2, 26, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, none, NONE, 0, none, NONE, 0, SLEW),
1354 NPCM8XX_PINCFG(23, hgpio3, MFSEL2, 27, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, none, NONE, 0, none, NONE, 0, SLEW),
1355 NPCM8XX_PINCFG(24, hgpio4, MFSEL2, 28, ioxh, MFSEL3, 18, smb7c, I2CSEGSEL, 28, tp_smb2, MFSEL7, 28, none, NONE, 0, SLEW),
1356 NPCM8XX_PINCFG(25, hgpio5, MFSEL2, 29, ioxh, MFSEL3, 18, smb7c, I2CSEGSEL, 28, tp_smb2, MFSEL7, 28, none, NONE, 0, SLEW),
1357 NPCM8XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1358 NPCM8XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1359 NPCM8XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1360 NPCM8XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1361 NPCM8XX_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1362 NPCM8XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1363 NPCM8XX_PINCFG(32, spi0cs1, MFSEL1, 3, smb14b, MFSEL7, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1364 NPCM8XX_PINCFG(33, i3c4, MFSEL6, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1365 NPCM8XX_PINCFG(34, i3c4, MFSEL6, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1366 NPCM8XX_PINCFG(35, gpi35, MFSEL5, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1367 NPCM8XX_PINCFG(36, gpi36, MFSEL5, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1368 NPCM8XX_PINCFG(37, smb3c, I2CSEGSEL, 12, smb23, MFSEL5, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1369 NPCM8XX_PINCFG(38, smb3c, I2CSEGSEL, 12, smb23, MFSEL5, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1370 NPCM8XX_PINCFG(39, smb3b, I2CSEGSEL, 11, smb22, MFSEL5, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1371 NPCM8XX_PINCFG(40, smb3b, I2CSEGSEL, 11, smb22, MFSEL5, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1372 NPCM8XX_PINCFG(41, bmcuart0a, MFSEL1, 9, cp1urxd, MFSEL6, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1373 NPCM8XX_PINCFG(42, bmcuart0a, MFSEL1, 9, cp1utxd, MFSEL6, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO),
1374 NPCM8XX_PINCFG(43, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1375 NPCM8XX_PINCFG(44, hsi1b, MFSEL1, 28, nbu1crts, MFSEL6, 15, jtag2, MFSEL4, 0, tp_jtag3, MFSEL7, 13, j2j3, MFSEL5, 2, GPO),
1376 NPCM8XX_PINCFG(45, hsi1c, MFSEL1, 4, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, tp_jtag3, MFSEL7, 13, none, NONE, 0, GPO),
1377 NPCM8XX_PINCFG(46, hsi1c, MFSEL1, 4, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, tp_jtag3, MFSEL7, 13, none, NONE, 0, GPO),
1378 NPCM8XX_PINCFG(47, hsi1c, MFSEL1, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 8)),
1379 NPCM8XX_PINCFG(48, hsi2a, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1380 NPCM8XX_PINCFG(49, hsi2a, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1381 NPCM8XX_PINCFG(50, hsi2b, MFSEL1, 29, bu6, MFSEL5, 6, tp_uart, MFSEL7, 12, none, NONE, 0, none, NONE, 0, GPO),
1382 NPCM8XX_PINCFG(51, hsi2b, MFSEL1, 29, bu6, MFSEL5, 6, tp_uart, MFSEL7, 12, none, NONE, 0, none, NONE, 0, GPO),
1383 NPCM8XX_PINCFG(52, hsi2c, MFSEL1, 5, bu5, MFSEL5, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1384 NPCM8XX_PINCFG(53, hsi2c, MFSEL1, 5, bu5, MFSEL5, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1385 NPCM8XX_PINCFG(54, hsi2c, MFSEL1, 5, bu4, MFSEL5, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1386 NPCM8XX_PINCFG(55, hsi2c, MFSEL1, 5, bu4, MFSEL5, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1387 NPCM8XX_PINCFG(56, r1err, MFSEL1, 12, r1oen, MFSEL5, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1388 NPCM8XX_PINCFG(57, r1md, MFSEL1, 13, tpgpio4b, MFSEL5, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1389 NPCM8XX_PINCFG(58, r1md, MFSEL1, 13, tpgpio5b, MFSEL5, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1390 NPCM8XX_PINCFG(59, hgpio6, MFSEL2, 30, smb3d, I2CSEGSEL, 13, smb19, MFSEL5, 27, none, NONE, 0, none, NONE, 0, 0),
1391 NPCM8XX_PINCFG(60, hgpio7, MFSEL2, 31, smb3d, I2CSEGSEL, 13, smb19, MFSEL5, 27, none, NONE, 0, none, NONE, 0, 0),
1392 NPCM8XX_PINCFG(61, hsi1c, MFSEL1, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1393 NPCM8XX_PINCFG(62, hsi1b, MFSEL1, 28, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, nbu1crts, MFSEL6, 15, tp_jtag3, MFSEL7, 13, GPO),
1394 NPCM8XX_PINCFG(63, hsi1a, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1395 NPCM8XX_PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1396 NPCM8XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1397 NPCM8XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1398 NPCM8XX_PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1399 NPCM8XX_PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1400 NPCM8XX_PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1401 NPCM8XX_PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1402 NPCM8XX_PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1403 NPCM8XX_PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1404 NPCM8XX_PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1405 NPCM8XX_PINCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1406 NPCM8XX_PINCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1407 NPCM8XX_PINCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1408 NPCM8XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1409 NPCM8XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1410 NPCM8XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1411 NPCM8XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1412 NPCM8XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1413 NPCM8XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1414 NPCM8XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1415 NPCM8XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1416 NPCM8XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1417 NPCM8XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1418 NPCM8XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1419 NPCM8XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1420 NPCM8XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1421 NPCM8XX_PINCFG(90, r2err, MFSEL1, 15, r2oen, MFSEL5, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1422 NPCM8XX_PINCFG(91, r2md, MFSEL1, 16, cp1gpio6, MFSEL6, 8, tp_gpio0, MFSEL7, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1423 NPCM8XX_PINCFG(92, r2md, MFSEL1, 16, cp1gpio7, MFSEL6, 9, tp_gpio1, MFSEL7, 1, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1424 NPCM8XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1425 NPCM8XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1426 NPCM8XX_PINCFG(95, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1427 NPCM8XX_PINCFG(96, cp1gpio7b, MFSEL6, 24, tp_gpio7, MFSEL7, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1428 NPCM8XX_PINCFG(97, cp1gpio6b, MFSEL6, 25, tp_gpio6, MFSEL7, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1429 NPCM8XX_PINCFG(98, bu4b, MFSEL5, 13, cp1gpio5b, MFSEL6, 26, tp_gpio5, MFSEL7, 5, none, NONE, 0, none, NONE, 0, SLEW),
1430 NPCM8XX_PINCFG(99, bu4b, MFSEL5, 13, cp1gpio4b, MFSEL6, 27, tp_gpio4, MFSEL7, 4, none, NONE, 0, none, NONE, 0, SLEW),
1431 NPCM8XX_PINCFG(100, bu5b, MFSEL5, 12, cp1gpio3c, MFSEL6, 28, tp_gpio3, MFSEL7, 3, none, NONE, 0, none, NONE, 0, SLEW),
1432 NPCM8XX_PINCFG(101, bu5b, MFSEL5, 12, cp1gpio2c, MFSEL6, 29, tp_gpio2, MFSEL7, 2, none, NONE, 0, none, NONE, 0, SLEW),
1433 NPCM8XX_PINCFG(102, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1434 NPCM8XX_PINCFG(103, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1435 NPCM8XX_PINCFG(104, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1436 NPCM8XX_PINCFG(105, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1437 NPCM8XX_PINCFG(106, i3c5, MFSEL3, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1438 NPCM8XX_PINCFG(107, i3c5, MFSEL3, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1439 NPCM8XX_PINCFG(108, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1440 NPCM8XX_PINCFG(109, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1441 NPCM8XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW),
1442 NPCM8XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW),
1443 NPCM8XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW),
1444 NPCM8XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW),
1445 NPCM8XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1446 NPCM8XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1447 NPCM8XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1448 NPCM8XX_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1449 NPCM8XX_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1450 NPCM8XX_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1451 NPCM8XX_PINCFG(120, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1452 NPCM8XX_PINCFG(121, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1453 NPCM8XX_PINCFG(122, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1454 NPCM8XX_PINCFG(123, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1455 NPCM8XX_PINCFG(124, smb1c, I2CSEGSEL, 6, cp1gpio3b, MFSEL6, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1456 NPCM8XX_PINCFG(125, smb1c, I2CSEGSEL, 6, cp1gpio2b, MFSEL6, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1457 NPCM8XX_PINCFG(126, smb1b, I2CSEGSEL, 5, cp1gpio1b, MFSEL6, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1458 NPCM8XX_PINCFG(127, smb1b, I2CSEGSEL, 5, cp1gpio0b, MFSEL6, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1459 NPCM8XX_PINCFG(128, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1460 NPCM8XX_PINCFG(129, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1461 NPCM8XX_PINCFG(130, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1462 NPCM8XX_PINCFG(131, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1463 NPCM8XX_PINCFG(132, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1464 NPCM8XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1465 NPCM8XX_PINCFG(134, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1466 NPCM8XX_PINCFG(135, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1467 NPCM8XX_PINCFG(136, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1468 NPCM8XX_PINCFG(137, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1469 NPCM8XX_PINCFG(138, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1470 NPCM8XX_PINCFG(139, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1471 NPCM8XX_PINCFG(140, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1472 NPCM8XX_PINCFG(141, smb7b, I2CSEGSEL, 27, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1473 NPCM8XX_PINCFG(142, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1474 NPCM8XX_PINCFG(143, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1475 NPCM8XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1476 NPCM8XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1477 NPCM8XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1478 NPCM8XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
1479 NPCM8XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1480 NPCM8XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1481 NPCM8XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1482 NPCM8XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1483 NPCM8XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1484 NPCM8XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1485 NPCM8XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1486 NPCM8XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1487 NPCM8XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1488 NPCM8XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1489 NPCM8XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1490 NPCM8XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1491 NPCM8XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1492 NPCM8XX_PINCFG(161, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1493 NPCM8XX_PINCFG(162, clkrun, MFSEL3, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1494 NPCM8XX_PINCFG(163, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1495 NPCM8XX_PINCFG(164, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1496 NPCM8XX_PINCFG(165, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1497 NPCM8XX_PINCFG(166, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1498 NPCM8XX_PINCFG(167, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1499 NPCM8XX_PINCFG(168, serirq, MFSEL1, 31, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1500 NPCM8XX_PINCFG(169, scipme, MFSEL3, 0, smb21, MFSEL5, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1501 NPCM8XX_PINCFG(170, smi, MFSEL1, 22, smb21, MFSEL5, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1502 NPCM8XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1503 NPCM8XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1504 NPCM8XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1505 NPCM8XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1506 NPCM8XX_PINCFG(175, spi1, MFSEL3, 4, faninx, MFSEL3, 3, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1507 NPCM8XX_PINCFG(176, spi1, MFSEL3, 4, faninx, MFSEL3, 3, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1508 NPCM8XX_PINCFG(177, spi1, MFSEL3, 4, faninx, MFSEL3, 3, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1509 NPCM8XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1510 NPCM8XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1511 NPCM8XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1512 NPCM8XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1513 NPCM8XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1514 NPCM8XX_PINCFG(183, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1515 NPCM8XX_PINCFG(184, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1516 NPCM8XX_PINCFG(185, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1517 NPCM8XX_PINCFG(186, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1518 NPCM8XX_PINCFG(187, gpo187, MFSEL7, 24, smb14b, MFSEL7, 26, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, SLEW),
1519 NPCM8XX_PINCFG(188, gpio1889, MFSEL7, 25, spi3cs2, MFSEL4, 18, spi3quad, MFSEL4, 20, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1520 NPCM8XX_PINCFG(189, gpio1889, MFSEL7, 25, spi3cs3, MFSEL4, 19, spi3quad, MFSEL4, 20, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1521 NPCM8XX_PINCFG(190, nprd_smi, FLOCKR1, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1522 NPCM8XX_PINCFG(191, spi1d23, MFSEL5, 3, spi1cs2, MFSEL5, 4, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, SLEW), /* XX */
1523 NPCM8XX_PINCFG(192, spi1d23, MFSEL5, 3, spi1cs3, MFSEL5, 5, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, SLEW), /* XX */
1524 NPCM8XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1525 NPCM8XX_PINCFG(194, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1526 NPCM8XX_PINCFG(195, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1527 NPCM8XX_PINCFG(196, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1528 NPCM8XX_PINCFG(197, smb0den, I2CSEGSEL, 22, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1529 NPCM8XX_PINCFG(198, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1530 NPCM8XX_PINCFG(199, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1531 NPCM8XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1532 NPCM8XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1533 NPCM8XX_PINCFG(202, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1534 NPCM8XX_PINCFG(203, faninx, MFSEL3, 3, spi1cs0, MFSEL3, 4, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1535 NPCM8XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW),
1536 NPCM8XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW),
1537 NPCM8XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1538 NPCM8XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1539 NPCM8XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, r3rxer, MFSEL6, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1540 NPCM8XX_PINCFG(213, rg2, MFSEL4, 24, ddr, MFSEL3, 26, r3oen, MFSEL5, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1541 NPCM8XX_PINCFG(214, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1542 NPCM8XX_PINCFG(215, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1543 NPCM8XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1544 NPCM8XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1545 NPCM8XX_PINCFG(218, wdog1, MFSEL3, 19, smb16b, MFSEL7, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1546 NPCM8XX_PINCFG(219, wdog2, MFSEL3, 20, smb16b, MFSEL7, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1547 NPCM8XX_PINCFG(220, smb12, MFSEL3, 5, pwm8, MFSEL6, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1548 NPCM8XX_PINCFG(221, smb12, MFSEL3, 5, pwm9, MFSEL6, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1549 NPCM8XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1550 NPCM8XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1551 NPCM8XX_PINCFG(224, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1552 NPCM8XX_PINCFG(225, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1553 NPCM8XX_PINCFG(226, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLEW),
1554 NPCM8XX_PINCFG(227, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1555 NPCM8XX_PINCFG(228, spixcs1, MFSEL4, 28, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1556 NPCM8XX_PINCFG(229, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLEW),
1557 NPCM8XX_PINCFG(230, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLEW),
1558 NPCM8XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 12) | SLEW),
1559 NPCM8XX_PINCFG(233, spi1cs1, MFSEL5, 0, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), /* slewlpc ? */
1560 NPCM8XX_PINCFG(234, pwm10, MFSEL6, 13, smb20, MFSEL5, 28, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1561 NPCM8XX_PINCFG(235, pwm11, MFSEL6, 14, smb20, MFSEL5, 28, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1562 NPCM8XX_PINCFG(240, i3c0, MFSEL5, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1563 NPCM8XX_PINCFG(241, i3c0, MFSEL5, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1564 NPCM8XX_PINCFG(242, i3c1, MFSEL5, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1565 NPCM8XX_PINCFG(243, i3c1, MFSEL5, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1566 NPCM8XX_PINCFG(244, i3c2, MFSEL5, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1567 NPCM8XX_PINCFG(245, i3c2, MFSEL5, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1568 NPCM8XX_PINCFG(246, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1569 NPCM8XX_PINCFG(247, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1570 NPCM8XX_PINCFG(250, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1571 NPCM8XX_PINCFG(251, jm2, MFSEL5, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1572 NPCM8XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */
1573 NPCM8XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */
1574 NPCM8XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */
1575 };
1576
1577 /* number, name, drv_data */
1578 static const struct pinctrl_pin_desc npcm8xx_pins[] = {
1579 PINCTRL_PIN(0, "GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA"),
1580 PINCTRL_PIN(1, "GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL"),
1581 PINCTRL_PIN(2, "GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA"),
1582 PINCTRL_PIN(3, "GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL"),
1583 PINCTRL_PIN(4, "GPIO4/IOX2_DI/SMB1D_SDA"),
1584 PINCTRL_PIN(5, "GPIO5/IOX2_LD/SMB1D_SCL"),
1585 PINCTRL_PIN(6, "GPIO6/IOX2_CK/SMB2D_SDA"),
1586 PINCTRL_PIN(7, "GPIO7/IOX2_DO/SMB2D_SCL"),
1587 PINCTRL_PIN(8, "GPIO8/LKGPO1/TP_GPIO0"),
1588 PINCTRL_PIN(9, "GPIO9/LKGPO2/TP_GPIO1"),
1589 PINCTRL_PIN(10, "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL"),
1590 PINCTRL_PIN(11, "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA"),
1591 PINCTRL_PIN(12, "GPIO12/GSPI_CK/SMB5B_SCL"),
1592 PINCTRL_PIN(13, "GPIO13/GSPI_DO/SMB5B_SDA"),
1593 PINCTRL_PIN(14, "GPIO14/GSPI_DI/SMB5C_SCL"),
1594 PINCTRL_PIN(15, "GPIO15/GSPI_CS/SMB5C_SDA"),
1595 PINCTRL_PIN(16, "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2"),
1596 PINCTRL_PIN(17, "GPIO17/PSPI_DI/CP1_GPIO5"),
1597 PINCTRL_PIN(18, "GPIO18/PSPI_D0/SMB4B_SDA"),
1598 PINCTRL_PIN(19, "GPIO19/PSPI_CK/SMB4B_SCL"),
1599 PINCTRL_PIN(20, "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA"),
1600 PINCTRL_PIN(21, "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL"),
1601 PINCTRL_PIN(22, "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA"),
1602 PINCTRL_PIN(23, "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL"),
1603 PINCTRL_PIN(24, "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL"),
1604 PINCTRL_PIN(25, "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA"),
1605 PINCTRL_PIN(26, "GPIO26/SMB5_SDA"),
1606 PINCTRL_PIN(27, "GPIO27/SMB5_SCL"),
1607 PINCTRL_PIN(28, "GPIO28/SMB4_SDA"),
1608 PINCTRL_PIN(29, "GPIO29/SMB4_SCL"),
1609 PINCTRL_PIN(30, "GPIO30/SMB3_SDA"),
1610 PINCTRL_PIN(31, "GPIO31/SMB3_SCL"),
1611 PINCTRL_PIN(32, "GPIO32/SMB14B_SCL/SPI0_nCS1"),
1612 PINCTRL_PIN(33, "GPIO33/I3C4_SCL"),
1613 PINCTRL_PIN(34, "GPIO34/I3C4_SDA"),
1614 PINCTRL_PIN(35, "MCBPCK/GPI35_AHB2PCI_DIS"),
1615 PINCTRL_PIN(36, "SYSBPCK/GPI36"),
1616 PINCTRL_PIN(37, "GPIO37/SMB3C_SDA/SMB23_SDA"),
1617 PINCTRL_PIN(38, "GPIO38/SMB3C_SCL/SMB23_SCL"),
1618 PINCTRL_PIN(39, "GPIO39/SMB3B_SDA/SMB22_SDA"),
1619 PINCTRL_PIN(40, "GPIO40/SMB3B_SCL/SMB22_SCL"),
1620 PINCTRL_PIN(41, "GPIO41/BU0_RXD/CP1U_RXD"),
1621 PINCTRL_PIN(42, "GPIO42/BU0_TXD/CP1U_TXD"),
1622 PINCTRL_PIN(43, "GPIO43/SI1_RXD/BU1_RXD"),
1623 PINCTRL_PIN(44, "GPIO44/SI1_nCTS/BU1_nCTS/CP_TDI/TP_TDI/CP_TP_TDI"),
1624 PINCTRL_PIN(45, "GPIO45/SI1_nDCD/CP_TMS_SWIO/TP_TMS_SWIO/CP_TP_TMS_SWIO"),
1625 PINCTRL_PIN(46, "GPIO46/SI1_nDSR/CP_TCK_SWCLK/TP_TCK_SWCLK/CP_TP_TCK_SWCLK"),
1626 PINCTRL_PIN(47, "GPIO47/SI1n_RI1"),
1627 PINCTRL_PIN(48, "GPIO48/SI2_TXD/BU0_TXD/STRAP5"),
1628 PINCTRL_PIN(49, "GPIO49/SI2_RXD/BU0_RXD"),
1629 PINCTRL_PIN(50, "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD"),
1630 PINCTRL_PIN(51, "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD"),
1631 PINCTRL_PIN(52, "GPIO52/SI2_nDCD/BU5_RXD"),
1632 PINCTRL_PIN(53, "GPIO53/SI2_nDTR_BOUT2/BU5_TXD"),
1633 PINCTRL_PIN(54, "GPIO54/SI2_nDSR/BU4_TXD"),
1634 PINCTRL_PIN(55, "GPIO55/SI2_RI2/BU4_RXD"),
1635 PINCTRL_PIN(56, "GPIO56/R1_RXERR/R1_OEN"),
1636 PINCTRL_PIN(57, "GPIO57/R1_MDC/TP_GPIO4"),
1637 PINCTRL_PIN(58, "GPIO58/R1_MDIO/TP_GPIO5"),
1638 PINCTRL_PIN(59, "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA"),
1639 PINCTRL_PIN(60, "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL"),
1640 PINCTRL_PIN(61, "GPIO61/SI1_nDTR_BOUT"),
1641 PINCTRL_PIN(62, "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO"),
1642 PINCTRL_PIN(63, "GPIO63/BU1_TXD1/SI1_TXD"),
1643 PINCTRL_PIN(64, "GPIO64/FANIN0"),
1644 PINCTRL_PIN(65, "GPIO65/FANIN1"),
1645 PINCTRL_PIN(66, "GPIO66/FANIN2"),
1646 PINCTRL_PIN(67, "GPIO67/FANIN3"),
1647 PINCTRL_PIN(68, "GPIO68/FANIN4"),
1648 PINCTRL_PIN(69, "GPIO69/FANIN5"),
1649 PINCTRL_PIN(70, "GPIO70/FANIN6"),
1650 PINCTRL_PIN(71, "GPIO71/FANIN7"),
1651 PINCTRL_PIN(72, "GPIO72/FANIN8"),
1652 PINCTRL_PIN(73, "GPIO73/FANIN9"),
1653 PINCTRL_PIN(74, "GPIO74/FANIN10"),
1654 PINCTRL_PIN(75, "GPIO75/FANIN11"),
1655 PINCTRL_PIN(76, "GPIO76/FANIN12"),
1656 PINCTRL_PIN(77, "GPIO77/FANIN13"),
1657 PINCTRL_PIN(78, "GPIO78/FANIN14"),
1658 PINCTRL_PIN(79, "GPIO79/FANIN15"),
1659 PINCTRL_PIN(80, "GPIO80/PWM0"),
1660 PINCTRL_PIN(81, "GPIO81/PWM1"),
1661 PINCTRL_PIN(82, "GPIO82/PWM2"),
1662 PINCTRL_PIN(83, "GPIO83/PWM3"),
1663 PINCTRL_PIN(84, "GPIO84/R2_TXD0"),
1664 PINCTRL_PIN(85, "GPIO85/R2_TXD1"),
1665 PINCTRL_PIN(86, "GPIO86/R2_TXEN"),
1666 PINCTRL_PIN(87, "GPIO87/R2_RXD0"),
1667 PINCTRL_PIN(88, "GPIO88/R2_RXD1"),
1668 PINCTRL_PIN(89, "GPIO89/R2_CRSDV"),
1669 PINCTRL_PIN(90, "GPIO90/R2_RXERR/R2_OEN"),
1670 PINCTRL_PIN(91, "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0"),
1671 PINCTRL_PIN(92, "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1"),
1672 PINCTRL_PIN(93, "GPIO93/GA20/SMB5D_SCL"),
1673 PINCTRL_PIN(94, "GPIO94/nKBRST/SMB5D_SDA"),
1674 PINCTRL_PIN(95, "GPIO95/nESPIRST/LPC_nLRESET"),
1675 PINCTRL_PIN(96, "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7"),
1676 PINCTRL_PIN(97, "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6"),
1677 PINCTRL_PIN(98, "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5"),
1678 PINCTRL_PIN(99, "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4"),
1679 PINCTRL_PIN(100, "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3"),
1680 PINCTRL_PIN(101, "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2"),
1681 PINCTRL_PIN(102, "GPIO102/HSYNC"),
1682 PINCTRL_PIN(103, "GPIO103/VSYNC"),
1683 PINCTRL_PIN(104, "GPIO104/DDC_SCL"),
1684 PINCTRL_PIN(105, "GPIO105/DDC_SDA"),
1685 PINCTRL_PIN(106, "GPIO106/I3C5_SCL"),
1686 PINCTRL_PIN(107, "GPIO107/I3C5_SDA"),
1687 PINCTRL_PIN(108, "GPIO108/SG1_MDC"),
1688 PINCTRL_PIN(109, "GPIO109/SG1_MDIO"),
1689 PINCTRL_PIN(110, "GPIO110/RG2_TXD0/DDRV0/R3_TXD0"),
1690 PINCTRL_PIN(111, "GPIO111/RG2_TXD1/DDRV1/R3_TXD1"),
1691 PINCTRL_PIN(112, "GPIO112/RG2_TXD2/DDRV2"),
1692 PINCTRL_PIN(113, "GPIO113/RG2_TXD3/DDRV3"),
1693 PINCTRL_PIN(114, "GPIO114/SMB0_SCL"),
1694 PINCTRL_PIN(115, "GPIO115/SMB0_SDA"),
1695 PINCTRL_PIN(116, "GPIO116/SMB1_SCL"),
1696 PINCTRL_PIN(117, "GPIO117/SMB1_SDA"),
1697 PINCTRL_PIN(118, "GPIO118/SMB2_SCL"),
1698 PINCTRL_PIN(119, "GPIO119/SMB2_SDA"),
1699 PINCTRL_PIN(120, "GPIO120/SMB2C_SDA"),
1700 PINCTRL_PIN(121, "GPIO121/SMB2C_SCL"),
1701 PINCTRL_PIN(122, "GPIO122/SMB2B_SDA"),
1702 PINCTRL_PIN(123, "GPIO123/SMB2B_SCL"),
1703 PINCTRL_PIN(124, "GPIO124/SMB1C_SDA/CP1_GPIO3"),
1704 PINCTRL_PIN(125, "GPIO125/SMB1C_SCL/CP1_GPIO2"),
1705 PINCTRL_PIN(126, "GPIO126/SMB1B_SDA/CP1_GPIO1"),
1706 PINCTRL_PIN(127, "GPIO127/SMB1B_SCL/CP1_GPIO0"),
1707 PINCTRL_PIN(128, "GPIO128/SMB824_SCL"),
1708 PINCTRL_PIN(129, "GPIO129/SMB824_SDA"),
1709 PINCTRL_PIN(130, "GPIO130/SMB925_SCL"),
1710 PINCTRL_PIN(131, "GPIO131/SMB925_SDA"),
1711 PINCTRL_PIN(132, "GPIO132/SMB1026_SCL"),
1712 PINCTRL_PIN(133, "GPIO133/SMB1026_SDA"),
1713 PINCTRL_PIN(134, "GPIO134/SMB11_SCL/SMB23B_SCL"),
1714 PINCTRL_PIN(135, "GPIO135/SMB11_SDA/SMB23B_SDA"),
1715 PINCTRL_PIN(136, "GPIO136/JM1_TCK"),
1716 PINCTRL_PIN(137, "GPIO137/JM1_TDO"),
1717 PINCTRL_PIN(138, "GPIO138/JM1_TMS"),
1718 PINCTRL_PIN(139, "GPIO139/JM1_TDI"),
1719 PINCTRL_PIN(140, "GPIO140/JM1_nTRST"),
1720 PINCTRL_PIN(141, "GPIO141/SMB7B_SCL"),
1721 PINCTRL_PIN(142, "GPIO142/SMB7D_SCL/TPSMB1_SCL"),
1722 PINCTRL_PIN(143, "GPIO143/SMB7D_SDA/TPSMB1_SDA"),
1723 PINCTRL_PIN(144, "GPIO144/PWM4"),
1724 PINCTRL_PIN(145, "GPIO145/PWM5"),
1725 PINCTRL_PIN(146, "GPIO146/PWM6"),
1726 PINCTRL_PIN(147, "GPIO147/PWM7"),
1727 PINCTRL_PIN(148, "GPIO148/MMC_DT4"),
1728 PINCTRL_PIN(149, "GPIO149/MMC_DT5"),
1729 PINCTRL_PIN(150, "GPIO150/MMC_DT6"),
1730 PINCTRL_PIN(151, "GPIO151/MMC_DT7"),
1731 PINCTRL_PIN(152, "GPIO152/MMC_CLK"),
1732 PINCTRL_PIN(153, "GPIO153/MMC_WP"),
1733 PINCTRL_PIN(154, "GPIO154/MMC_CMD"),
1734 PINCTRL_PIN(155, "GPIO155/MMC_nCD/MMC_nRSTLK"),
1735 PINCTRL_PIN(156, "GPIO156/MMC_DT0"),
1736 PINCTRL_PIN(157, "GPIO157/MMC_DT1"),
1737 PINCTRL_PIN(158, "GPIO158/MMC_DT2"),
1738 PINCTRL_PIN(159, "GPIO159/MMC_DT3"),
1739 PINCTRL_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK"),
1740 PINCTRL_PIN(161, "GPIO161/ESPI_nCS/LPC_nLFRAME"),
1741 PINCTRL_PIN(162, "GPIO162/SERIRQ"),
1742 PINCTRL_PIN(163, "GPIO163/ESPI_CK/LPC_LCLK"),
1743 PINCTRL_PIN(164, "GPIO164/ESPI_IO0/LPC_LAD0"),
1744 PINCTRL_PIN(165, "GPIO165/ESPI_IO1/LPC_LAD1"),
1745 PINCTRL_PIN(166, "GPIO166/ESPI_IO2/LPC_LAD2"),
1746 PINCTRL_PIN(167, "GPIO167/ESPI_IO3/LPC_LAD3"),
1747 PINCTRL_PIN(168, "GPIO168/ESPI_nALERT/LPC_nCLKRUN"),
1748 PINCTRL_PIN(169, "GPIO169/nSCIPME/SMB21_SCL"),
1749 PINCTRL_PIN(170, "GPIO170/nSMI/SMB21_SDA"),
1750 PINCTRL_PIN(171, "GPIO171/SMB6_SCL"),
1751 PINCTRL_PIN(172, "GPIO172/SMB6_SDA"),
1752 PINCTRL_PIN(173, "GPIO173/SMB7_SCL"),
1753 PINCTRL_PIN(174, "GPIO174/SMB7_SDA"),
1754 PINCTRL_PIN(175, "GPIO175/SPI1_CK/FANIN19/FM1_CK"),
1755 PINCTRL_PIN(176, "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9"),
1756 PINCTRL_PIN(177, "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10"),
1757 PINCTRL_PIN(178, "GPIO178/R1_TXD0"),
1758 PINCTRL_PIN(179, "GPIO179/R1_TXD1"),
1759 PINCTRL_PIN(180, "GPIO180/R1_TXEN"),
1760 PINCTRL_PIN(181, "GPIO181/R1_RXD0"),
1761 PINCTRL_PIN(182, "GPIO182/R1_RXD1"),
1762 PINCTRL_PIN(183, "GPIO183/SPI3_SEL"),
1763 PINCTRL_PIN(184, "GPIO184/SPI3_D0/STRAP13"),
1764 PINCTRL_PIN(185, "GPIO185/SPI3_D1"),
1765 PINCTRL_PIN(186, "GPIO186/SPI3_nCS0"),
1766 PINCTRL_PIN(187, "GPO187/SPI3_nCS1_SMB14B_SDA"),
1767 PINCTRL_PIN(188, "GPIO188/SPI3_D2/SPI3_nCS2"),
1768 PINCTRL_PIN(189, "GPIO189/SPI3_D3/SPI3_nCS3"),
1769 PINCTRL_PIN(190, "GPIO190/nPRD_SMI"),
1770 PINCTRL_PIN(191, "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10"),
1771 PINCTRL_PIN(192, "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL"),
1772 PINCTRL_PIN(193, "GPIO193/R1_CRSDV"),
1773 PINCTRL_PIN(194, "GPIO194/SMB0B_SCL/FM0_CK"),
1774 PINCTRL_PIN(195, "GPIO195/SMB0B_SDA/FM0_D0"),
1775 PINCTRL_PIN(196, "GPIO196/SMB0C_SCL/FM0_D1"),
1776 PINCTRL_PIN(197, "GPIO197/SMB0DEN/FM0_D3"),
1777 PINCTRL_PIN(198, "GPIO198/SMB0D_SDA/FM0_D2"),
1778 PINCTRL_PIN(199, "GPIO199/SMB0D_SCL/FM0_CSO"),
1779 PINCTRL_PIN(200, "GPIO200/R2_CK"),
1780 PINCTRL_PIN(201, "GPIO201/R1_CK"),
1781 PINCTRL_PIN(202, "GPIO202/SMB0C_SDA/FM0_CSI"),
1782 PINCTRL_PIN(203, "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI"),
1783 PINCTRL_PIN(208, "GPIO208/RG2_TXC/DVCK"),
1784 PINCTRL_PIN(209, "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN"),
1785 PINCTRL_PIN(210, "GPIO210/RG2_RXD0/DDRV5/R3_RXD0"),
1786 PINCTRL_PIN(211, "GPIO211/RG2_RXD1/DDRV6/R3_RXD1"),
1787 PINCTRL_PIN(212, "GPIO212/RG2_RXD2/DDRV7/R3_RXD2"),
1788 PINCTRL_PIN(213, "GPIO213/RG2_RXD3/DDRV8/R3_OEN"),
1789 PINCTRL_PIN(214, "GPIO214/RG2_RXC/DDRV9/R3_CK"),
1790 PINCTRL_PIN(215, "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV"),
1791 PINCTRL_PIN(216, "GPIO216/RG2_MDC/DDRV11"),
1792 PINCTRL_PIN(217, "GPIO217/RG2_MDIO/DVHSYNC"),
1793 PINCTRL_PIN(218, "GPIO218/nWDO1/SMB16_SCL"),
1794 PINCTRL_PIN(219, "GPIO219/nWDO2/SMB16_SDA"),
1795 PINCTRL_PIN(220, "GPIO220/SMB12_SCL/PWM8"),
1796 PINCTRL_PIN(221, "GPIO221/SMB12_SDA/PWM9"),
1797 PINCTRL_PIN(222, "GPIO222/SMB13_SCL"),
1798 PINCTRL_PIN(223, "GPIO223/SMB13_SDA"),
1799 PINCTRL_PIN(224, "GPIO224/SPIX_CK/FM2_CK"),
1800 PINCTRL_PIN(225, "GPO225/SPIX_D0/FM2_D0/STRAP1"),
1801 PINCTRL_PIN(226, "GPO226/SPIX_D1/FM2_D1/STRAP2"),
1802 PINCTRL_PIN(227, "GPIO227/SPIX_nCS0/FM2_CSI"),
1803 PINCTRL_PIN(228, "GPIO228/SPIX_nCS1/FM2_CSO"),
1804 PINCTRL_PIN(229, "GPO229/SPIX_D2/FM2_D2/STRAP3"),
1805 PINCTRL_PIN(230, "GPO230/SPIX_D3/FM2_D3/STRAP6"),
1806 PINCTRL_PIN(231, "GPIO231/EP_nCLKREQ"),
1807 PINCTRL_PIN(233, "GPIO233/SPI1_nCS1/FM1_CSO"),
1808 PINCTRL_PIN(234, "GPIO234/PWM10/SMB20_SCL"),
1809 PINCTRL_PIN(235, "GPIO235/PWM11/SMB20_SDA"),
1810 PINCTRL_PIN(240, "GPIO240/I3C0_SCL"),
1811 PINCTRL_PIN(241, "GPIO241/I3C0_SDA"),
1812 PINCTRL_PIN(242, "GPIO242/I3C1_SCL"),
1813 PINCTRL_PIN(243, "GPIO243/I3C1_SDA"),
1814 PINCTRL_PIN(244, "GPIO244/I3C2_SCL"),
1815 PINCTRL_PIN(245, "GPIO245/I3C2_SDA"),
1816 PINCTRL_PIN(246, "GPIO246/I3C3_SCL"),
1817 PINCTRL_PIN(247, "GPIO247/I3C3_SDA"),
1818 PINCTRL_PIN(250, "GPIO250/RG2_REFCK/DVVSYNC"),
1819 PINCTRL_PIN(251, "JM2/CP1_GPIO"),
1820 };
1821
npcm8xx_rmii_output_enable_mask(unsigned int pin)1822 static u32 npcm8xx_rmii_output_enable_mask(unsigned int pin)
1823 {
1824 switch (pin) {
1825 case 178:
1826 case 179:
1827 case 180:
1828 case 181:
1829 case 182:
1830 case 193:
1831 case 201:
1832 return NPCM8XX_INTCR4_R1_RMII_EN;
1833 case 84:
1834 case 85:
1835 case 86:
1836 case 87:
1837 case 88:
1838 case 89:
1839 case 200:
1840 return NPCM8XX_INTCR4_R2_RMII_EN;
1841 case 110:
1842 case 111:
1843 case 209:
1844 case 210:
1845 case 211:
1846 case 214:
1847 case 215:
1848 return NPCM8XX_INTCR4_RMII3_EN;
1849 default:
1850 return 0;
1851 }
1852 }
1853
npcm8xx_set_rmii_output_enable(struct regmap * gcr_regmap,const unsigned int * pin,int pin_number,int mode)1854 static void npcm8xx_set_rmii_output_enable(struct regmap *gcr_regmap,
1855 const unsigned int *pin,
1856 int pin_number, int mode)
1857 {
1858 u32 mask = 0;
1859 u32 val = 0;
1860 u32 bit;
1861 int i;
1862
1863 for (i = 0; i < pin_number; i++) {
1864 bit = npcm8xx_rmii_output_enable_mask(pin[i]);
1865 mask |= bit;
1866
1867 if ((mode == fn_r1 && bit == NPCM8XX_INTCR4_R1_RMII_EN) ||
1868 (mode == fn_r2 && bit == NPCM8XX_INTCR4_R2_RMII_EN) ||
1869 (mode == fn_rmii3 && bit == NPCM8XX_INTCR4_RMII3_EN))
1870 val |= bit;
1871 }
1872
1873 if (mask)
1874 regmap_update_bits(gcr_regmap, NPCM8XX_GCR_INTCR4, mask, val);
1875 }
1876
1877 /* Enable mode in pin group */
npcm8xx_setfunc(struct regmap * gcr_regmap,const unsigned int * pin,int pin_number,int mode)1878 static void npcm8xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
1879 int pin_number, int mode)
1880 {
1881 const struct npcm8xx_pincfg *cfg;
1882 int i;
1883
1884 for (i = 0 ; i < pin_number ; i++) {
1885 cfg = &pincfg[pin[i]];
1886 if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode ||
1887 cfg->fn2 == mode || cfg->fn3 == mode || cfg->fn4 == mode) {
1888 if (cfg->reg0)
1889 regmap_update_bits(gcr_regmap, cfg->reg0,
1890 BIT(cfg->bit0),
1891 (cfg->fn0 == mode) ?
1892 BIT(cfg->bit0) : 0);
1893 if (cfg->reg1)
1894 regmap_update_bits(gcr_regmap, cfg->reg1,
1895 BIT(cfg->bit1),
1896 (cfg->fn1 == mode) ?
1897 BIT(cfg->bit1) : 0);
1898 if (cfg->reg2)
1899 regmap_update_bits(gcr_regmap, cfg->reg2,
1900 BIT(cfg->bit2),
1901 (cfg->fn2 == mode) ?
1902 BIT(cfg->bit2) : 0);
1903 if (cfg->reg3)
1904 regmap_update_bits(gcr_regmap, cfg->reg3,
1905 BIT(cfg->bit3),
1906 (cfg->fn3 == mode) ?
1907 BIT(cfg->bit3) : 0);
1908 if (cfg->reg4)
1909 regmap_update_bits(gcr_regmap, cfg->reg4,
1910 BIT(cfg->bit4),
1911 (cfg->fn4 == mode) ?
1912 BIT(cfg->bit4) : 0);
1913 }
1914 }
1915
1916 npcm8xx_set_rmii_output_enable(gcr_regmap, pin, pin_number, mode);
1917 }
1918
npcm8xx_get_slew_rate(struct npcm8xx_gpio * bank,struct regmap * gcr_regmap,unsigned int pin)1919 static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank,
1920 struct regmap *gcr_regmap, unsigned int pin)
1921 {
1922 int gpio = pin % bank->chip.gc.ngpio;
1923 unsigned long pinmask = BIT(gpio);
1924 u32 val;
1925
1926 if (pincfg[pin].flag & SLEW)
1927 return ioread32(bank->base + NPCM8XX_GP_N_OSRC) & pinmask;
1928 /* LPC Slew rate in SRCNT register */
1929 if (pincfg[pin].flag & SLEWLPC) {
1930 regmap_read(gcr_regmap, NPCM8XX_GCR_SRCNT, &val);
1931 return !!(val & SRCNT_ESPI);
1932 }
1933
1934 return -EINVAL;
1935 }
1936
npcm8xx_set_slew_rate(struct npcm8xx_gpio * bank,struct regmap * gcr_regmap,unsigned int pin,int arg)1937 static int npcm8xx_set_slew_rate(struct npcm8xx_gpio *bank,
1938 struct regmap *gcr_regmap, unsigned int pin,
1939 int arg)
1940 {
1941 void __iomem *OSRC_Offset = bank->base + NPCM8XX_GP_N_OSRC;
1942 int gpio = BIT(pin % bank->chip.gc.ngpio);
1943
1944 if (pincfg[pin].flag & SLEW) {
1945 switch (arg) {
1946 case 0:
1947 npcm_gpio_clr(&bank->chip, OSRC_Offset, gpio);
1948 return 0;
1949 case 1:
1950 npcm_gpio_set(&bank->chip, OSRC_Offset, gpio);
1951 return 0;
1952 default:
1953 return -EINVAL;
1954 }
1955 }
1956
1957 if (!(pincfg[pin].flag & SLEWLPC))
1958 return -EINVAL;
1959
1960 switch (arg) {
1961 case 0:
1962 regmap_update_bits(gcr_regmap, NPCM8XX_GCR_SRCNT,
1963 SRCNT_ESPI, 0);
1964 break;
1965 case 1:
1966 regmap_update_bits(gcr_regmap, NPCM8XX_GCR_SRCNT,
1967 SRCNT_ESPI, SRCNT_ESPI);
1968 break;
1969 default:
1970 return -EINVAL;
1971 }
1972
1973 return 0;
1974 }
1975
npcm8xx_get_rg2_drive_strength(struct npcm8xx_pinctrl * npcm)1976 static int npcm8xx_get_rg2_drive_strength(struct npcm8xx_pinctrl *npcm)
1977 {
1978 u32 val;
1979 int ret;
1980
1981 ret = regmap_read(npcm->gcr_regmap, NPCM8XX_GCR_DSCNT, &val);
1982 if (ret)
1983 return ret;
1984
1985 switch ((val & NPCM8XX_GCR_DSCNT_RG2DS_MASK) >>
1986 NPCM8XX_GCR_DSCNT_RG2DS_SHIFT) {
1987 case 0:
1988 return 8;
1989 case 1:
1990 return 12;
1991 case 2:
1992 return 16;
1993 case 3:
1994 return 24;
1995 default:
1996 return -EINVAL;
1997 }
1998 }
1999
npcm8xx_set_rg2_drive_strength(struct npcm8xx_pinctrl * npcm,int nval)2000 static int npcm8xx_set_rg2_drive_strength(struct npcm8xx_pinctrl *npcm, int nval)
2001 {
2002 u32 val;
2003
2004 switch (nval) {
2005 case 8:
2006 val = 0;
2007 break;
2008 case 12:
2009 val = 1;
2010 break;
2011 case 16:
2012 val = 2;
2013 break;
2014 case 24:
2015 val = 3;
2016 break;
2017 default:
2018 return -EOPNOTSUPP;
2019 }
2020
2021 return regmap_update_bits(npcm->gcr_regmap, NPCM8XX_GCR_DSCNT,
2022 NPCM8XX_GCR_DSCNT_RG2DS_MASK,
2023 val << NPCM8XX_GCR_DSCNT_RG2DS_SHIFT);
2024 }
2025
npcm8xx_get_drive_strength(struct pinctrl_dev * pctldev,unsigned int pin)2026 static int npcm8xx_get_drive_strength(struct pinctrl_dev *pctldev,
2027 unsigned int pin)
2028 {
2029 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2030 struct npcm8xx_gpio *bank =
2031 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
2032 int gpio = pin % bank->chip.gc.ngpio;
2033 unsigned long pinmask = BIT(gpio);
2034 int flg, ds;
2035 u32 val;
2036
2037 flg = pincfg[pin].flag;
2038 if (flg & DSTR_RG2)
2039 return npcm8xx_get_rg2_drive_strength(npcm);
2040
2041 if (!(flg & DRIVE_STRENGTH_MASK))
2042 return -EINVAL;
2043
2044 val = ioread32(bank->base + NPCM8XX_GP_N_ODSC) & pinmask;
2045 ds = val ? DSHI(flg) : DSLO(flg);
2046 dev_dbg(bank->chip.gc.parent, "pin %d strength %d = %d\n", pin, val, ds);
2047
2048 return ds;
2049 }
2050
npcm8xx_set_drive_strength(struct npcm8xx_pinctrl * npcm,unsigned int pin,int nval)2051 static int npcm8xx_set_drive_strength(struct npcm8xx_pinctrl *npcm,
2052 unsigned int pin, int nval)
2053 {
2054 struct npcm8xx_gpio *bank =
2055 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
2056 int gpio = BIT(pin % bank->chip.gc.ngpio);
2057 int v;
2058
2059 if (pincfg[pin].flag & DSTR_RG2)
2060 return npcm8xx_set_rg2_drive_strength(npcm, nval);
2061
2062 v = pincfg[pin].flag & DRIVE_STRENGTH_MASK;
2063
2064 if (DSLO(v) == nval)
2065 npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_ODSC, gpio);
2066 else if (DSHI(v) == nval)
2067 npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_ODSC, gpio);
2068 else
2069 return -ENOTSUPP;
2070
2071 return 0;
2072 }
2073
2074 /* pinctrl_ops */
npcm8xx_get_groups_count(struct pinctrl_dev * pctldev)2075 static int npcm8xx_get_groups_count(struct pinctrl_dev *pctldev)
2076 {
2077 return ARRAY_SIZE(npcm8xx_pingroups);
2078 }
2079
npcm8xx_get_group_name(struct pinctrl_dev * pctldev,unsigned int selector)2080 static const char *npcm8xx_get_group_name(struct pinctrl_dev *pctldev,
2081 unsigned int selector)
2082 {
2083 return npcm8xx_pingroups[selector].name;
2084 }
2085
npcm8xx_get_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * npins)2086 static int npcm8xx_get_group_pins(struct pinctrl_dev *pctldev,
2087 unsigned int selector,
2088 const unsigned int **pins,
2089 unsigned int *npins)
2090 {
2091 *npins = npcm8xx_pingroups[selector].npins;
2092 *pins = npcm8xx_pingroups[selector].pins;
2093
2094 return 0;
2095 }
2096
npcm8xx_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np_config,struct pinctrl_map ** map,u32 * num_maps)2097 static int npcm8xx_dt_node_to_map(struct pinctrl_dev *pctldev,
2098 struct device_node *np_config,
2099 struct pinctrl_map **map,
2100 u32 *num_maps)
2101 {
2102 return pinconf_generic_dt_node_to_map(pctldev, np_config,
2103 map, num_maps,
2104 PIN_MAP_TYPE_INVALID);
2105 }
2106
npcm8xx_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,u32 num_maps)2107 static void npcm8xx_dt_free_map(struct pinctrl_dev *pctldev,
2108 struct pinctrl_map *map, u32 num_maps)
2109 {
2110 kfree(map);
2111 }
2112
2113 static const struct pinctrl_ops npcm8xx_pinctrl_ops = {
2114 .get_groups_count = npcm8xx_get_groups_count,
2115 .get_group_name = npcm8xx_get_group_name,
2116 .get_group_pins = npcm8xx_get_group_pins,
2117 .dt_node_to_map = npcm8xx_dt_node_to_map,
2118 .dt_free_map = npcm8xx_dt_free_map,
2119 };
2120
npcm8xx_get_functions_count(struct pinctrl_dev * pctldev)2121 static int npcm8xx_get_functions_count(struct pinctrl_dev *pctldev)
2122 {
2123 return ARRAY_SIZE(npcm8xx_funcs);
2124 }
2125
npcm8xx_get_function_name(struct pinctrl_dev * pctldev,unsigned int function)2126 static const char *npcm8xx_get_function_name(struct pinctrl_dev *pctldev,
2127 unsigned int function)
2128 {
2129 return npcm8xx_funcs[function].name;
2130 }
2131
npcm8xx_get_function_groups(struct pinctrl_dev * pctldev,unsigned int function,const char * const ** groups,unsigned int * const ngroups)2132 static int npcm8xx_get_function_groups(struct pinctrl_dev *pctldev,
2133 unsigned int function,
2134 const char * const **groups,
2135 unsigned int * const ngroups)
2136 {
2137 *ngroups = npcm8xx_funcs[function].ngroups;
2138 *groups = npcm8xx_funcs[function].groups;
2139
2140 return 0;
2141 }
2142
npcm8xx_pinmux_set_mux(struct pinctrl_dev * pctldev,unsigned int function,unsigned int group)2143 static int npcm8xx_pinmux_set_mux(struct pinctrl_dev *pctldev,
2144 unsigned int function,
2145 unsigned int group)
2146 {
2147 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2148
2149 npcm8xx_setfunc(npcm->gcr_regmap, npcm8xx_pingroups[group].pins,
2150 npcm8xx_pingroups[group].npins, group);
2151
2152 return 0;
2153 }
2154
npcm8xx_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)2155 static int npcm8xx_gpio_request_enable(struct pinctrl_dev *pctldev,
2156 struct pinctrl_gpio_range *range,
2157 unsigned int offset)
2158 {
2159 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2160 const unsigned int *pin = &offset;
2161 int mode = fn_gpio;
2162
2163 if ((pin[0] >= 183 && pin[0] <= 189) || pin[0] == 35 || pin[0] == 36)
2164 mode = pincfg[pin[0]].fn0;
2165
2166 npcm8xx_setfunc(npcm->gcr_regmap, &offset, 1, mode);
2167
2168 return 0;
2169 }
2170
npcm8xx_gpio_request_free(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)2171 static void npcm8xx_gpio_request_free(struct pinctrl_dev *pctldev,
2172 struct pinctrl_gpio_range *range,
2173 unsigned int offset)
2174 {
2175 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2176 int virq;
2177
2178 virq = irq_find_mapping(npcm->domain, offset);
2179 if (virq)
2180 irq_dispose_mapping(virq);
2181 }
2182
npcm_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset,bool input)2183 static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev,
2184 struct pinctrl_gpio_range *range,
2185 unsigned int offset, bool input)
2186 {
2187 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2188 struct npcm8xx_gpio *bank =
2189 &npcm->gpio_bank[offset / NPCM8XX_GPIO_PER_BANK];
2190 int gpio = BIT(offset % bank->chip.gc.ngpio);
2191
2192 if (input)
2193 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);
2194 else
2195 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);
2196
2197 return 0;
2198 }
2199
2200 static const struct pinmux_ops npcm8xx_pinmux_ops = {
2201 .get_functions_count = npcm8xx_get_functions_count,
2202 .get_function_name = npcm8xx_get_function_name,
2203 .get_function_groups = npcm8xx_get_function_groups,
2204 .set_mux = npcm8xx_pinmux_set_mux,
2205 .gpio_request_enable = npcm8xx_gpio_request_enable,
2206 .gpio_disable_free = npcm8xx_gpio_request_free,
2207 .gpio_set_direction = npcm_gpio_set_direction,
2208 };
2209
debounce_timing_setting(struct npcm8xx_gpio * bank,u32 gpio,u32 nanosecs)2210 static int debounce_timing_setting(struct npcm8xx_gpio *bank, u32 gpio,
2211 u32 nanosecs)
2212 {
2213 void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 +
2214 (gpio / 16) * 4;
2215 int gpio_debounce = (gpio % 16) * 2, debounce_select, i;
2216 u32 dbncp_val, dbncp_val_mod;
2217
2218 for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++) {
2219 if (bank->debounce.set_val[i]) {
2220 if (bank->debounce.nanosec_val[i] == nanosecs) {
2221 debounce_select = i << gpio_debounce;
2222 npcm_gpio_set(&bank->chip, DBNCS_offset,
2223 debounce_select);
2224 break;
2225 }
2226 } else {
2227 bank->debounce.set_val[i] = true;
2228 bank->debounce.nanosec_val[i] = nanosecs;
2229 debounce_select = i << gpio_debounce;
2230 npcm_gpio_set(&bank->chip, DBNCS_offset, debounce_select);
2231 switch (nanosecs) {
2232 case 1 ... 1040:
2233 iowrite32(0, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2234 break;
2235 case 1041 ... 1640:
2236 iowrite32(0x10, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2237 break;
2238 case 1641 ... 2280:
2239 iowrite32(0x20, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2240 break;
2241 case 2281 ... 2700:
2242 iowrite32(0x30, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2243 break;
2244 case 2701 ... 2856:
2245 iowrite32(0x40, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2246 break;
2247 case 2857 ... 3496:
2248 iowrite32(0x50, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2249 break;
2250 case 3497 ... 4136:
2251 iowrite32(0x60, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2252 break;
2253 case 4137 ... 5025:
2254 iowrite32(0x70, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2255 break;
2256 default:
2257 dbncp_val = DIV_ROUND_CLOSEST(nanosecs, NPCM8XX_DEBOUNCE_NSEC);
2258 if (dbncp_val > NPCM8XX_DEBOUNCE_MAX_VAL)
2259 return -ENOTSUPP;
2260 dbncp_val_mod = dbncp_val & GENMASK(3, 0);
2261 if (dbncp_val_mod > GENMASK(2, 0))
2262 dbncp_val += 0x10;
2263 iowrite32(dbncp_val & NPCM8XX_DEBOUNCE_VAL_MASK,
2264 bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2265 break;
2266 }
2267 break;
2268 }
2269 }
2270
2271 if (i == 4)
2272 return -ENOTSUPP;
2273
2274 return 0;
2275 }
2276
npcm_set_debounce(struct npcm8xx_pinctrl * npcm,unsigned int pin,u32 nanosecs)2277 static int npcm_set_debounce(struct npcm8xx_pinctrl *npcm, unsigned int pin,
2278 u32 nanosecs)
2279 {
2280 struct npcm8xx_gpio *bank =
2281 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
2282 int gpio = BIT(pin % bank->chip.gc.ngpio);
2283 int ret;
2284
2285 if (nanosecs) {
2286 ret = debounce_timing_setting(bank, pin % bank->chip.gc.ngpio,
2287 nanosecs);
2288 if (ret)
2289 dev_err(npcm->dev, "Pin %d, All four debounce timing values are used, please use one of exist debounce values\n", pin);
2290 else
2291 npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_DBNC,
2292 gpio);
2293 return ret;
2294 }
2295
2296 npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_DBNC, gpio);
2297
2298 return 0;
2299 }
2300
2301 /* pinconf_ops */
npcm8xx_config_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)2302 static int npcm8xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
2303 unsigned long *config)
2304 {
2305 enum pin_config_param param = pinconf_to_config_param(*config);
2306 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2307 struct npcm8xx_gpio *bank =
2308 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
2309 int gpio = pin % bank->chip.gc.ngpio;
2310 unsigned long pinmask = BIT(gpio);
2311 u32 ie, oe, pu, pd;
2312 int rc = 0;
2313
2314 switch (param) {
2315 case PIN_CONFIG_BIAS_DISABLE:
2316 case PIN_CONFIG_BIAS_PULL_UP:
2317 case PIN_CONFIG_BIAS_PULL_DOWN:
2318 pu = ioread32(bank->base + NPCM8XX_GP_N_PU) & pinmask;
2319 pd = ioread32(bank->base + NPCM8XX_GP_N_PD) & pinmask;
2320 if (param == PIN_CONFIG_BIAS_DISABLE)
2321 rc = !pu && !pd;
2322 else if (param == PIN_CONFIG_BIAS_PULL_UP)
2323 rc = pu && !pd;
2324 else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
2325 rc = !pu && pd;
2326 break;
2327 case PIN_CONFIG_LEVEL:
2328 case PIN_CONFIG_INPUT_ENABLE:
2329 ie = ioread32(bank->base + NPCM8XX_GP_N_IEM) & pinmask;
2330 oe = ioread32(bank->base + NPCM8XX_GP_N_OE) & pinmask;
2331 if (param == PIN_CONFIG_INPUT_ENABLE)
2332 rc = (ie && !oe);
2333 else if (param == PIN_CONFIG_LEVEL)
2334 rc = (!ie && oe);
2335 break;
2336 case PIN_CONFIG_DRIVE_PUSH_PULL:
2337 rc = !(ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask);
2338 break;
2339 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
2340 rc = ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask;
2341 break;
2342 case PIN_CONFIG_INPUT_DEBOUNCE:
2343 rc = ioread32(bank->base + NPCM8XX_GP_N_DBNC) & pinmask;
2344 break;
2345 case PIN_CONFIG_DRIVE_STRENGTH:
2346 rc = npcm8xx_get_drive_strength(pctldev, pin);
2347 if (rc)
2348 *config = pinconf_to_config_packed(param, rc);
2349 break;
2350 case PIN_CONFIG_SLEW_RATE:
2351 rc = npcm8xx_get_slew_rate(bank, npcm->gcr_regmap, pin);
2352 if (rc >= 0)
2353 *config = pinconf_to_config_packed(param, rc);
2354 break;
2355 default:
2356 return -ENOTSUPP;
2357 }
2358
2359 if (!rc)
2360 return -EINVAL;
2361
2362 return 0;
2363 }
2364
npcm8xx_config_set_one(struct npcm8xx_pinctrl * npcm,unsigned int pin,unsigned long config)2365 static int npcm8xx_config_set_one(struct npcm8xx_pinctrl *npcm,
2366 unsigned int pin, unsigned long config)
2367 {
2368 enum pin_config_param param = pinconf_to_config_param(config);
2369 struct npcm8xx_gpio *bank =
2370 &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
2371 u32 arg = pinconf_to_config_argument(config);
2372 int gpio = BIT(pin % bank->chip.gc.ngpio);
2373
2374 switch (param) {
2375 case PIN_CONFIG_BIAS_DISABLE:
2376 npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio);
2377 npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio);
2378 break;
2379 case PIN_CONFIG_BIAS_PULL_DOWN:
2380 npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio);
2381 npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio);
2382 break;
2383 case PIN_CONFIG_BIAS_PULL_UP:
2384 npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio);
2385 npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio);
2386 break;
2387 case PIN_CONFIG_INPUT_ENABLE:
2388 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);
2389 bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio);
2390 break;
2391 case PIN_CONFIG_LEVEL:
2392 bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg);
2393 iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);
2394 break;
2395 case PIN_CONFIG_DRIVE_PUSH_PULL:
2396 npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_OTYP, gpio);
2397 break;
2398 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
2399 npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_OTYP, gpio);
2400 break;
2401 case PIN_CONFIG_INPUT_DEBOUNCE:
2402 return npcm_set_debounce(npcm, pin, arg * 1000);
2403 case PIN_CONFIG_SLEW_RATE:
2404 return npcm8xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg);
2405 case PIN_CONFIG_DRIVE_STRENGTH:
2406 return npcm8xx_set_drive_strength(npcm, pin, arg);
2407 default:
2408 return -ENOTSUPP;
2409 }
2410
2411 return 0;
2412 }
2413
npcm8xx_config_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)2414 static int npcm8xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
2415 unsigned long *configs, unsigned int num_configs)
2416 {
2417 struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2418 int rc;
2419
2420 while (num_configs--) {
2421 rc = npcm8xx_config_set_one(npcm, pin, *configs++);
2422 if (rc)
2423 return rc;
2424 }
2425
2426 return 0;
2427 }
2428
2429 static const struct pinconf_ops npcm8xx_pinconf_ops = {
2430 .is_generic = true,
2431 .pin_config_get = npcm8xx_config_get,
2432 .pin_config_set = npcm8xx_config_set,
2433 };
2434
2435 /* pinctrl_desc */
2436 static const struct pinctrl_desc npcm8xx_pinctrl_desc = {
2437 .name = "npcm8xx-pinctrl",
2438 .pins = npcm8xx_pins,
2439 .npins = ARRAY_SIZE(npcm8xx_pins),
2440 .pctlops = &npcm8xx_pinctrl_ops,
2441 .pmxops = &npcm8xx_pinmux_ops,
2442 .confops = &npcm8xx_pinconf_ops,
2443 .owner = THIS_MODULE,
2444 };
2445
npcmgpio_add_pin_ranges(struct gpio_chip * chip)2446 static int npcmgpio_add_pin_ranges(struct gpio_chip *chip)
2447 {
2448 struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
2449
2450 return gpiochip_add_pin_range(&bank->chip.gc, dev_name(chip->parent),
2451 bank->pinctrl_id, bank->chip.gc.base,
2452 bank->chip.gc.ngpio);
2453 }
2454
npcm8xx_gpio_fw(struct npcm8xx_pinctrl * pctrl)2455 static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl)
2456 {
2457 struct gpio_generic_chip_config config;
2458 struct fwnode_reference_args args;
2459 struct device *dev = pctrl->dev;
2460 struct fwnode_handle *child;
2461 int ret = -ENXIO;
2462 int id = 0, i;
2463
2464 for_each_gpiochip_node(dev, child) {
2465 pctrl->gpio_bank[id].base = fwnode_iomap(child, 0);
2466 if (!pctrl->gpio_bank[id].base)
2467 return dev_err_probe(dev, -ENXIO, "fwnode_iomap id %d failed\n", id);
2468
2469 config = (struct gpio_generic_chip_config) {
2470 .dev = dev,
2471 .sz = 4,
2472 .dat = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN,
2473 .set = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT,
2474 .dirin = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM,
2475 .flags = GPIO_GENERIC_READ_OUTPUT_REG_SET,
2476 };
2477
2478 ret = gpio_generic_chip_init(&pctrl->gpio_bank[id].chip, &config);
2479 if (ret)
2480 return dev_err_probe(dev, ret,
2481 "failed to initialize the generic GPIO chip\n");
2482
2483 ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args);
2484 if (ret < 0)
2485 return dev_err_probe(dev, ret, "gpio-ranges fail for GPIO bank %u\n", id);
2486
2487 ret = fwnode_irq_get(child, 0);
2488 if (ret < 0)
2489 return dev_err_probe(dev, ret, "Failed to retrieve IRQ for bank %u\n", id);
2490
2491 iowrite32(0, pctrl->gpio_bank[id].base + NPCM8XX_GP_N_EVEN);
2492 iowrite32(0xffffffff, pctrl->gpio_bank[id].base + NPCM8XX_GP_N_EVST);
2493
2494 pctrl->gpio_bank[id].irq = ret;
2495 pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip;
2496 pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK;
2497 pctrl->gpio_bank[id].pinctrl_id = args.args[0];
2498 pctrl->gpio_bank[id].chip.gc.base = -1;
2499 pctrl->gpio_bank[id].chip.gc.ngpio = args.args[2];
2500 pctrl->gpio_bank[id].chip.gc.owner = THIS_MODULE;
2501 pctrl->gpio_bank[id].chip.gc.parent = dev;
2502 pctrl->gpio_bank[id].chip.gc.fwnode = child;
2503 pctrl->gpio_bank[id].chip.gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child);
2504 if (pctrl->gpio_bank[id].chip.gc.label == NULL)
2505 return -ENOMEM;
2506
2507 pctrl->gpio_bank[id].chip.gc.dbg_show = npcmgpio_dbg_show;
2508 pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].chip.gc.direction_input;
2509 pctrl->gpio_bank[id].chip.gc.direction_input = npcmgpio_direction_input;
2510 pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].chip.gc.direction_output;
2511 pctrl->gpio_bank[id].chip.gc.direction_output = npcmgpio_direction_output;
2512 pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].chip.gc.request;
2513 pctrl->gpio_bank[id].chip.gc.request = npcmgpio_gpio_request;
2514 pctrl->gpio_bank[id].chip.gc.free = pinctrl_gpio_free;
2515 for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++)
2516 pctrl->gpio_bank[id].debounce.set_val[i] = false;
2517 pctrl->gpio_bank[id].chip.gc.add_pin_ranges = npcmgpio_add_pin_ranges;
2518 id++;
2519 }
2520
2521 pctrl->bank_num = id;
2522 return ret;
2523 }
2524
npcm8xx_gpio_register(struct npcm8xx_pinctrl * pctrl)2525 static int npcm8xx_gpio_register(struct npcm8xx_pinctrl *pctrl)
2526 {
2527 int ret, id;
2528
2529 for (id = 0 ; id < pctrl->bank_num ; id++) {
2530 struct gpio_irq_chip *girq;
2531
2532 girq = &pctrl->gpio_bank[id].chip.gc.irq;
2533 girq->chip = &pctrl->gpio_bank[id].irq_chip;
2534 girq->parent_handler = npcmgpio_irq_handler;
2535 girq->num_parents = 1;
2536 girq->parents = devm_kcalloc(pctrl->dev, girq->num_parents,
2537 sizeof(*girq->parents),
2538 GFP_KERNEL);
2539 if (!girq->parents)
2540 return -ENOMEM;
2541
2542 girq->parents[0] = pctrl->gpio_bank[id].irq;
2543 girq->default_type = IRQ_TYPE_NONE;
2544 girq->handler = handle_level_irq;
2545 ret = devm_gpiochip_add_data(pctrl->dev,
2546 &pctrl->gpio_bank[id].chip.gc,
2547 &pctrl->gpio_bank[id]);
2548 if (ret)
2549 return dev_err_probe(pctrl->dev, ret, "Failed to add GPIO chip %u\n", id);
2550 }
2551
2552 return 0;
2553 }
2554
npcm8xx_pinctrl_probe(struct platform_device * pdev)2555 static int npcm8xx_pinctrl_probe(struct platform_device *pdev)
2556 {
2557 struct device *dev = &pdev->dev;
2558 struct npcm8xx_pinctrl *pctrl;
2559 int ret;
2560
2561 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
2562 if (!pctrl)
2563 return -ENOMEM;
2564
2565 pctrl->dev = dev;
2566 platform_set_drvdata(pdev, pctrl);
2567
2568 pctrl->gcr_regmap =
2569 syscon_regmap_lookup_by_phandle(dev_of_node(dev), "nuvoton,sysgcr");
2570 if (IS_ERR(pctrl->gcr_regmap))
2571 return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap),
2572 "Failed to find nuvoton,sysgcr property\n");
2573
2574 ret = npcm8xx_gpio_fw(pctrl);
2575 if (ret < 0)
2576 return dev_err_probe(dev, ret,
2577 "Failed to gpio dt-binding\n");
2578
2579 pctrl->pctldev = devm_pinctrl_register(dev, &npcm8xx_pinctrl_desc, pctrl);
2580 if (IS_ERR(pctrl->pctldev))
2581 return dev_err_probe(dev, PTR_ERR(pctrl->pctldev),
2582 "Failed to register pinctrl device\n");
2583
2584 ret = npcm8xx_gpio_register(pctrl);
2585 if (ret < 0)
2586 dev_err_probe(dev, ret, "Failed to register gpio\n");
2587
2588 return 0;
2589 }
2590
2591 static const struct of_device_id npcm8xx_pinctrl_match[] = {
2592 { .compatible = "nuvoton,npcm845-pinctrl" },
2593 { }
2594 };
2595 MODULE_DEVICE_TABLE(of, npcm8xx_pinctrl_match);
2596
2597 static struct platform_driver npcm8xx_pinctrl_driver = {
2598 .probe = npcm8xx_pinctrl_probe,
2599 .driver = {
2600 .name = "npcm8xx-pinctrl",
2601 .of_match_table = npcm8xx_pinctrl_match,
2602 .suppress_bind_attrs = true,
2603 },
2604 };
2605
npcm8xx_pinctrl_register(void)2606 static int __init npcm8xx_pinctrl_register(void)
2607 {
2608 return platform_driver_register(&npcm8xx_pinctrl_driver);
2609 }
2610 arch_initcall(npcm8xx_pinctrl_register);
2611
2612 MODULE_LICENSE("GPL v2");
2613 MODULE_AUTHOR("tomer.maimon@nuvoton.com");
2614 MODULE_DESCRIPTION("Nuvoton NPCM8XX Pinctrl and GPIO driver");
2615