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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28-var4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
12 /dts-v1/;
13 #include "fsl-ls1028a-kontron-sl28.dts"
14 #include <dt-bindings/net/qca-ar803x.h>
17 model = "Kontron SMARC-sAL28 (Dual PHY)";
18 compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
22 phy1: ethernet-phy@4 {
24 eee-broken-1000t;
25 eee-broken-100tx;
[all …]
H A Dfsl-ls1028a-kontron-sl28-var1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
15 /dts-v1/;
16 #include "fsl-ls1028a-kontron-sl28.dts"
17 #include <dt-bindings/net/qca-ar803x.h>
20 model = "Kontron SMARC-sAL28 (4 Lanes)";
21 compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
26 /delete-node/ ethernet-phy@5;
28 phy0: ethernet-phy@4 {
30 eee-broken-1000t;
[all …]
H A Dfsl-ls1028a-kontron-sl28-var2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
12 /dts-v1/;
13 #include "fsl-ls1028a-kontron-sl28.dts"
16 model = "Kontron SMARC-sAL28 (TSN-on-module)";
17 compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a";
21 phy1: ethernet-phy@4 {
23 eee-broken-1000t;
24 eee-broken-100tx;
33 * port instead. Therefore, delete the phy-handle property here.
[all …]
H A Dfsl-lx2160a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2018-2020 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
H A Dfsl-lx2162a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2162a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "LTM4619-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
[all …]
H A Dfsl-ls1028a-kontron-sl28.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
9 /dts-v1/;
10 #include "fsl-ls1028a.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
16 model = "Kontron SMARC-sAL28";
33 compatible = "gpio-keys";
35 power-button {
[all …]
H A Dimx93-var-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
12 model = "Variscite VAR-SOM-MX93 module";
13 compatible = "variscite,var-som-mx93", "fsl,imx93";
15 mmc_pwrseq: mmc-pwrseq {
16 compatible = "mmc-pwrseq-simple";
17 post-power-on-delay-ms = <100>;
18 power-off-delay-us = <10000>;
19 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
25 pinctrl-names = "default";
[all …]
H A Dimx8mp-debix-som-a-bmb-08.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx8mp-debix-som-a.dtsi"
12 model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08";
13 compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a",
22 stdout-path = &uart2;
25 reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 {
26 compatible = "regulator-fixed";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
[all …]
H A Dimx8mp-msc-sm2s.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 #include <dt-bindings/net/ti-dp83867.h>
18 stdout-path = &uart2;
21 reg_usb0_host_vbus: regulator-usb0-vbus {
22 compatible = "regulator-fixed";
23 regulator-name = "usb0_host_vbus";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_usb0_vbus>;
26 regulator-min-microvolt = <5000000>;
[all …]
H A Dimx93-var-som-symphony.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/leds/common.h>
10 #include "imx93-var-som.dtsi"
13 model = "Variscite VAR-SOM-MX93 on Symphony evaluation board";
14 compatible = "variscite,var-som-mx93-symphony",
15 "variscite,var-som-mx93", "fsl,imx93";
23 stdout-path = &lpuart1;
29 reg_fec_phy: regulator-fec-phy {
30 compatible = "regulator-fixed";
[all …]
H A Dimx8mp-nitrogen-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "boundary,imx8mp-nitrogen-som", "fsl,imx8mp";
13 rfkill-bt {
14 compatible = "rfkill-gpio";
15 label = "rfkill-bluetooth";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_rfkill_bt>;
18 radio-type = "bluetooth";
19 shutdown-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
22 rfkill-wlan {
[all …]
H A Dimx8mp-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
16 stdout-path = &uart2;
19 backlight_lvds: backlight-lvds {
20 compatible = "pwm-backlight";
22 brightness-levels = <0 100>;
23 num-interpolated-steps = <100>;
24 default-brightness-level = <100>;
[all …]
H A Dimx93-14x14-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/usb/pd.h>
13 compatible = "fsl,imx93-14x14-evk", "fsl,imx93";
16 stdout-path = &lpuart1;
19 reserved-memory {
20 #address-cells = <2>;
21 #size-cells = <2>;
25 compatible = "shared-dma-pool";
27 alloc-ranges = <0 0x80000000 0 0x40000000>;
[all …]
H A Dimx8mp-verdin.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
7 #include <dt-bindings/pwm/pwm.h>
12 stdout-path = &uart3;
24 compatible = "pwm-backlight";
25 brightness-levels = <0 45 63 88 119 158 203 255>;
26 default-brightness-level = <4>;
28 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
[all …]
H A Dimx93-11x11-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/usb/pd.h>
13 compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
16 stdout-path = &lpuart1;
19 reserved-memory {
20 #address-cells = <2>;
21 #size-cells = <2>;
25 compatible = "shared-dma-pool";
27 alloc-ranges = <0 0x80000000 0 0x40000000>;
[all …]
H A Dimx8dxl-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
12 compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
24 stdout-path = &lpuart0;
27 imx8dxl-cm4 {
28 compatible = "fsl,imx8qxp-cm4";
30 mbox-names = "tx", "rx", "rxdb";
32 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
34 power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;
35 fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
[all …]
/linux/drivers/net/phy/
H A Dphy-core.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include "phylib-internal.h"
11 #include "phy-caps.h"
14 * phy_speed_to_str - Return a string representing the PHY link speed
61 return "Unsupported (update phy-core.c)"; in phy_speed_to_str()
67 * phy_duplex_to_str - Return string describing the duplex
79 return "Unsupported (update phy-core.c)"; in phy_duplex_to_str()
84 * phy_rate_matching_to_str - Return a string describing the rate matching
98 return "open-loop"; in phy_rate_matching_to_str()
100 return "Unsupported (update phy-core.c)"; in phy_rate_matching_to_str()
[all …]
H A Dphy_device.c1 // SPDX-License-Identifier: GPL-2.0+
33 #include <linux/pse-pd/pse.h>
44 #include "phylib-internal.h"
45 #include "phy-caps.h"
167 /* 10/100 half/full + 1000 half/full */ in features_init()
178 /* 10/100 half/full + 1000 half/full + fibre*/ in features_init()
190 /* 10/100 half/full + 1000 half/full + 10G full*/ in features_init()
214 put_device(&phydev->mdio.dev); in phy_device_free()
228 fwnode_handle_put(dev->fwnode); in phy_device_release()
256 struct net_device *netdev = phydev->attached_dev; in phy_link_change()
[all …]
H A Dphylink.c1 // SPDX-License-Identifier: GPL-2.0
4 * technologies such as SFP cages where the PHY is hot-pluggable.
23 #include "phy-caps.h"
38 * struct phylink - internal data type for phylink
55 u8 link_port; /* The current non-phy ethtool port */
98 if ((pl)->config->type == PHYLINK_NETDEV) \
99 netdev_printk(level, (pl)->netdev, fmt, ##__VA_ARGS__); \
100 else if ((pl)->config->type == PHYLINK_DEV) \
101 dev_printk(level, (pl)->dev, fmt, ##__VA_ARGS__); \
113 if ((pl)->config->type == PHYLINK_NETDEV) \
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam5729-beagleboneai.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2019 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
9 #include "am57xx-commercial-grade.dtsi"
10 #include "dra74x-mmc-iodelay.dtsi"
11 #include "dra74-ipu-dsp-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/dra.h>
18 compatible = "beagle,am5729-beagleboneai", "ti,am5728",
[all …]
H A Dam335x-myirtech-myd.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
4 /* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */
6 /dts-v1/;
8 #include "am335x-myirtech-myc.dtsi"
10 #include <dt-bindings/display/tda998x.h>
11 #include <dt-bindings/input/input.h>
14 model = "MYIR MYD-AM335X";
15 compatible = "myir,myd-am335x", "myir,myc-am335x", "ti,am33xx";
18 stdout-path = &uart0;
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12a-x96-max.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-g12a.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-g12a-gpio.h>
11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
14 compatible = "amediatech,x96-max", "amlogic,g12a";
22 spdif_dit: audio-codec-1 {
23 #sound-dai-cells = <0>;
24 compatible = "linux,spdif-dit";
[all …]
H A Dmeson-axg-s400.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-axg.dtsi"
9 #include <dt-bindings/input/input.h>
12 compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg";
16 compatible = "adc-keys";
17 io-channels = <&saradc 0>;
18 io-channel-names = "buttons";
19 keyup-threshold-microvolt = <1800000>;
21 button-next {
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_main.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/dma-mapping.h>
51 /* The default timer value as per the sxgbe specification 1 sec(1000 ms) */
52 #define SXGBE_DEFAULT_LPI_TIMER 1000
54 static int debug = -1;
73 * sxgbe_verify_args - verify the driver parameters.
86 if (!priv->tx_path_in_lpi_mode) in sxgbe_enable_eee_mode()
87 priv->hw->mac->set_eee_mode(priv->ioaddr); in sxgbe_enable_eee_mode()
92 /* Exit and disable EEE in case of we are in LPI state. */ in sxgbe_disable_eee_mode()
93 priv->hw->mac->reset_eee_mode(priv->ioaddr); in sxgbe_disable_eee_mode()
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.c7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
14 * Copyright (C) 2000-2016 Broadcom Corporation.
15 * Copyright (C) 2016-2017 Broadcom Ltd.
52 #include <linux/dma-mapping.h>
56 #include <linux/hwmon-sysfs.h>
94 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
96 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
98 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
124 * and dev->tx_timeout() should be called to fix the problem
[all …]

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