1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> 4 */ 5 6#include <dt-bindings/clock/qcom,milos-camcc.h> 7#include <dt-bindings/clock/qcom,milos-dispcc.h> 8#include <dt-bindings/clock/qcom,milos-gcc.h> 9#include <dt-bindings/clock/qcom,milos-gpucc.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm8650-tcsr.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,milos-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <76800000>; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32764>; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 cpu0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a520"; 54 reg = <0x0 0x0>; 55 56 clocks = <&cpufreq_hw 0>; 57 58 power-domains = <&cpu_pd0>; 59 power-domain-names = "psci"; 60 61 enable-method = "psci"; 62 next-level-cache = <&l2_0>; 63 capacity-dmips-mhz = <1024>; 64 dynamic-power-coefficient = <100>; 65 66 qcom,freq-domain = <&cpufreq_hw 0>; 67 68 #cooling-cells = <2>; 69 70 l2_0: l2-cache { 71 compatible = "cache"; 72 cache-level = <2>; 73 cache-unified; 74 next-level-cache = <&l3_0>; 75 76 l3_0: l3-cache { 77 compatible = "cache"; 78 cache-level = <3>; 79 cache-unified; 80 }; 81 }; 82 }; 83 84 cpu1: cpu@100 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a520"; 87 reg = <0x0 0x100>; 88 89 clocks = <&cpufreq_hw 0>; 90 91 power-domains = <&cpu_pd1>; 92 power-domain-names = "psci"; 93 94 enable-method = "psci"; 95 next-level-cache = <&l2_0>; 96 capacity-dmips-mhz = <1024>; 97 dynamic-power-coefficient = <100>; 98 99 qcom,freq-domain = <&cpufreq_hw 0>; 100 101 #cooling-cells = <2>; 102 }; 103 104 cpu2: cpu@200 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a520"; 107 reg = <0x0 0x200>; 108 109 clocks = <&cpufreq_hw 0>; 110 111 power-domains = <&cpu_pd2>; 112 power-domain-names = "psci"; 113 114 enable-method = "psci"; 115 next-level-cache = <&l2_2>; 116 capacity-dmips-mhz = <1024>; 117 dynamic-power-coefficient = <100>; 118 119 qcom,freq-domain = <&cpufreq_hw 0>; 120 121 #cooling-cells = <2>; 122 123 l2_2: l2-cache { 124 compatible = "cache"; 125 cache-level = <2>; 126 cache-unified; 127 next-level-cache = <&l3_0>; 128 }; 129 }; 130 131 cpu3: cpu@300 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a520"; 134 reg = <0x0 0x300>; 135 136 clocks = <&cpufreq_hw 0>; 137 138 power-domains = <&cpu_pd3>; 139 power-domain-names = "psci"; 140 141 enable-method = "psci"; 142 next-level-cache = <&l2_2>; 143 capacity-dmips-mhz = <1024>; 144 dynamic-power-coefficient = <100>; 145 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 148 #cooling-cells = <2>; 149 }; 150 151 cpu4: cpu@400 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a720"; 154 reg = <0x0 0x400>; 155 156 clocks = <&cpufreq_hw 1>; 157 158 power-domains = <&cpu_pd4>; 159 power-domain-names = "psci"; 160 161 enable-method = "psci"; 162 next-level-cache = <&l2_4>; 163 capacity-dmips-mhz = <1670>; 164 dynamic-power-coefficient = <264>; 165 166 qcom,freq-domain = <&cpufreq_hw 1>; 167 168 #cooling-cells = <2>; 169 170 l2_4: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&l3_0>; 175 }; 176 }; 177 178 cpu5: cpu@500 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a720"; 181 reg = <0x0 0x500>; 182 183 clocks = <&cpufreq_hw 1>; 184 185 power-domains = <&cpu_pd5>; 186 power-domain-names = "psci"; 187 188 enable-method = "psci"; 189 next-level-cache = <&l2_5>; 190 capacity-dmips-mhz = <1670>; 191 dynamic-power-coefficient = <264>; 192 193 qcom,freq-domain = <&cpufreq_hw 1>; 194 195 #cooling-cells = <2>; 196 197 l2_5: l2-cache { 198 compatible = "cache"; 199 cache-level = <2>; 200 cache-unified; 201 next-level-cache = <&l3_0>; 202 }; 203 }; 204 205 cpu6: cpu@600 { 206 device_type = "cpu"; 207 compatible = "arm,cortex-a720"; 208 reg = <0x0 0x600>; 209 210 clocks = <&cpufreq_hw 1>; 211 212 power-domains = <&cpu_pd6>; 213 power-domain-names = "psci"; 214 215 enable-method = "psci"; 216 next-level-cache = <&l2_6>; 217 capacity-dmips-mhz = <1670>; 218 dynamic-power-coefficient = <264>; 219 220 qcom,freq-domain = <&cpufreq_hw 1>; 221 222 #cooling-cells = <2>; 223 224 l2_6: l2-cache { 225 compatible = "cache"; 226 cache-level = <2>; 227 cache-unified; 228 next-level-cache = <&l3_0>; 229 }; 230 }; 231 232 cpu7: cpu@700 { 233 device_type = "cpu"; 234 compatible = "arm,cortex-a720"; 235 reg = <0x0 0x700>; 236 237 clocks = <&cpufreq_hw 2>; 238 239 power-domains = <&cpu_pd7>; 240 power-domain-names = "psci"; 241 242 enable-method = "psci"; 243 next-level-cache = <&l2_7>; 244 capacity-dmips-mhz = <1670>; 245 dynamic-power-coefficient = <287>; 246 247 qcom,freq-domain = <&cpufreq_hw 2>; 248 249 #cooling-cells = <2>; 250 251 l2_7: l2-cache { 252 compatible = "cache"; 253 cache-level = <2>; 254 cache-unified; 255 next-level-cache = <&l3_0>; 256 }; 257 }; 258 259 cpu-map { 260 cluster0 { 261 core0 { 262 cpu = <&cpu0>; 263 }; 264 265 core1 { 266 cpu = <&cpu1>; 267 }; 268 269 core2 { 270 cpu = <&cpu2>; 271 }; 272 273 core3 { 274 cpu = <&cpu3>; 275 }; 276 }; 277 278 cluster1 { 279 core0 { 280 cpu = <&cpu4>; 281 }; 282 283 core1 { 284 cpu = <&cpu5>; 285 }; 286 287 core2 { 288 cpu = <&cpu6>; 289 }; 290 }; 291 292 cluster2 { 293 core0 { 294 cpu = <&cpu7>; 295 }; 296 }; 297 }; 298 299 idle-states { 300 entry-method = "psci"; 301 302 silver_cpu_sleep_0: cpu-sleep-0-0 { 303 compatible = "arm,idle-state"; 304 idle-state-name = "pc"; 305 arm,psci-suspend-param = <0x40000003>; 306 entry-latency-us = <250>; 307 exit-latency-us = <700>; 308 min-residency-us = <5200>; 309 local-timer-stop; 310 }; 311 312 silver_cpu_sleep_1: cpu-sleep-0-1 { 313 compatible = "arm,idle-state"; 314 idle-state-name = "silver-rail-power-collapse"; 315 arm,psci-suspend-param = <0x40000004>; 316 entry-latency-us = <550>; 317 exit-latency-us = <750>; 318 min-residency-us = <6700>; 319 local-timer-stop; 320 }; 321 322 gold_cpu_sleep_0: cpu-sleep-1-0 { 323 compatible = "arm,idle-state"; 324 idle-state-name = "silver-power-collapse"; 325 arm,psci-suspend-param = <0x40000003>; 326 entry-latency-us = <400>; 327 exit-latency-us = <900>; 328 min-residency-us = <5511>; 329 local-timer-stop; 330 }; 331 332 gold_cpu_sleep_1: cpu-sleep-1-1 { 333 compatible = "arm,idle-state"; 334 idle-state-name = "gold-rail-power-collapse"; 335 arm,psci-suspend-param = <0x40000004>; 336 entry-latency-us = <600>; 337 exit-latency-us = <1300>; 338 min-residency-us = <8136>; 339 local-timer-stop; 340 }; 341 342 gold_plus_cpu_sleep_0: cpu-sleep-2-0 { 343 compatible = "arm,idle-state"; 344 idle-state-name = "gold-plus-rail-power-collapse"; 345 arm,psci-suspend-param = <0x40000004>; 346 entry-latency-us = <600>; 347 exit-latency-us = <1500>; 348 min-residency-us = <8551>; 349 local-timer-stop; 350 }; 351 }; 352 353 domain-idle-states { 354 cluster_sleep_0: cluster-sleep-0 { 355 compatible = "domain-idle-state"; 356 arm,psci-suspend-param = <0x41000044>; 357 entry-latency-us = <750>; 358 exit-latency-us = <2350>; 359 min-residency-us = <9144>; 360 }; 361 362 cluster_sleep_1: cluster-sleep-1 { 363 compatible = "domain-idle-state"; 364 arm,psci-suspend-param = <0x41003344>; 365 entry-latency-us = <2800>; 366 exit-latency-us = <4400>; 367 min-residency-us = <10150>; 368 }; 369 }; 370 }; 371 372 firmware { 373 scm: scm { 374 compatible = "qcom,scm-milos", "qcom,scm"; 375 qcom,dload-mode = <&tcsr 0x19000>; 376 }; 377 }; 378 379 clk_virt: interconnect-0 { 380 compatible = "qcom,milos-clk-virt"; 381 #interconnect-cells = <2>; 382 qcom,bcm-voters = <&apps_bcm_voter>; 383 }; 384 385 mc_virt: interconnect-1 { 386 compatible = "qcom,milos-mc-virt"; 387 #interconnect-cells = <2>; 388 qcom,bcm-voters = <&apps_bcm_voter>; 389 }; 390 391 memory@0 { 392 device_type = "memory"; 393 /* We expect the bootloader to fill in the size */ 394 reg = <0 0 0 0>; 395 }; 396 397 pmu-a520 { 398 compatible = "arm,cortex-a520-pmu"; 399 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 400 }; 401 402 pmu-a720 { 403 compatible = "arm,cortex-a720-pmu"; 404 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 405 }; 406 407 psci { 408 compatible = "arm,psci-1.0"; 409 method = "smc"; 410 411 cpu_pd0: power-domain-cpu0 { 412 #power-domain-cells = <0>; 413 power-domains = <&cluster_pd>; 414 domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; 415 }; 416 417 cpu_pd1: power-domain-cpu1 { 418 #power-domain-cells = <0>; 419 power-domains = <&cluster_pd>; 420 domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; 421 }; 422 423 cpu_pd2: power-domain-cpu2 { 424 #power-domain-cells = <0>; 425 power-domains = <&cluster_pd>; 426 domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; 427 }; 428 429 cpu_pd3: power-domain-cpu3 { 430 #power-domain-cells = <0>; 431 power-domains = <&cluster_pd>; 432 domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; 433 }; 434 435 cpu_pd4: power-domain-cpu4 { 436 #power-domain-cells = <0>; 437 power-domains = <&cluster_pd>; 438 domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; 439 }; 440 441 cpu_pd5: power-domain-cpu5 { 442 #power-domain-cells = <0>; 443 power-domains = <&cluster_pd>; 444 domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; 445 }; 446 447 cpu_pd6: power-domain-cpu6 { 448 #power-domain-cells = <0>; 449 power-domains = <&cluster_pd>; 450 domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; 451 }; 452 453 cpu_pd7: power-domain-cpu7 { 454 #power-domain-cells = <0>; 455 power-domains = <&cluster_pd>; 456 domain-idle-states = <&gold_plus_cpu_sleep_0>; 457 }; 458 459 cluster_pd: power-domain-cluster { 460 #power-domain-cells = <0>; 461 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; 462 }; 463 }; 464 465 reserved-memory { 466 #address-cells = <2>; 467 #size-cells = <2>; 468 ranges; 469 470 gunyah_hyp_mem: gunyah-hyp-region@80000000 { 471 reg = <0x0 0x80000000 0x0 0xe00000>; 472 no-map; 473 }; 474 475 xbl_sc_mem: xbl-sc-region@81800000 { 476 reg = <0x0 0x81800000 0x0 0x40000>; 477 no-map; 478 }; 479 480 cpucp_fw_mem: cpucp-fw-region@81840000 { 481 reg = <0x0 0x81840000 0x0 0x1c0000>; 482 no-map; 483 }; 484 485 xbl_dtlog_mem: xbl-dtlog-region@81a00000 { 486 reg = <0x0 0x81a00000 0x0 0x40000>; 487 no-map; 488 }; 489 490 xbl_ramdump_mem: xbl-ramdump-region@81a40000 { 491 reg = <0x0 0x81a40000 0x0 0x1c0000>; 492 no-map; 493 }; 494 495 aop_image_mem: aop-image-region@81c00000 { 496 reg = <0x0 0x81c00000 0x0 0x60000>; 497 no-map; 498 }; 499 500 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 501 compatible = "qcom,cmd-db"; 502 reg = <0x0 0x81c60000 0x0 0x20000>; 503 no-map; 504 }; 505 506 aop_config_mem: aop-config-region@81c80000 { 507 reg = <0x0 0x81c80000 0x0 0x20000>; 508 no-map; 509 }; 510 511 tme_crash_dump_mem: tme-crash-dump-region@81ca0000 { 512 reg = <0x0 0x81ca0000 0x0 0x40000>; 513 no-map; 514 }; 515 516 tme_log_mem: tme-log-region@81ce0000 { 517 reg = <0x0 0x81ce0000 0x0 0x4000>; 518 no-map; 519 }; 520 521 uefi_log_mem: uefi-log-region@81ce4000 { 522 reg = <0x0 0x81ce4000 0x0 0x10000>; 523 no-map; 524 }; 525 526 chipinfo_mem: chipinfo-region@81cf4000 { 527 reg = <0x0 0x81cf4000 0x0 0x1000>; 528 no-map; 529 }; 530 531 secdata_apss_mem: secdata-apss-region@81cff000 { 532 reg = <0x0 0x81cff000 0x0 0x1000>; 533 no-map; 534 }; 535 536 smem_mem: smem-region@81d00000 { 537 compatible = "qcom,smem"; 538 reg = <0x0 0x81d00000 0x0 0x200000>; 539 hwlocks = <&tcsr_mutex 3>; 540 no-map; 541 }; 542 543 adsp_mhi_mem: adsp-mhi-region@81f00000 { 544 reg = <0x0 0x81f00000 0x0 0x20000>; 545 no-map; 546 }; 547 548 pvm_fw_mem: pvm-fw-region@824a0000 { 549 reg = <0x0 0x824a0000 0x0 0x100000>; 550 no-map; 551 }; 552 553 hyp_mem_database_mem: hyp-mem-database-region@825a0000 { 554 reg = <0x0 0x825a0000 0x0 0x60000>; 555 no-map; 556 }; 557 558 global_sync_mem: global-sync-region@82600000 { 559 reg = <0x0 0x82600000 0x0 0x100000>; 560 no-map; 561 }; 562 563 tz_stat_mem: tz-stat-region@82700000 { 564 reg = <0x0 0x82700000 0x0 0x100000>; 565 no-map; 566 }; 567 568 qdss_apps_mem: qdss-apps-region@82800000 { 569 reg = <0x0 0x82800000 0x0 0x2000000>; 570 reusable; 571 }; 572 573 mpss_mem: mpss-region@8ac00000 { 574 reg = <0x0 0x8ac00000 0x0 0xe600000>; 575 no-map; 576 }; 577 578 q6_mpss_dtb_mem: q6-mpss-dtb-region@99200000 { 579 reg = <0x0 0x99200000 0x0 0x80000>; 580 no-map; 581 }; 582 583 q6_adsp_dtb_mem: q6-adsp-dtb-region@99280000 { 584 reg = <0x0 0x99280000 0x0 0x80000>; 585 no-map; 586 }; 587 588 adspslpi_mem: adspslpi-region@99300000 { 589 reg = <0x0 0x99300000 0x0 0x2800000>; 590 no-map; 591 }; 592 593 wpss_mem: wpss-region@9bb00000 { 594 reg = <0x0 0x9bb00000 0x0 0x1900000>; 595 no-map; 596 }; 597 598 video_mem: video-region@9d400000 { 599 reg = <0x0 0x9d400000 0x0 0x700000>; 600 no-map; 601 }; 602 603 cdsp_mem: cdsp-region@9db00000 { 604 reg = <0x0 0x9db00000 0x0 0xf00000>; 605 no-map; 606 }; 607 608 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9ea00000 { 609 reg = <0x0 0x9ea00000 0x0 0x80000>; 610 no-map; 611 }; 612 613 ipa_fw_mem: ipa-fw-region@9ea80000 { 614 reg = <0x0 0x9ea80000 0x0 0x10000>; 615 no-map; 616 }; 617 618 ipa_gsi_mem: ipa-gsi-region@9ea90000 { 619 reg = <0x0 0x9ea90000 0x0 0xa000>; 620 no-map; 621 }; 622 623 gpu_microcode_mem: gpu-microcode-region@9ea9a000 { 624 reg = <0x0 0x9ea9a000 0x0 0x2000>; 625 no-map; 626 }; 627 628 camera_mem: camera-region@9eb00000 { 629 reg = <0x0 0x9eb00000 0x0 0x800000>; 630 no-map; 631 }; 632 633 wlan_msa_mem: wlan-msa-region@a6400000 { 634 reg = <0x0 0xa6400000 0x0 0xc00000>; 635 no-map; 636 }; 637 638 cpusys_vm_mem: cpusys-vm-region@e0600000 { 639 reg = <0x0 0xe0600000 0x0 0x400000>; 640 no-map; 641 }; 642 643 rmtfs_mem: rmtfs@e1f00000 { 644 compatible = "qcom,rmtfs-mem"; 645 reg = <0x0 0xe1f00000 0x0 0x600000>; 646 no-map; 647 648 qcom,client-id = <1>; 649 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 650 }; 651 652 qtee_mem: qtee-region@e8900000 { 653 reg = <0x0 0xe8900000 0x0 0x500000>; 654 no-map; 655 }; 656 657 tags_mem: tags-region@e8e00000 { 658 reg = <0x0 0xe8e00000 0x0 0x700000>; 659 no-map; 660 }; 661 662 trusted_apps_mem: trusted-apps-region@e9500000 { 663 reg = <0x0 0xe9500000 0x0 0x1200000>; 664 no-map; 665 }; 666 }; 667 668 smp2p-adsp { 669 compatible = "qcom,smp2p"; 670 qcom,smem = <443>, <429>; 671 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 672 IPCC_MPROC_SIGNAL_SMP2P 673 IRQ_TYPE_EDGE_RISING>; 674 mboxes = <&ipcc IPCC_CLIENT_LPASS 675 IPCC_MPROC_SIGNAL_SMP2P>; 676 677 qcom,local-pid = <0>; 678 qcom,remote-pid = <2>; 679 680 smp2p_adsp_out: master-kernel { 681 qcom,entry-name = "master-kernel"; 682 #qcom,smem-state-cells = <1>; 683 }; 684 685 smp2p_adsp_in: slave-kernel { 686 qcom,entry-name = "slave-kernel"; 687 interrupt-controller; 688 #interrupt-cells = <2>; 689 }; 690 }; 691 692 smp2p-cdsp { 693 compatible = "qcom,smp2p"; 694 qcom,smem = <94>, <432>; 695 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 696 IPCC_MPROC_SIGNAL_SMP2P 697 IRQ_TYPE_EDGE_RISING>; 698 mboxes = <&ipcc IPCC_CLIENT_CDSP 699 IPCC_MPROC_SIGNAL_SMP2P>; 700 701 qcom,local-pid = <0>; 702 qcom,remote-pid = <5>; 703 704 smp2p_cdsp_out: master-kernel { 705 qcom,entry-name = "master-kernel"; 706 #qcom,smem-state-cells = <1>; 707 }; 708 709 smp2p_cdsp_in: slave-kernel { 710 qcom,entry-name = "slave-kernel"; 711 interrupt-controller; 712 #interrupt-cells = <2>; 713 }; 714 }; 715 716 smp2p-modem { 717 compatible = "qcom,smp2p"; 718 qcom,smem = <435>, <428>; 719 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 720 IPCC_MPROC_SIGNAL_SMP2P 721 IRQ_TYPE_EDGE_RISING>; 722 mboxes = <&ipcc IPCC_CLIENT_MPSS 723 IPCC_MPROC_SIGNAL_SMP2P>; 724 725 qcom,local-pid = <0>; 726 qcom,remote-pid = <1>; 727 728 smp2p_modem_out: master-kernel { 729 qcom,entry-name = "master-kernel"; 730 #qcom,smem-state-cells = <1>; 731 }; 732 733 smp2p_modem_in: slave-kernel { 734 qcom,entry-name = "slave-kernel"; 735 interrupt-controller; 736 #interrupt-cells = <2>; 737 }; 738 739 smp2p_ipa_out: ipa-ap-to-modem { 740 qcom,entry-name = "ipa"; 741 #qcom,smem-state-cells = <1>; 742 }; 743 744 smp2p_ipa_in: ipa-modem-to-ap { 745 qcom,entry-name = "ipa"; 746 interrupt-controller; 747 #interrupt-cells = <2>; 748 }; 749 }; 750 751 smp2p-wpss { 752 compatible = "qcom,smp2p"; 753 qcom,smem = <617>, <616>; 754 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 755 IPCC_MPROC_SIGNAL_SMP2P 756 IRQ_TYPE_EDGE_RISING>; 757 mboxes = <&ipcc IPCC_CLIENT_WPSS 758 IPCC_MPROC_SIGNAL_SMP2P>; 759 760 qcom,local-pid = <0>; 761 qcom,remote-pid = <13>; 762 763 smp2p_wpss_out: master-kernel { 764 qcom,entry-name = "master-kernel"; 765 #qcom,smem-state-cells = <1>; 766 }; 767 768 smp2p_wpss_in: slave-kernel { 769 qcom,entry-name = "slave-kernel"; 770 interrupt-controller; 771 #interrupt-cells = <2>; 772 }; 773 774 smp2p_wlan_out: wlan-ap-to-wpss { 775 qcom,entry-name = "wlan"; 776 #qcom,smem-state-cells = <1>; 777 }; 778 779 smp2p_wlan_in: wlan-wpss-to-ap { 780 qcom,entry-name = "wlan"; 781 interrupt-controller; 782 #interrupt-cells = <2>; 783 }; 784 }; 785 786 soc: soc@0 { 787 compatible = "simple-bus"; 788 789 #address-cells = <2>; 790 #size-cells = <2>; 791 dma-ranges = <0 0 0 0 0x10 0>; 792 ranges = <0 0 0 0 0x10 0>; 793 794 gcc: clock-controller@100000 { 795 compatible = "qcom,milos-gcc"; 796 reg = <0x0 0x00100000 0x0 0x1f4200>; 797 798 clocks = <&rpmhcc RPMH_CXO_CLK>, 799 <&sleep_clk>, 800 <0>, /* pcie_0_pipe_clk */ 801 <0>, /* pcie_1_pipe_clk */ 802 <&ufs_mem_phy 0>, 803 <&ufs_mem_phy 1>, 804 <&ufs_mem_phy 2>, 805 <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */ 806 807 power-domains = <&rpmhpd RPMHPD_CX>; 808 809 #clock-cells = <1>; 810 #reset-cells = <1>; 811 #power-domain-cells = <1>; 812 }; 813 814 ipcc: mailbox@405000 { 815 compatible = "qcom,milos-ipcc", "qcom,ipcc"; 816 reg = <0x0 0x00405000 0x0 0x1000>; 817 818 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>; 819 interrupt-controller; 820 #interrupt-cells = <3>; 821 822 #mbox-cells = <2>; 823 }; 824 825 gpi_dma1: dma-controller@800000 { 826 compatible = "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma"; 827 reg = <0x0 0x00800000 0x0 0x60000>; 828 829 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>, 830 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>, 831 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, 832 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, 833 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, 834 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, 835 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, 836 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 0>, 837 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH 0>, 838 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>, 839 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>, 840 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 841 842 dma-channels = <12>; 843 dma-channel-mask = <0x3f>; 844 #dma-cells = <3>; 845 846 iommus = <&apps_smmu 0x36 0x0>; 847 dma-coherent; 848 }; 849 850 qupv3_id_1: geniqup@8c0000 { 851 compatible = "qcom,geni-se-qup"; 852 reg = <0x0 0x008c0000 0x0 0x2000>; 853 854 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 855 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 856 clock-names = "m-ahb", 857 "s-ahb"; 858 859 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 860 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 861 interconnect-names = "qup-core"; 862 863 iommus = <&apps_smmu 0x23 0>; 864 865 dma-coherent; 866 867 #address-cells = <2>; 868 #size-cells = <2>; 869 ranges; 870 871 status = "disabled"; 872 873 i2c7: i2c@880000 { 874 compatible = "qcom,geni-i2c"; 875 reg = <0x0 0x00880000 0x0 0x4000>; 876 877 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 878 879 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 880 clock-names = "se"; 881 882 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 883 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 884 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 885 &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 886 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 887 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 888 interconnect-names = "qup-core", 889 "qup-config", 890 "qup-memory"; 891 892 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 893 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 894 dma-names = "tx", 895 "rx"; 896 897 pinctrl-0 = <&qup_i2c7_data_clk>; 898 pinctrl-names = "default"; 899 900 #address-cells = <1>; 901 #size-cells = <0>; 902 903 status = "disabled"; 904 }; 905 906 uart11: serial@890000 { 907 compatible = "qcom,geni-uart"; 908 reg = <0x0 0x00890000 0x0 0x4000>; 909 910 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 911 912 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 913 clock-names = "se"; 914 915 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 916 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 917 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 918 &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 919 interconnect-names = "qup-core", 920 "qup-config"; 921 922 pinctrl-0 = <&qup_uart11_default>, <&qup_uart11_cts_rts>; 923 pinctrl-names = "default"; 924 925 status = "disabled"; 926 }; 927 }; 928 929 gpi_dma0: dma-controller@a00000 { 930 compatible = "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma"; 931 reg = <0x0 0x00a00000 0x0 0x60000>; 932 933 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH 0>, 934 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, 935 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, 936 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, 937 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>, 938 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, 939 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>, 940 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, 941 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, 942 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>, 943 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>, 944 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>; 945 946 dma-channels = <12>; 947 dma-channel-mask = <0x3e>; 948 #dma-cells = <3>; 949 950 iommus = <&apps_smmu 0x576 0x0>; 951 dma-coherent; 952 }; 953 954 qupv3_id_0: geniqup@ac0000 { 955 compatible = "qcom,geni-se-qup"; 956 reg = <0x0 0x00ac0000 0x0 0x2000>; 957 958 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 959 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 960 clock-names = "m-ahb", 961 "s-ahb"; 962 963 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 964 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; 965 interconnect-names = "qup-core"; 966 967 iommus = <&apps_smmu 0x563 0>; 968 969 dma-coherent; 970 971 #address-cells = <2>; 972 #size-cells = <2>; 973 ranges; 974 975 status = "disabled"; 976 977 spi0: spi@a80000 { 978 compatible = "qcom,geni-spi"; 979 reg = <0x0 0x00a80000 0x0 0x4000>; 980 981 interrupts = <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>; 982 983 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 984 clock-names = "se"; 985 986 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 987 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 988 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 989 &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 990 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 991 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 992 interconnect-names = "qup-core", 993 "qup-config", 994 "qup-memory"; 995 996 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 997 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 998 dma-names = "tx", 999 "rx"; 1000 1001 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1002 pinctrl-names = "default"; 1003 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 1007 status = "disabled"; 1008 }; 1009 1010 i2c1: i2c@a84000 { 1011 compatible = "qcom,geni-i2c"; 1012 reg = <0x0 0x00a84000 0x0 0x4000>; 1013 1014 interrupts = <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH 0>; 1015 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1017 clock-names = "se"; 1018 1019 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1020 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1021 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1022 &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 1023 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1024 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1025 interconnect-names = "qup-core", 1026 "qup-config", 1027 "qup-memory"; 1028 1029 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1030 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1031 dma-names = "tx", 1032 "rx"; 1033 1034 pinctrl-0 = <&qup_i2c1_data_clk>; 1035 pinctrl-names = "default"; 1036 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 1040 status = "disabled"; 1041 }; 1042 1043 i2c3: i2c@a8c000 { 1044 compatible = "qcom,geni-i2c"; 1045 reg = <0x0 0x00a8c000 0x0 0x4000>; 1046 1047 interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH 0>; 1048 1049 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1050 clock-names = "se"; 1051 1052 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1053 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1054 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1055 &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 1056 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1057 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1058 interconnect-names = "qup-core", 1059 "qup-config", 1060 "qup-memory"; 1061 1062 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1063 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1064 dma-names = "tx", 1065 "rx"; 1066 1067 pinctrl-0 = <&qup_i2c3_data_clk>; 1068 pinctrl-names = "default"; 1069 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 1073 status = "disabled"; 1074 }; 1075 1076 uart5: serial@a94000 { 1077 compatible = "qcom,geni-debug-uart"; 1078 reg = <0x0 0x00a94000 0x0 0x4000>; 1079 1080 interrupts = <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH 0>; 1081 1082 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1083 clock-names = "se"; 1084 1085 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1086 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1087 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1088 &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1089 interconnect-names = "qup-core", 1090 "qup-config"; 1091 1092 pinctrl-0 = <&qup_uart5_default>; 1093 pinctrl-names = "default"; 1094 1095 status = "disabled"; 1096 }; 1097 }; 1098 1099 rng: rng@10c3000 { 1100 compatible = "qcom,milos-trng", "qcom,trng"; 1101 reg = <0x0 0x010c3000 0x0 0x1000>; 1102 }; 1103 1104 mmss_noc: interconnect@1400000 { 1105 compatible = "qcom,milos-mmss-noc"; 1106 reg = <0x0 0x01400000 0x0 0xdb800>; 1107 #interconnect-cells = <2>; 1108 qcom,bcm-voters = <&apps_bcm_voter>; 1109 }; 1110 1111 cnoc_main: interconnect@1500000 { 1112 compatible = "qcom,milos-cnoc-main"; 1113 reg = <0x0 0x01500000 0x0 0x14400>; 1114 #interconnect-cells = <2>; 1115 qcom,bcm-voters = <&apps_bcm_voter>; 1116 }; 1117 1118 cnoc_cfg: interconnect@1600000 { 1119 compatible = "qcom,milos-cnoc-cfg"; 1120 reg = <0x0 0x01600000 0x0 0x6e00>; 1121 #interconnect-cells = <2>; 1122 qcom,bcm-voters = <&apps_bcm_voter>; 1123 }; 1124 1125 system_noc: interconnect@1680000 { 1126 compatible = "qcom,milos-system-noc"; 1127 reg = <0x0 0x01680000 0x0 0x40000>; 1128 #interconnect-cells = <2>; 1129 qcom,bcm-voters = <&apps_bcm_voter>; 1130 }; 1131 1132 pcie_anoc: interconnect@16c0000 { 1133 compatible = "qcom,milos-pcie-anoc"; 1134 reg = <0x0 0x016c0000 0x0 0x12400>; 1135 #interconnect-cells = <2>; 1136 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1137 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1138 qcom,bcm-voters = <&apps_bcm_voter>; 1139 }; 1140 1141 aggre1_noc: interconnect@16e0000 { 1142 compatible = "qcom,milos-aggre1-noc"; 1143 reg = <0x0 0x016e0000 0x0 0x16400>; 1144 #interconnect-cells = <2>; 1145 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1146 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 1147 qcom,bcm-voters = <&apps_bcm_voter>; 1148 }; 1149 1150 aggre2_noc: interconnect@1700000 { 1151 compatible = "qcom,milos-aggre2-noc"; 1152 reg = <0x0 0x01700000 0x0 0x1f400>; 1153 #interconnect-cells = <2>; 1154 clocks = <&rpmhcc RPMH_IPA_CLK>; 1155 qcom,bcm-voters = <&apps_bcm_voter>; 1156 }; 1157 1158 ufs_mem_phy: phy@1d80000 { 1159 compatible = "qcom,milos-qmp-ufs-phy"; 1160 reg = <0x0 0x01d80000 0x0 0x2000>; 1161 1162 clocks = <&rpmhcc RPMH_CXO_CLK>, 1163 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1164 <&tcsr TCSR_UFS_CLKREF_EN>; 1165 clock-names = "ref", 1166 "ref_aux", 1167 "qref"; 1168 1169 resets = <&ufs_mem_hc 0>; 1170 reset-names = "ufsphy"; 1171 1172 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1173 1174 #clock-cells = <1>; 1175 #phy-cells = <0>; 1176 1177 status = "disabled"; 1178 }; 1179 1180 ufs_mem_hc: ufshc@1d84000 { 1181 compatible = "qcom,milos-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1182 reg = <0x0 0x01d84000 0x0 0x3000>; 1183 1184 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 1185 1186 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1187 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1188 <&gcc GCC_UFS_PHY_AHB_CLK>, 1189 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1190 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 1191 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1192 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1193 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1194 clock-names = "core_clk", 1195 "bus_aggr_clk", 1196 "iface_clk", 1197 "core_clk_unipro", 1198 "ref_clk", 1199 "tx_lane0_sync_clk", 1200 "rx_lane0_sync_clk", 1201 "rx_lane1_sync_clk"; 1202 1203 resets = <&gcc GCC_UFS_PHY_BCR>; 1204 reset-names = "rst"; 1205 1206 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1207 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1208 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1209 &cnoc_cfg SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 1210 interconnect-names = "ufs-ddr", 1211 "cpu-ufs"; 1212 1213 power-domains = <&gcc UFS_PHY_GDSC>; 1214 required-opps = <&rpmhpd_opp_nom>; 1215 1216 operating-points-v2 = <&ufs_opp_table>; 1217 1218 iommus = <&apps_smmu 0x60 0>; 1219 1220 dma-coherent; 1221 1222 lanes-per-direction = <2>; 1223 qcom,ice = <&ice>; 1224 1225 phys = <&ufs_mem_phy>; 1226 phy-names = "ufsphy"; 1227 1228 #reset-cells = <1>; 1229 1230 status = "disabled"; 1231 1232 ufs_opp_table: opp-table { 1233 compatible = "operating-points-v2"; 1234 1235 opp-75000000 { 1236 opp-hz = /bits/ 64 <75000000>, 1237 /bits/ 64 <0>, 1238 /bits/ 64 <0>, 1239 /bits/ 64 <75000000>, 1240 /bits/ 64 <0>, 1241 /bits/ 64 <0>, 1242 /bits/ 64 <0>, 1243 /bits/ 64 <0>; 1244 required-opps = <&rpmhpd_opp_low_svs>; 1245 }; 1246 1247 opp-150000000 { 1248 opp-hz = /bits/ 64 <150000000>, 1249 /bits/ 64 <0>, 1250 /bits/ 64 <0>, 1251 /bits/ 64 <150000000>, 1252 /bits/ 64 <0>, 1253 /bits/ 64 <0>, 1254 /bits/ 64 <0>, 1255 /bits/ 64 <0>; 1256 required-opps = <&rpmhpd_opp_svs>; 1257 }; 1258 1259 opp-300000000 { 1260 opp-hz = /bits/ 64 <300000000>, 1261 /bits/ 64 <0>, 1262 /bits/ 64 <0>, 1263 /bits/ 64 <300000000>, 1264 /bits/ 64 <0>, 1265 /bits/ 64 <0>, 1266 /bits/ 64 <0>, 1267 /bits/ 64 <0>; 1268 required-opps = <&rpmhpd_opp_nom>; 1269 }; 1270 }; 1271 }; 1272 1273 ice: crypto@1d88000 { 1274 compatible = "qcom,milos-inline-crypto-engine", 1275 "qcom,inline-crypto-engine"; 1276 reg = <0x0 0x01d88000 0x0 0x18000>; 1277 1278 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, 1279 <&gcc GCC_UFS_PHY_AHB_CLK>; 1280 clock-names = "core", 1281 "iface"; 1282 power-domains = <&gcc UFS_PHY_GDSC>; 1283 }; 1284 1285 tcsr_mutex: hwlock@1f40000 { 1286 compatible = "qcom,tcsr-mutex"; 1287 reg = <0x0 0x01f40000 0x0 0x20000>; 1288 1289 #hwlock-cells = <1>; 1290 }; 1291 1292 tcsr: clock-controller@1fc0000 { 1293 compatible = "qcom,milos-tcsr", "syscon"; 1294 reg = <0x0 0x01fc0000 0x0 0xa0000>; 1295 1296 clocks = <&rpmhcc RPMH_CXO_CLK>; 1297 1298 #clock-cells = <1>; 1299 #reset-cells = <1>; 1300 }; 1301 1302 remoteproc_adsp: remoteproc@3000000 { 1303 compatible = "qcom,milos-adsp-pas"; 1304 reg = <0x0 0x03000000 0x0 0x10000>; 1305 1306 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1307 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1308 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1309 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1310 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 1311 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 1312 interrupt-names = "wdog", 1313 "fatal", 1314 "ready", 1315 "handover", 1316 "stop-ack", 1317 "shutdown-ack"; 1318 1319 clocks = <&rpmhcc RPMH_CXO_CLK>; 1320 clock-names = "xo"; 1321 1322 power-domains = <&rpmhpd RPMHPD_LCX>, 1323 <&rpmhpd RPMHPD_LMX>; 1324 power-domain-names = "lcx", 1325 "lmx"; 1326 1327 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 1328 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1329 1330 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 1331 1332 qcom,qmp = <&aoss_qmp>; 1333 1334 qcom,smem-states = <&smp2p_adsp_out 0>; 1335 qcom,smem-state-names = "stop"; 1336 1337 status = "disabled"; 1338 1339 glink-edge { 1340 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1341 IPCC_MPROC_SIGNAL_GLINK_QMP 1342 IRQ_TYPE_EDGE_RISING>; 1343 mboxes = <&ipcc IPCC_CLIENT_LPASS 1344 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1345 1346 label = "lpass"; 1347 qcom,remote-pid = <2>; 1348 1349 fastrpc { 1350 compatible = "qcom,fastrpc"; 1351 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1352 label = "adsp"; 1353 qcom,non-secure-domain; 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 1357 compute-cb@3 { 1358 compatible = "qcom,fastrpc-compute-cb"; 1359 reg = <3>; 1360 iommus = <&apps_smmu 0x1003 0x0>, 1361 <&apps_smmu 0x1063 0x0>; 1362 dma-coherent; 1363 }; 1364 1365 compute-cb@4 { 1366 compatible = "qcom,fastrpc-compute-cb"; 1367 reg = <4>; 1368 iommus = <&apps_smmu 0x1004 0x0>, 1369 <&apps_smmu 0x1064 0x0>; 1370 dma-coherent; 1371 }; 1372 1373 compute-cb@5 { 1374 compatible = "qcom,fastrpc-compute-cb"; 1375 reg = <5>; 1376 iommus = <&apps_smmu 0x1005 0x0>, 1377 <&apps_smmu 0x1065 0x0>; 1378 dma-coherent; 1379 }; 1380 1381 compute-cb@6 { 1382 compatible = "qcom,fastrpc-compute-cb"; 1383 reg = <6>; 1384 iommus = <&apps_smmu 0x1006 0x0>, 1385 <&apps_smmu 0x1066 0x0>; 1386 dma-coherent; 1387 }; 1388 1389 compute-cb@7 { 1390 compatible = "qcom,fastrpc-compute-cb"; 1391 reg = <7>; 1392 iommus = <&apps_smmu 0x1007 0x0>, 1393 <&apps_smmu 0x1067 0x0>; 1394 dma-coherent; 1395 }; 1396 }; 1397 1398 gpr { 1399 compatible = "qcom,gpr"; 1400 qcom,glink-channels = "adsp_apps"; 1401 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 1402 qcom,intents = <512 20>; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 1406 q6apm: service@1 { 1407 compatible = "qcom,q6apm"; 1408 reg = <GPR_APM_MODULE_IID>; 1409 #sound-dai-cells = <0>; 1410 qcom,protection-domain = "avs/audio", 1411 "msm/adsp/audio_pd"; 1412 1413 q6apmbedai: bedais { 1414 compatible = "qcom,q6apm-lpass-dais"; 1415 #sound-dai-cells = <1>; 1416 }; 1417 1418 q6apmdai: dais { 1419 compatible = "qcom,q6apm-dais"; 1420 iommus = <&apps_smmu 0x1001 0x0>, 1421 <&apps_smmu 0x1061 0x0>; 1422 }; 1423 }; 1424 1425 q6prm: service@2 { 1426 compatible = "qcom,q6prm"; 1427 reg = <GPR_PRM_MODULE_IID>; 1428 qcom,protection-domain = "avs/audio", 1429 "msm/adsp/audio_pd"; 1430 1431 q6prmcc: clock-controller { 1432 compatible = "qcom,q6prm-lpass-clocks"; 1433 #clock-cells = <2>; 1434 }; 1435 }; 1436 }; 1437 }; 1438 }; 1439 1440 lpass_tlmm: pinctrl@3440000 { 1441 compatible = "qcom,milos-lpass-lpi-pinctrl"; 1442 reg = <0x0 0x03440000 0x0 0x20000>, 1443 <0x0 0x034d0000 0x0 0x10000>; 1444 gpio-controller; 1445 #gpio-cells = <2>; 1446 gpio-ranges = <&lpass_tlmm 0 0 23>; 1447 1448 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1449 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1450 clock-names = "core", 1451 "audio"; 1452 1453 tx_swr_active: tx-swr-active-state { 1454 clk-pins { 1455 pins = "gpio0"; 1456 function = "swr_tx_clk"; 1457 drive-strength = <4>; 1458 slew-rate = <1>; 1459 bias-disable; 1460 }; 1461 1462 data-pins { 1463 pins = "gpio1", "gpio2", "gpio14"; 1464 function = "swr_tx_data"; 1465 drive-strength = <4>; 1466 slew-rate = <1>; 1467 bias-bus-hold; 1468 }; 1469 }; 1470 1471 rx_swr_active: rx-swr-active-state { 1472 clk-pins { 1473 pins = "gpio3"; 1474 function = "swr_rx_clk"; 1475 drive-strength = <2>; 1476 slew-rate = <1>; 1477 bias-disable; 1478 }; 1479 1480 data-pins { 1481 pins = "gpio4", "gpio5"; 1482 function = "swr_rx_data"; 1483 drive-strength = <2>; 1484 slew-rate = <1>; 1485 bias-bus-hold; 1486 }; 1487 }; 1488 1489 lpi_i2s2_active: lpi-i2s2-active-state { 1490 clk-pins { 1491 pins = "gpio10"; 1492 function = "i2s2_clk"; 1493 drive-strength = <8>; 1494 bias-disable; 1495 output-high; 1496 }; 1497 1498 ws-pins { 1499 pins = "gpio11"; 1500 function = "i2s2_ws"; 1501 drive-strength = <8>; 1502 bias-disable; 1503 output-high; 1504 }; 1505 1506 data-pins { 1507 pins = "gpio12", "gpio13"; 1508 function = "i2s2_data"; 1509 drive-strength = <8>; 1510 bias-disable; 1511 output-high; 1512 }; 1513 }; 1514 1515 lpi_i2s2_sleep: lpi-i2s2-sleep-state { 1516 clk-pins { 1517 pins = "gpio10"; 1518 function = "i2s2_clk"; 1519 drive-strength = <2>; 1520 bias-pull-down; 1521 input-enable; 1522 }; 1523 1524 ws-pins { 1525 pins = "gpio11"; 1526 function = "i2s2_ws"; 1527 drive-strength = <2>; 1528 bias-pull-down; 1529 input-enable; 1530 }; 1531 1532 data-pins { 1533 pins = "gpio12", "gpio13"; 1534 function = "i2s2_data"; 1535 drive-strength = <2>; 1536 bias-pull-down; 1537 input-enable; 1538 }; 1539 }; 1540 }; 1541 1542 lpass_ag_noc: interconnect@3c40000 { 1543 compatible = "qcom,milos-lpass-ag-noc"; 1544 reg = <0x0 0x03c40000 0x0 0x17200>; 1545 #interconnect-cells = <2>; 1546 qcom,bcm-voters = <&apps_bcm_voter>; 1547 }; 1548 1549 gpucc: clock-controller@3d90000 { 1550 compatible = "qcom,milos-gpucc"; 1551 reg = <0x0 0x03d90000 0x0 0x9800>; 1552 1553 clocks = <&rpmhcc RPMH_CXO_CLK>, 1554 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1555 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1556 1557 #clock-cells = <1>; 1558 #reset-cells = <1>; 1559 #power-domain-cells = <1>; 1560 }; 1561 1562 adreno_smmu: iommu@3da0000 { 1563 compatible = "qcom,milos-smmu-500", "qcom,adreno-smmu", 1564 "qcom,smmu-500", "arm,mmu-500"; 1565 reg = <0x0 0x03da0000 0x0 0x40000>; 1566 #iommu-cells = <2>; 1567 #global-interrupts = <1>; 1568 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>, 1569 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>, 1570 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>, 1571 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>, 1572 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>, 1573 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>, 1574 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>, 1575 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>, 1576 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>, 1577 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>, 1578 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>, 1579 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>, 1580 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>, 1581 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>, 1582 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>, 1583 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>, 1584 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>, 1585 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>, 1586 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>, 1587 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>, 1588 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, 1589 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>, 1590 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>, 1591 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>, 1592 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>, 1593 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>; 1594 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1595 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1596 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1597 <&gpucc GPU_CC_AHB_CLK>; 1598 clock-names = "hlos", 1599 "bus", 1600 "iface", 1601 "ahb"; 1602 power-domains = <&gpucc GPU_CC_CX_GDSC>; 1603 dma-coherent; 1604 }; 1605 1606 remoteproc_mpss: remoteproc@4080000 { 1607 compatible = "qcom,milos-mpss-pas"; 1608 reg = <0x0 0x04080000 0x0 0x10000>; 1609 1610 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, 1611 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1612 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1613 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1614 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1615 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1616 interrupt-names = "wdog", 1617 "fatal", 1618 "ready", 1619 "handover", 1620 "stop-ack", 1621 "shutdown-ack"; 1622 1623 clocks = <&rpmhcc RPMH_CXO_CLK>; 1624 clock-names = "xo"; 1625 1626 power-domains = <&rpmhpd RPMHPD_CX>, 1627 <&rpmhpd RPMHPD_MSS>; 1628 power-domain-names = "cx", 1629 "mss"; 1630 1631 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 1632 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1633 1634 memory-region = <&mpss_mem>; 1635 1636 qcom,qmp = <&aoss_qmp>; 1637 1638 qcom,smem-states = <&smp2p_modem_out 0>; 1639 qcom,smem-state-names = "stop"; 1640 1641 status = "disabled"; 1642 1643 glink-edge { 1644 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1645 IPCC_MPROC_SIGNAL_GLINK_QMP 1646 IRQ_TYPE_EDGE_RISING>; 1647 mboxes = <&ipcc IPCC_CLIENT_MPSS 1648 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1649 1650 label = "mpss"; 1651 qcom,remote-pid = <1>; 1652 }; 1653 }; 1654 1655 sdhc_2: mmc@8804000 { 1656 compatible = "qcom,milos-sdhci", "qcom,sdhci-msm-v5"; 1657 reg = <0x0 0x08804000 0x0 0x1000>; 1658 1659 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>, 1660 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>; 1661 interrupt-names = "hc_irq", 1662 "pwr_irq"; 1663 1664 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1665 <&gcc GCC_SDCC2_APPS_CLK>, 1666 <&rpmhcc RPMH_CXO_CLK>; 1667 clock-names = "iface", 1668 "core", 1669 "xo"; 1670 1671 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 1672 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1673 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1674 &cnoc_cfg SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1675 interconnect-names = "sdhc-ddr", 1676 "cpu-sdhc"; 1677 1678 power-domains = <&rpmhpd RPMHPD_CX>; 1679 operating-points-v2 = <&sdhc2_opp_table>; 1680 1681 iommus = <&apps_smmu 0x540 0>; 1682 1683 bus-width = <4>; 1684 1685 qcom,dll-config = <0x0007442c>; 1686 qcom,ddr-config = <0x80040868>; 1687 1688 dma-coherent; 1689 1690 status = "disabled"; 1691 1692 sdhc2_opp_table: opp-table { 1693 compatible = "operating-points-v2"; 1694 1695 opp-100000000 { 1696 opp-hz = /bits/ 64 <100000000>; 1697 required-opps = <&rpmhpd_opp_low_svs>; 1698 }; 1699 1700 opp-202000000 { 1701 opp-hz = /bits/ 64 <202000000>; 1702 required-opps = <&rpmhpd_opp_svs_l1>; 1703 }; 1704 }; 1705 }; 1706 1707 usb_1_hsphy: phy@88e3000 { 1708 compatible = "qcom,milos-snps-eusb2-phy", 1709 "qcom,sm8550-snps-eusb2-phy"; 1710 reg = <0x0 0x088e3000 0x0 0x154>; 1711 #phy-cells = <0>; 1712 1713 clocks = <&rpmhcc RPMH_CXO_CLK>; 1714 clock-names = "ref"; 1715 1716 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1717 1718 status = "disabled"; 1719 }; 1720 1721 remoteproc_wpss: remoteproc@8a00000 { 1722 compatible = "qcom,milos-wpss-pas"; 1723 reg = <0x0 0x08a00000 0x0 0x10000>; 1724 1725 interrupts-extended = <&intc GIC_SPI 579 IRQ_TYPE_EDGE_RISING 0>, 1726 <&smp2p_wpss_in 0 IRQ_TYPE_EDGE_RISING>, 1727 <&smp2p_wpss_in 1 IRQ_TYPE_EDGE_RISING>, 1728 <&smp2p_wpss_in 2 IRQ_TYPE_EDGE_RISING>, 1729 <&smp2p_wpss_in 3 IRQ_TYPE_EDGE_RISING>, 1730 <&smp2p_wpss_in 7 IRQ_TYPE_EDGE_RISING>; 1731 interrupt-names = "wdog", 1732 "fatal", 1733 "ready", 1734 "handover", 1735 "stop-ack", 1736 "shutdown-ack"; 1737 1738 clocks = <&rpmhcc RPMH_CXO_CLK>; 1739 clock-names = "xo"; 1740 1741 power-domains = <&rpmhpd RPMHPD_CX>, 1742 <&rpmhpd RPMHPD_MX>; 1743 power-domain-names = "cx", 1744 "mx"; 1745 1746 memory-region = <&wpss_mem>; 1747 1748 qcom,qmp = <&aoss_qmp>; 1749 1750 qcom,smem-states = <&smp2p_wpss_out 0>; 1751 qcom,smem-state-names = "stop"; 1752 1753 status = "disabled"; 1754 1755 glink-edge { 1756 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 1757 IPCC_MPROC_SIGNAL_GLINK_QMP 1758 IRQ_TYPE_EDGE_RISING>; 1759 mboxes = <&ipcc IPCC_CLIENT_WPSS 1760 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1761 1762 label = "wpss"; 1763 qcom,remote-pid = <13>; 1764 }; 1765 }; 1766 1767 usb_1: usb@a600000 { 1768 compatible = "qcom,milos-dwc3", "qcom,snps-dwc3"; 1769 reg = <0x0 0x0a600000 0x0 0xfc000>; 1770 1771 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1772 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1773 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1774 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1775 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1776 <&rpmhcc RPMH_CXO_CLK>; 1777 clock-names = "cfg_noc", 1778 "core", 1779 "iface", 1780 "sleep", 1781 "mock_utmi", 1782 "xo"; 1783 1784 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1785 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1786 assigned-clock-rates = <19200000>, <200000000>; 1787 1788 interrupts-extended = <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 0>, 1789 <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 0>, 1790 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1791 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1792 <&pdc 25 IRQ_TYPE_LEVEL_HIGH>; 1793 interrupt-names = "dwc_usb3", 1794 "pwr_event", 1795 "dp_hs_phy_irq", 1796 "dm_hs_phy_irq", 1797 "ss_phy_irq"; 1798 1799 iommus = <&apps_smmu 0x40 0x0>; 1800 power-domains = <&gcc USB30_PRIM_GDSC>; 1801 required-opps = <&rpmhpd_opp_nom>; 1802 1803 resets = <&gcc GCC_USB30_PRIM_BCR>; 1804 1805 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 1806 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1807 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1808 &cnoc_cfg SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1809 interconnect-names = "usb-ddr", "apps-usb"; 1810 1811 phys = <&usb_1_hsphy>; 1812 phy-names = "usb2-phy"; 1813 1814 snps,dis-u1-entry-quirk; 1815 snps,dis-u2-entry-quirk; 1816 snps,dis_enblslpm_quirk; 1817 snps,dis_u2_susphy_quirk; 1818 snps,dis_u3_susphy_quirk; 1819 snps,has-lpm-erratum; 1820 snps,hird-threshold = /bits/ 8 <0x0>; 1821 snps,is-utmi-l1-suspend; 1822 snps,parkmode-disable-ss-quirk; 1823 tx-fifo-resize; 1824 dma-coherent; 1825 usb-role-switch; 1826 1827 status = "disabled"; 1828 1829 ports { 1830 #address-cells = <1>; 1831 #size-cells = <0>; 1832 1833 port@0 { 1834 reg = <0>; 1835 1836 usb_1_dwc3_hs: endpoint { 1837 }; 1838 }; 1839 }; 1840 }; 1841 1842 videocc: clock-controller@aaf0000 { 1843 compatible = "qcom,milos-videocc"; 1844 reg = <0x0 0x0aaf0000 0x0 0x10000>; 1845 1846 clocks = <&rpmhcc RPMH_CXO_CLK>, 1847 <&rpmhcc RPMH_CXO_CLK_A>, 1848 <&sleep_clk>, 1849 <&gcc GCC_VIDEO_AHB_CLK>; 1850 1851 #clock-cells = <1>; 1852 #reset-cells = <1>; 1853 #power-domain-cells = <1>; 1854 }; 1855 1856 cci0: cci@ac15000 { 1857 compatible = "qcom,milos-cci", "qcom,msm8996-cci"; 1858 reg = <0x0 0x0ac15000 0x0 0x1000>; 1859 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>; 1860 power-domains = <&camcc CAM_CC_CAMSS_TOP_GDSC>; 1861 clocks = <&camcc CAM_CC_SOC_AHB_CLK>, 1862 <&camcc CAM_CC_CPAS_AHB_CLK>, 1863 <&camcc CAM_CC_CCI_0_CLK>; 1864 clock-names = "soc_ahb", 1865 "cpas_ahb", 1866 "cci"; 1867 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 1868 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 1869 pinctrl-names = "default", "sleep"; 1870 status = "disabled"; 1871 #address-cells = <1>; 1872 #size-cells = <0>; 1873 1874 cci0_i2c0: i2c-bus@0 { 1875 reg = <0>; 1876 clock-frequency = <1000000>; 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 }; 1880 1881 cci0_i2c1: i2c-bus@1 { 1882 reg = <1>; 1883 clock-frequency = <1000000>; 1884 #address-cells = <1>; 1885 #size-cells = <0>; 1886 }; 1887 }; 1888 1889 cci1: cci@ac16000 { 1890 compatible = "qcom,milos-cci", "qcom,msm8996-cci"; 1891 reg = <0x0 0x0ac16000 0x0 0x1000>; 1892 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING 0>; 1893 power-domains = <&camcc CAM_CC_CAMSS_TOP_GDSC>; 1894 clocks = <&camcc CAM_CC_SOC_AHB_CLK>, 1895 <&camcc CAM_CC_CPAS_AHB_CLK>, 1896 <&camcc CAM_CC_CCI_1_CLK>; 1897 clock-names = "soc_ahb", 1898 "cpas_ahb", 1899 "cci"; 1900 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 1901 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 1902 pinctrl-names = "default", "sleep"; 1903 status = "disabled"; 1904 #address-cells = <1>; 1905 #size-cells = <0>; 1906 1907 cci1_i2c0: i2c-bus@0 { 1908 reg = <0>; 1909 clock-frequency = <1000000>; 1910 #address-cells = <1>; 1911 #size-cells = <0>; 1912 }; 1913 1914 cci1_i2c1: i2c-bus@1 { 1915 reg = <1>; 1916 clock-frequency = <1000000>; 1917 #address-cells = <1>; 1918 #size-cells = <0>; 1919 }; 1920 }; 1921 1922 camcc: clock-controller@adb0000 { 1923 compatible = "qcom,milos-camcc"; 1924 reg = <0x0 0x0adb0000 0x0 0x40000>; 1925 1926 clocks = <&rpmhcc RPMH_CXO_CLK>, 1927 <&sleep_clk>, 1928 <&gcc GCC_CAMERA_AHB_CLK>; 1929 1930 #clock-cells = <1>; 1931 #reset-cells = <1>; 1932 #power-domain-cells = <1>; 1933 }; 1934 1935 dispcc: clock-controller@af00000 { 1936 compatible = "qcom,milos-dispcc"; 1937 reg = <0x0 0x0af00000 0x0 0x20000>; 1938 1939 clocks = <&rpmhcc RPMH_CXO_CLK>, 1940 <&sleep_clk>, 1941 <&gcc GCC_DISP_AHB_CLK>, 1942 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 1943 <0>, /* dsi0_phy_pll_out_byteclk */ 1944 <0>, /* dsi0_phy_pll_out_dsiclk */ 1945 <0>, /* dp0_phy_pll_link_clk */ 1946 <0>; /* dp0_phy_pll_vco_div_clk */ 1947 1948 #clock-cells = <1>; 1949 #reset-cells = <1>; 1950 #power-domain-cells = <1>; 1951 }; 1952 1953 pdc: interrupt-controller@b220000 { 1954 compatible = "qcom,milos-pdc", "qcom,pdc"; 1955 reg = <0x0 0x0b220000 0x0 0x30000>, 1956 <0x0 0x174000f0 0x0 0x64>; 1957 interrupt-parent = <&intc>; 1958 1959 qcom,pdc-ranges = <0 480 40>, <40 140 11>, <51 527 47>, 1960 <98 609 31>, <129 63 1>, <130 716 12>, 1961 <142 251 5>; 1962 1963 #interrupt-cells = <2>; 1964 interrupt-controller; 1965 }; 1966 1967 tsens0: thermal-sensor@c228000 { 1968 compatible = "qcom,milos-tsens", "qcom,tsens-v2"; 1969 reg = <0x0 0x0c228000 0x0 0x1000>, 1970 <0x0 0x0c222000 0x0 0x1000>; 1971 1972 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1973 <&intc GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 1974 interrupt-names = "uplow", 1975 "critical"; 1976 1977 #qcom,sensors = <15>; 1978 1979 #thermal-sensor-cells = <1>; 1980 }; 1981 1982 tsens1: thermal-sensor@c229000 { 1983 compatible = "qcom,milos-tsens", "qcom,tsens-v2"; 1984 reg = <0x0 0x0c229000 0x0 0x1000>, 1985 <0x0 0x0c223000 0x0 0x1000>; 1986 1987 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1988 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 1989 interrupt-names = "uplow", 1990 "critical"; 1991 1992 #qcom,sensors = <14>; 1993 1994 #thermal-sensor-cells = <1>; 1995 }; 1996 1997 aoss_qmp: power-management@c300000 { 1998 compatible = "qcom,milos-aoss-qmp", "qcom,aoss-qmp"; 1999 reg = <0x0 0x0c300000 0x0 0x400>; 2000 2001 interrupt-parent = <&ipcc>; 2002 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2003 IRQ_TYPE_EDGE_RISING>; 2004 2005 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2006 2007 #clock-cells = <0>; 2008 }; 2009 2010 sram@c3f0000 { 2011 compatible = "qcom,rpmh-stats"; 2012 reg = <0x0 0x0c3f0000 0x0 0x400>; 2013 }; 2014 2015 spmi_bus: spmi@c400000 { 2016 compatible = "qcom,spmi-pmic-arb"; 2017 reg = <0x0 0x0c400000 0x0 0x3000>, 2018 <0x0 0x0c500000 0x0 0x400000>, 2019 <0x0 0x0c440000 0x0 0x80000>, 2020 <0x0 0x0c4c0000 0x0 0x10000>, 2021 <0x0 0x0c42d000 0x0 0x4000>; 2022 reg-names = "core", 2023 "chnls", 2024 "obsrvr", 2025 "intr", 2026 "cnfg"; 2027 2028 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2029 interrupt-names = "periph_irq"; 2030 2031 qcom,ee = <0>; 2032 qcom,channel = <0>; 2033 qcom,bus-id = <0>; 2034 2035 interrupt-controller; 2036 #interrupt-cells = <4>; 2037 2038 #address-cells = <2>; 2039 #size-cells = <0>; 2040 }; 2041 2042 tlmm: pinctrl@f100000 { 2043 compatible = "qcom,milos-tlmm"; 2044 reg = <0x0 0x0f100000 0x0 0x300000>; 2045 2046 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; 2047 2048 gpio-controller; 2049 #gpio-cells = <2>; 2050 2051 interrupt-controller; 2052 #interrupt-cells = <2>; 2053 2054 gpio-ranges = <&tlmm 0 0 168>; 2055 2056 wakeup-parent = <&pdc>; 2057 2058 qup_spi0_data_clk: qup-spi0-data-clk-state { 2059 /* MISO, MOSI, CLK */ 2060 pins = "gpio0", "gpio1", "gpio2"; 2061 function = "qup0_se0"; 2062 drive-strength = <6>; 2063 bias-disable; 2064 }; 2065 2066 qup_spi0_cs: qup-spi0-cs-state { 2067 pins = "gpio3"; 2068 function = "qup0_se0"; 2069 drive-strength = <6>; 2070 bias-disable; 2071 }; 2072 2073 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2074 /* SDA, SCL */ 2075 pins = "gpio4", "gpio5"; 2076 function = "qup0_se1"; 2077 drive-strength = <2>; 2078 bias-pull-up; 2079 }; 2080 2081 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2082 /* SDA, SCL */ 2083 pins = "gpio15", "gpio16"; 2084 function = "qup0_se3"; 2085 drive-strength = <2>; 2086 bias-pull-up = <2200>; 2087 }; 2088 2089 qup_uart5_default: qup-uart5-default-state { 2090 /* TX, RX */ 2091 pins = "gpio25", "gpio26"; 2092 function = "qup0_se5"; 2093 drive-strength = <2>; 2094 bias-disable; 2095 }; 2096 2097 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 2098 /* SDA, SCL */ 2099 pins = "gpio32", "gpio33"; 2100 function = "qup1_se0"; 2101 drive-strength = <2>; 2102 bias-pull-up; 2103 }; 2104 2105 qup_uart11_cts_rts: qup-uart11-cts-rts-state { 2106 /* CTS, RTS */ 2107 pins = "gpio48", "gpio49"; 2108 function = "qup1_se4"; 2109 drive-strength = <2>; 2110 bias-pull-down; 2111 }; 2112 2113 qup_uart11_default: qup-uart11-default-state { 2114 /* TX, RX */ 2115 pins = "gpio50", "gpio51"; 2116 function = "qup1_se4"; 2117 drive-strength = <2>; 2118 bias-pull-up; 2119 }; 2120 2121 sdc2_default: sdc2-default-state { 2122 clk-pins { 2123 pins = "gpio62"; 2124 function = "sdc2_clk"; 2125 drive-strength = <16>; 2126 bias-disable; 2127 }; 2128 2129 cmd-pins { 2130 pins = "gpio61"; 2131 function = "sdc2_cmd"; 2132 drive-strength = <10>; 2133 bias-pull-up; 2134 }; 2135 2136 data-pins { 2137 pins = "gpio58", "gpio57", "gpio35", "gpio34"; 2138 function = "sdc2_data"; 2139 drive-strength = <10>; 2140 bias-pull-up; 2141 }; 2142 }; 2143 2144 sdc2_sleep: sdc2-sleep-state { 2145 clk-pins { 2146 pins = "gpio62"; 2147 function = "gpio"; 2148 drive-strength = <2>; 2149 bias-disable; 2150 }; 2151 2152 cmd-pins { 2153 pins = "gpio61"; 2154 function = "gpio"; 2155 drive-strength = <2>; 2156 bias-pull-up; 2157 }; 2158 2159 data-pins { 2160 pins = "gpio58", "gpio57", "gpio35", "gpio34"; 2161 function = "gpio"; 2162 drive-strength = <2>; 2163 bias-pull-up; 2164 }; 2165 }; 2166 2167 cci0_0_default: cci0-0-default-state { 2168 sda-pins { 2169 pins = "gpio88"; 2170 function = "cci_i2c_sda"; 2171 drive-strength = <2>; 2172 bias-pull-up = <2200>; 2173 }; 2174 2175 scl-pins { 2176 pins = "gpio89"; 2177 function = "cci_i2c_scl"; 2178 drive-strength = <2>; 2179 bias-pull-up = <2200>; 2180 }; 2181 }; 2182 2183 cci0_0_sleep: cci0-0-sleep-state { 2184 sda-pins { 2185 pins = "gpio88"; 2186 function = "cci_i2c_sda"; 2187 drive-strength = <2>; 2188 bias-pull-down; 2189 }; 2190 2191 scl-pins { 2192 pins = "gpio89"; 2193 function = "cci_i2c_scl"; 2194 drive-strength = <2>; 2195 bias-pull-down; 2196 }; 2197 }; 2198 2199 cci0_1_default: cci0-1-default-state { 2200 sda-pins { 2201 pins = "gpio90"; 2202 function = "cci_i2c_sda"; 2203 drive-strength = <2>; 2204 bias-pull-up = <2200>; 2205 }; 2206 2207 scl-pins { 2208 pins = "gpio91"; 2209 function = "cci_i2c_scl"; 2210 drive-strength = <2>; 2211 bias-pull-up = <2200>; 2212 }; 2213 }; 2214 2215 cci0_1_sleep: cci0-1-sleep-state { 2216 sda-pins { 2217 pins = "gpio90"; 2218 function = "cci_i2c_sda"; 2219 drive-strength = <2>; 2220 bias-pull-down; 2221 }; 2222 2223 scl-pins { 2224 pins = "gpio91"; 2225 function = "cci_i2c_scl"; 2226 drive-strength = <2>; 2227 bias-pull-down; 2228 }; 2229 }; 2230 2231 cci1_0_default: cci1-0-default-state { 2232 sda-pins { 2233 pins = "gpio92"; 2234 function = "cci_i2c_sda"; 2235 drive-strength = <2>; 2236 bias-pull-up = <2200>; 2237 }; 2238 2239 scl-pins { 2240 pins = "gpio93"; 2241 function = "cci_i2c_scl"; 2242 drive-strength = <2>; 2243 bias-pull-up = <2200>; 2244 }; 2245 }; 2246 2247 cci1_0_sleep: cci1-0-sleep-state { 2248 sda-pins { 2249 pins = "gpio92"; 2250 function = "cci_i2c_sda"; 2251 drive-strength = <2>; 2252 bias-pull-down; 2253 }; 2254 2255 scl-pins { 2256 pins = "gpio93"; 2257 function = "cci_i2c_scl"; 2258 drive-strength = <2>; 2259 bias-pull-down; 2260 }; 2261 }; 2262 2263 cci1_1_default: cci1-1-default-state { 2264 sda-pins { 2265 pins = "gpio94"; 2266 function = "cci_i2c_sda"; 2267 drive-strength = <2>; 2268 bias-pull-up = <2200>; 2269 }; 2270 2271 scl-pins { 2272 pins = "gpio95"; 2273 function = "cci_i2c_scl"; 2274 drive-strength = <2>; 2275 bias-pull-up = <2200>; 2276 }; 2277 }; 2278 2279 cci1_1_sleep: cci1-1-sleep-state { 2280 sda-pins { 2281 pins = "gpio94"; 2282 function = "cci_i2c_sda"; 2283 drive-strength = <2>; 2284 bias-pull-down; 2285 }; 2286 2287 scl-pins { 2288 pins = "gpio95"; 2289 function = "cci_i2c_scl"; 2290 drive-strength = <2>; 2291 bias-pull-down; 2292 }; 2293 }; 2294 }; 2295 2296 apps_smmu: iommu@15000000 { 2297 compatible = "qcom,milos-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2298 reg = <0x0 0x15000000 0x0 0x100000>; 2299 #iommu-cells = <2>; 2300 #global-interrupts = <1>; 2301 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, 2302 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, 2303 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, 2304 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, 2305 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, 2306 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 2307 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, 2308 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 2309 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 2310 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, 2311 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, 2312 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 2313 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 2314 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 2315 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, 2316 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, 2317 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, 2318 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, 2319 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 2320 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, 2321 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, 2322 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, 2323 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, 2324 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, 2325 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, 2326 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, 2327 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, 2328 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, 2329 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, 2330 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, 2331 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, 2332 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, 2333 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, 2334 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, 2335 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, 2336 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, 2337 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, 2338 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, 2339 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, 2340 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, 2341 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, 2342 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, 2343 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, 2344 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, 2345 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, 2346 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, 2347 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, 2348 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, 2349 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, 2350 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, 2351 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, 2352 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, 2353 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, 2354 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, 2355 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, 2356 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, 2357 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, 2358 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, 2359 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, 2360 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, 2361 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, 2362 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>, 2363 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>, 2364 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>, 2365 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>, 2366 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>, 2367 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>, 2368 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 2369 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 2370 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>, 2371 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>, 2372 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>, 2373 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>, 2374 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>, 2375 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>, 2376 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>, 2377 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>, 2378 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>, 2379 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, 2380 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, 2381 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, 2382 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, 2383 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, 2384 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>, 2385 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>, 2386 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>, 2387 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>, 2388 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>, 2389 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>, 2390 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>, 2391 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>, 2392 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>, 2393 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>, 2394 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>, 2395 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>, 2396 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>, 2397 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>; 2398 dma-coherent; 2399 }; 2400 2401 intc: interrupt-controller@17100000 { 2402 compatible = "arm,gic-v3"; 2403 reg = <0x0 0x17100000 0x0 0x10000>, 2404 <0x0 0x17180000 0x0 0x200000>; 2405 2406 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 2407 2408 #interrupt-cells = <4>; 2409 interrupt-controller; 2410 2411 #redistributor-regions = <1>; 2412 redistributor-stride = <0 0x40000>; 2413 2414 #address-cells = <2>; 2415 #size-cells = <2>; 2416 ranges; 2417 2418 ppi-partitions { 2419 ppi_cluster0: interrupt-partition-0 { 2420 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 2421 }; 2422 2423 ppi_cluster1: interrupt-partition-1 { 2424 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 2425 }; 2426 }; 2427 2428 gic_its: msi-controller@17140000 { 2429 compatible = "arm,gic-v3-its"; 2430 reg = <0x0 0x17140000 0x0 0x40000>; 2431 2432 msi-controller; 2433 #msi-cells = <1>; 2434 }; 2435 }; 2436 2437 timer@17420000 { 2438 compatible = "arm,armv7-timer-mem"; 2439 reg = <0x0 0x17420000 0x0 0x1000>; 2440 2441 ranges = <0 0 0 0x20000000>; 2442 #address-cells = <1>; 2443 #size-cells = <1>; 2444 2445 frame@17421000 { 2446 reg = <0x17421000 0x1000>, 2447 <0x17422000 0x1000>; 2448 2449 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, 2450 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 2451 2452 frame-number = <0>; 2453 }; 2454 2455 frame@17423000 { 2456 reg = <0x17423000 0x1000>; 2457 2458 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 2459 2460 frame-number = <1>; 2461 2462 status = "disabled"; 2463 }; 2464 2465 frame@17425000 { 2466 reg = <0x17425000 0x1000>; 2467 2468 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 2469 2470 frame-number = <2>; 2471 2472 status = "disabled"; 2473 }; 2474 2475 frame@17427000 { 2476 reg = <0x17427000 0x1000>; 2477 2478 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 2479 2480 frame-number = <3>; 2481 2482 status = "disabled"; 2483 }; 2484 2485 frame@17429000 { 2486 reg = <0x17429000 0x1000>; 2487 2488 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 2489 2490 frame-number = <4>; 2491 2492 status = "disabled"; 2493 }; 2494 2495 frame@1742b000 { 2496 reg = <0x1742b000 0x1000>; 2497 2498 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; 2499 2500 frame-number = <5>; 2501 2502 status = "disabled"; 2503 }; 2504 2505 frame@1742d000 { 2506 reg = <0x1742d000 0x1000>; 2507 2508 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 2509 2510 frame-number = <6>; 2511 2512 status = "disabled"; 2513 }; 2514 }; 2515 2516 apps_rsc: rsc@17a00000 { 2517 compatible = "qcom,rpmh-rsc"; 2518 reg = <0x0 0x17a00000 0x0 0x10000>, 2519 <0x0 0x17a10000 0x0 0x10000>, 2520 <0x0 0x17a20000 0x0 0x10000>; 2521 reg-names = "drv-0", 2522 "drv-1", 2523 "drv-2"; 2524 2525 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, 2526 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, 2527 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; 2528 2529 power-domains = <&cluster_pd>; 2530 2531 qcom,tcs-offset = <0xd00>; 2532 qcom,drv-id = <2>; 2533 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 2534 <WAKE_TCS 2>, <CONTROL_TCS 0>; 2535 2536 label = "apps_rsc"; 2537 2538 apps_bcm_voter: bcm-voter { 2539 compatible = "qcom,bcm-voter"; 2540 }; 2541 2542 rpmhcc: clock-controller { 2543 compatible = "qcom,milos-rpmh-clk"; 2544 2545 clocks = <&xo_board>; 2546 clock-names = "xo"; 2547 2548 #clock-cells = <1>; 2549 }; 2550 2551 rpmhpd: power-controller { 2552 compatible = "qcom,milos-rpmhpd"; 2553 #power-domain-cells = <1>; 2554 operating-points-v2 = <&rpmhpd_opp_table>; 2555 2556 rpmhpd_opp_table: opp-table { 2557 compatible = "operating-points-v2"; 2558 2559 rpmhpd_opp_ret: opp-16 { 2560 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2561 }; 2562 2563 rpmhpd_opp_low_svs_d1: opp-56 { 2564 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2565 }; 2566 2567 rpmhpd_opp_low_svs: opp-64 { 2568 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2569 }; 2570 2571 rpmhpd_opp_svs: opp-128 { 2572 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2573 }; 2574 2575 rpmhpd_opp_svs_l1: opp-192 { 2576 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2577 }; 2578 2579 rpmhpd_opp_nom: opp-256 { 2580 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2581 }; 2582 2583 rpmhpd_opp_nom_l1: opp-320 { 2584 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2585 }; 2586 2587 rpmhpd_opp_turbo: opp-384 { 2588 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2589 }; 2590 2591 rpmhpd_opp_turbo_l1: opp-416 { 2592 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2593 }; 2594 }; 2595 }; 2596 }; 2597 2598 cpufreq_hw: cpufreq@17d91000 { 2599 compatible = "qcom,milos-cpufreq-epss", "qcom,cpufreq-epss"; 2600 reg = <0x0 0x17d91000 0x0 0x1000>, 2601 <0x0 0x17d92000 0x0 0x1000>, 2602 <0x0 0x17d93000 0x0 0x1000>; 2603 reg-names = "freq-domain0", 2604 "freq-domain1", 2605 "freq-domain2"; 2606 2607 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, 2608 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>, 2609 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 2610 interrupt-names = "dcvsh-irq-0", 2611 "dcvsh-irq-1", 2612 "dcvsh-irq-2"; 2613 2614 clocks = <&rpmhcc RPMH_CXO_CLK>, 2615 <&gcc GCC_GPLL0>; 2616 clock-names = "xo", 2617 "alternate"; 2618 2619 #freq-domain-cells = <1>; 2620 #clock-cells = <1>; 2621 }; 2622 2623 gem_noc: interconnect@24100000 { 2624 compatible = "qcom,milos-gem-noc"; 2625 reg = <0x0 0x24100000 0x0 0xff080>; 2626 #interconnect-cells = <2>; 2627 qcom,bcm-voters = <&apps_bcm_voter>; 2628 }; 2629 2630 nsp_noc: interconnect@320c0000 { 2631 compatible = "qcom,milos-nsp-noc"; 2632 reg = <0x0 0x320c0000 0x0 0xe080>; 2633 #interconnect-cells = <2>; 2634 qcom,bcm-voters = <&apps_bcm_voter>; 2635 }; 2636 2637 remoteproc_cdsp: remoteproc@32300000 { 2638 compatible = "qcom,milos-cdsp-pas"; 2639 reg = <0x0 0x32300000 0x0 0x10000>; 2640 2641 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, 2642 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2643 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2644 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2645 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, 2646 <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; 2647 interrupt-names = "wdog", 2648 "fatal", 2649 "ready", 2650 "handover", 2651 "stop-ack", 2652 "shutdown-ack"; 2653 2654 clocks = <&rpmhcc RPMH_CXO_CLK>; 2655 clock-names = "xo"; 2656 2657 power-domains = <&rpmhpd RPMHPD_CX>, 2658 <&rpmhpd RPMHPD_MX>; 2659 power-domain-names = "cx", 2660 "mx"; 2661 2662 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 2663 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2664 2665 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 2666 2667 qcom,qmp = <&aoss_qmp>; 2668 2669 qcom,smem-states = <&smp2p_cdsp_out 0>; 2670 qcom,smem-state-names = "stop"; 2671 2672 status = "disabled"; 2673 2674 glink-edge { 2675 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2676 IPCC_MPROC_SIGNAL_GLINK_QMP 2677 IRQ_TYPE_EDGE_RISING>; 2678 mboxes = <&ipcc IPCC_CLIENT_CDSP 2679 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2680 2681 label = "cdsp"; 2682 qcom,remote-pid = <5>; 2683 2684 fastrpc { 2685 compatible = "qcom,fastrpc"; 2686 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2687 label = "cdsp"; 2688 qcom,non-secure-domain; 2689 #address-cells = <1>; 2690 #size-cells = <0>; 2691 2692 compute-cb@1 { 2693 compatible = "qcom,fastrpc-compute-cb"; 2694 reg = <1>; 2695 iommus = <&apps_smmu 0x0c01 0x0>; 2696 dma-coherent; 2697 }; 2698 2699 compute-cb@2 { 2700 compatible = "qcom,fastrpc-compute-cb"; 2701 reg = <2>; 2702 iommus = <&apps_smmu 0x0c02 0x0>; 2703 dma-coherent; 2704 }; 2705 2706 compute-cb@3 { 2707 compatible = "qcom,fastrpc-compute-cb"; 2708 reg = <3>; 2709 iommus = <&apps_smmu 0x0c03 0x0>; 2710 dma-coherent; 2711 }; 2712 2713 compute-cb@4 { 2714 compatible = "qcom,fastrpc-compute-cb"; 2715 reg = <4>; 2716 iommus = <&apps_smmu 0x0c04 0x0>; 2717 dma-coherent; 2718 }; 2719 2720 compute-cb@5 { 2721 compatible = "qcom,fastrpc-compute-cb"; 2722 reg = <5>; 2723 iommus = <&apps_smmu 0x0c05 0x0>; 2724 dma-coherent; 2725 }; 2726 2727 compute-cb@6 { 2728 compatible = "qcom,fastrpc-compute-cb"; 2729 reg = <6>; 2730 iommus = <&apps_smmu 0x0c06 0x0>; 2731 dma-coherent; 2732 }; 2733 2734 compute-cb@7 { 2735 compatible = "qcom,fastrpc-compute-cb"; 2736 reg = <7>; 2737 iommus = <&apps_smmu 0x0c07 0x0>; 2738 dma-coherent; 2739 }; 2740 2741 compute-cb@8 { 2742 compatible = "qcom,fastrpc-compute-cb"; 2743 reg = <8>; 2744 iommus = <&apps_smmu 0x0c08 0x0>; 2745 dma-coherent; 2746 }; 2747 2748 /* note: secure cb9 in downstream */ 2749 2750 compute-cb@12 { 2751 compatible = "qcom,fastrpc-compute-cb"; 2752 reg = <12>; 2753 iommus = <&apps_smmu 0x0c0c 0x0>; 2754 dma-coherent; 2755 }; 2756 2757 compute-cb@13 { 2758 compatible = "qcom,fastrpc-compute-cb"; 2759 reg = <13>; 2760 iommus = <&apps_smmu 0x0c0d 0x0>; 2761 dma-coherent; 2762 }; 2763 2764 compute-cb@14 { 2765 compatible = "qcom,fastrpc-compute-cb"; 2766 reg = <14>; 2767 iommus = <&apps_smmu 0x0c0e 0x0>; 2768 dma-coherent; 2769 }; 2770 2771 compute-cb@15 { 2772 compatible = "qcom,fastrpc-compute-cb"; 2773 reg = <15>; 2774 iommus = <&apps_smmu 0x0c0f 0x0>; 2775 dma-coherent; 2776 }; 2777 }; 2778 }; 2779 }; 2780 }; 2781 2782 thermal-zones { 2783 aoss0-thermal { 2784 thermal-sensors = <&tsens0 0>; 2785 2786 trips { 2787 aoss0-hot { 2788 temperature = <110000>; 2789 hysteresis = <1000>; 2790 type = "hot"; 2791 }; 2792 2793 aoss0-critical { 2794 temperature = <115000>; 2795 hysteresis = <0>; 2796 type = "critical"; 2797 }; 2798 }; 2799 }; 2800 2801 cpuss0-thermal { 2802 thermal-sensors = <&tsens0 1>; 2803 2804 trips { 2805 cpuss0-critical { 2806 temperature = <115000>; 2807 hysteresis = <0>; 2808 type = "critical"; 2809 }; 2810 }; 2811 }; 2812 2813 cpuss1-thermal { 2814 thermal-sensors = <&tsens0 2>; 2815 2816 trips { 2817 cpuss1-critical { 2818 temperature = <115000>; 2819 hysteresis = <0>; 2820 type = "critical"; 2821 }; 2822 }; 2823 }; 2824 2825 cpu4-left-thermal { 2826 thermal-sensors = <&tsens0 3>; 2827 2828 trips { 2829 cpu4-left-critical { 2830 temperature = <110000>; 2831 hysteresis = <1000>; 2832 type = "critical"; 2833 }; 2834 }; 2835 }; 2836 2837 cpu4-right-thermal { 2838 thermal-sensors = <&tsens0 4>; 2839 2840 trips { 2841 cpu4-right-critical { 2842 temperature = <110000>; 2843 hysteresis = <1000>; 2844 type = "critical"; 2845 }; 2846 }; 2847 }; 2848 2849 cpu5-left-thermal { 2850 thermal-sensors = <&tsens0 5>; 2851 2852 trips { 2853 cpu5-left-critical { 2854 temperature = <110000>; 2855 hysteresis = <1000>; 2856 type = "critical"; 2857 }; 2858 }; 2859 }; 2860 2861 cpu5-right-thermal { 2862 thermal-sensors = <&tsens0 6>; 2863 2864 trips { 2865 cpu5-right-critical { 2866 temperature = <110000>; 2867 hysteresis = <1000>; 2868 type = "critical"; 2869 }; 2870 }; 2871 }; 2872 2873 cpu6-left-thermal { 2874 thermal-sensors = <&tsens0 7>; 2875 2876 trips { 2877 cpu6-left-critical { 2878 temperature = <110000>; 2879 hysteresis = <1000>; 2880 type = "critical"; 2881 }; 2882 }; 2883 }; 2884 2885 cpu6-right-thermal { 2886 thermal-sensors = <&tsens0 8>; 2887 2888 trips { 2889 cpu6-right-critical { 2890 temperature = <110000>; 2891 hysteresis = <1000>; 2892 type = "critical"; 2893 }; 2894 }; 2895 }; 2896 2897 cpu7-left-thermal { 2898 thermal-sensors = <&tsens0 9>; 2899 2900 trips { 2901 cpu7-left-critical { 2902 temperature = <110000>; 2903 hysteresis = <1000>; 2904 type = "critical"; 2905 }; 2906 }; 2907 }; 2908 2909 cpu7-right-thermal { 2910 thermal-sensors = <&tsens0 10>; 2911 2912 trips { 2913 cpu7-right-critical { 2914 temperature = <110000>; 2915 hysteresis = <1000>; 2916 type = "critical"; 2917 }; 2918 }; 2919 }; 2920 2921 cpu0-thermal { 2922 thermal-sensors = <&tsens0 11>; 2923 2924 trips { 2925 cpu0-critical { 2926 temperature = <110000>; 2927 hysteresis = <1000>; 2928 type = "critical"; 2929 }; 2930 }; 2931 }; 2932 2933 cpu1-thermal { 2934 thermal-sensors = <&tsens0 12>; 2935 2936 trips { 2937 cpu1-critical { 2938 temperature = <110000>; 2939 hysteresis = <1000>; 2940 type = "critical"; 2941 }; 2942 }; 2943 }; 2944 2945 cpu2-thermal { 2946 thermal-sensors = <&tsens0 13>; 2947 2948 trips { 2949 cpu2-critical { 2950 temperature = <110000>; 2951 hysteresis = <1000>; 2952 type = "critical"; 2953 }; 2954 }; 2955 }; 2956 2957 cpu3-thermal { 2958 thermal-sensors = <&tsens0 14>; 2959 2960 trips { 2961 cpu3-critical { 2962 temperature = <110000>; 2963 hysteresis = <1000>; 2964 type = "critical"; 2965 }; 2966 }; 2967 }; 2968 2969 aoss1-thermal { 2970 thermal-sensors = <&tsens1 0>; 2971 2972 trips { 2973 aoss1-hot { 2974 temperature = <110000>; 2975 hysteresis = <1000>; 2976 type = "hot"; 2977 }; 2978 2979 aoss1-critical { 2980 temperature = <115000>; 2981 hysteresis = <0>; 2982 type = "critical"; 2983 }; 2984 }; 2985 }; 2986 2987 nsphvx0-thermal { 2988 polling-delay-passive = <10>; 2989 2990 thermal-sensors = <&tsens1 1>; 2991 2992 trips { 2993 nsphvx0-hot { 2994 temperature = <110000>; 2995 hysteresis = <1000>; 2996 type = "hot"; 2997 }; 2998 2999 nsphvx0-critical { 3000 temperature = <115000>; 3001 hysteresis = <0>; 3002 type = "critical"; 3003 }; 3004 }; 3005 }; 3006 3007 nsphmx1-thermal { 3008 polling-delay-passive = <10>; 3009 3010 thermal-sensors = <&tsens1 2>; 3011 3012 trips { 3013 nsphmx1-hot { 3014 temperature = <110000>; 3015 hysteresis = <1000>; 3016 type = "hot"; 3017 }; 3018 3019 nsphmx1-critical { 3020 temperature = <115000>; 3021 hysteresis = <0>; 3022 type = "critical"; 3023 }; 3024 }; 3025 }; 3026 3027 nsphmx0-thermal { 3028 polling-delay-passive = <10>; 3029 3030 thermal-sensors = <&tsens1 3>; 3031 3032 trips { 3033 nsphmx0-hot { 3034 temperature = <110000>; 3035 hysteresis = <1000>; 3036 type = "hot"; 3037 }; 3038 3039 nsphmx0-critical { 3040 temperature = <115000>; 3041 hysteresis = <0>; 3042 type = "critical"; 3043 }; 3044 }; 3045 }; 3046 3047 gpuss0-thermal { 3048 polling-delay-passive = <10>; 3049 3050 thermal-sensors = <&tsens1 4>; 3051 3052 trips { 3053 gpu0_alert0: trip-point0 { 3054 temperature = <85000>; 3055 hysteresis = <1000>; 3056 type = "passive"; 3057 }; 3058 3059 trip-point1 { 3060 temperature = <90000>; 3061 hysteresis = <1000>; 3062 type = "hot"; 3063 }; 3064 3065 gpuss0-critical { 3066 temperature = <110000>; 3067 hysteresis = <1000>; 3068 type = "critical"; 3069 }; 3070 }; 3071 }; 3072 3073 gpuss1-thermal { 3074 polling-delay-passive = <10>; 3075 3076 thermal-sensors = <&tsens1 5>; 3077 3078 trips { 3079 gpu1_alert0: trip-point0 { 3080 temperature = <85000>; 3081 hysteresis = <1000>; 3082 type = "passive"; 3083 }; 3084 3085 trip-point1 { 3086 temperature = <90000>; 3087 hysteresis = <1000>; 3088 type = "hot"; 3089 }; 3090 3091 gpuss1-critical { 3092 temperature = <110000>; 3093 hysteresis = <1000>; 3094 type = "critical"; 3095 }; 3096 }; 3097 }; 3098 3099 video-thermal { 3100 thermal-sensors = <&tsens1 7>; 3101 3102 trips { 3103 video-hot { 3104 temperature = <110000>; 3105 hysteresis = <1000>; 3106 type = "hot"; 3107 }; 3108 3109 video-critical { 3110 temperature = <115000>; 3111 hysteresis = <0>; 3112 type = "critical"; 3113 }; 3114 }; 3115 }; 3116 3117 ddr-thermal { 3118 polling-delay-passive = <10>; 3119 3120 thermal-sensors = <&tsens1 8>; 3121 3122 trips { 3123 ddr-hot { 3124 temperature = <110000>; 3125 hysteresis = <1000>; 3126 type = "hot"; 3127 }; 3128 3129 ddr-critical { 3130 temperature = <115000>; 3131 hysteresis = <0>; 3132 type = "critical"; 3133 }; 3134 }; 3135 }; 3136 3137 camera0-thermal { 3138 thermal-sensors = <&tsens1 9>; 3139 3140 trips { 3141 camera0-hot { 3142 temperature = <110000>; 3143 hysteresis = <1000>; 3144 type = "hot"; 3145 }; 3146 3147 camera0-critical { 3148 temperature = <115000>; 3149 hysteresis = <0>; 3150 type = "critical"; 3151 }; 3152 }; 3153 }; 3154 3155 modem0-thermal { 3156 polling-delay-passive = <100>; 3157 3158 thermal-sensors = <&tsens1 10>; 3159 3160 trips { 3161 modem0-hot { 3162 temperature = <110000>; 3163 hysteresis = <1000>; 3164 type = "hot"; 3165 }; 3166 3167 modem0-critical { 3168 temperature = <115000>; 3169 hysteresis = <0>; 3170 type = "critical"; 3171 }; 3172 }; 3173 }; 3174 3175 modem1-thermal { 3176 polling-delay-passive = <100>; 3177 3178 thermal-sensors = <&tsens1 11>; 3179 3180 trips { 3181 modem1-hot { 3182 temperature = <110000>; 3183 hysteresis = <1000>; 3184 type = "hot"; 3185 }; 3186 3187 modem1-critical { 3188 temperature = <115000>; 3189 hysteresis = <0>; 3190 type = "critical"; 3191 }; 3192 }; 3193 }; 3194 3195 modem2-thermal { 3196 polling-delay-passive = <100>; 3197 3198 thermal-sensors = <&tsens1 12>; 3199 3200 trips { 3201 modem2-hot { 3202 temperature = <110000>; 3203 hysteresis = <1000>; 3204 type = "hot"; 3205 }; 3206 3207 modem2-critical { 3208 temperature = <115000>; 3209 hysteresis = <0>; 3210 type = "critical"; 3211 }; 3212 }; 3213 }; 3214 3215 modem3-thermal { 3216 polling-delay-passive = <100>; 3217 3218 thermal-sensors = <&tsens1 13>; 3219 3220 trips { 3221 modem3-hot { 3222 temperature = <110000>; 3223 hysteresis = <1000>; 3224 type = "hot"; 3225 }; 3226 3227 modem3-critical { 3228 temperature = <115000>; 3229 hysteresis = <0>; 3230 type = "critical"; 3231 }; 3232 }; 3233 }; 3234 }; 3235 3236 timer { 3237 compatible = "arm,armv8-timer"; 3238 3239 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 3240 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 3241 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 3242 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>; 3243 }; 3244}; 3245