Searched full:drams (Results 1 – 5 of 5) sorted by relevance
392 struct iwl_dram_data *cur_payload_dram = &dram_regions->drams[0]; in iwl_pcie_load_payloads_segments()435 cpu_to_le64(dram_regions->drams[i].physical); in iwl_pcie_load_payloads_segments()477 &dram_regions->drams[0]); in iwl_trans_pcie_ctx_info_v2_load_pnvm()494 total_size += dram_regions->drams[i].size; in iwl_dram_regions_size()519 cpu_to_le64(trans_pcie->pnvm_data.drams[0].physical); in iwl_pcie_set_contig_pnvm()521 cpu_to_le32(trans_pcie->pnvm_data.drams[0].size); in iwl_pcie_set_contig_pnvm()571 &dram_regions->drams[0]); in iwl_trans_pcie_ctx_info_v2_load_reduce_power()601 cpu_to_le64(trans_pcie->reduced_tables_data.drams[0].physical); in iwl_pcie_set_contig_reduce_power()603 cpu_to_le32(trans_pcie->reduced_tables_data.drams[0].size); in iwl_pcie_set_contig_reduce_power()
38 node0 is for DDR5 DRAMs connected via DIMM, while node1 is for DDR439 DRAMs connected via CXL.
51 * Places DRAMs in self-refresh mode59 * DRAMS are placed back into normal mode
1928 dma_free_coherent(dev, dram_regions->drams[i].size, in iwl_trans_pcie_free_pnvm_dram_regions()1929 dram_regions->drams[i].block, in iwl_trans_pcie_free_pnvm_dram_regions()1930 dram_regions->drams[i].physical); in iwl_trans_pcie_free_pnvm_dram_regions()
609 * the effective memory clock of the DRAMs. To translate it, use the