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/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddml1_display_rq_dlg_calc.c33 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
37 * remain as-is as it provides us with a guarantee from HW that it is correct.
97 static double get_refcyc_per_delivery( in get_refcyc_per_delivery()
99 double refclk_freq_in_mhz, in get_refcyc_per_delivery()
100 double pclk_freq_in_mhz, in get_refcyc_per_delivery()
102 double vratio, in get_refcyc_per_delivery()
103 double hscale_pixel_rate, in get_refcyc_per_delivery()
107 double refcyc_per_delivery = 0.0; in get_refcyc_per_delivery()
110 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width in get_refcyc_per_delivery()
111 / pclk_freq_in_mhz / (double) req_per_swath_ub; in get_refcyc_per_delivery()
[all …]
H A Ddisplay_mode_vba.c33 * This file is gcc-parsable HW gospel, coming straight from HW engineers.
37 * remain as-is as it provides us with a guarantee from HW that it is correct.
57 bool need_recalculate = memcmp(&mode_lib->soc, &mode_lib->vba.soc, sizeof(mode_lib->vba.soc)) != 0 in dml_get_voltage_level()
58 || memcmp(&mode_lib->ip, &mode_lib->vba.ip, sizeof(mode_lib->vba.ip)) != 0 in dml_get_voltage_level()
59 || num_pipes != mode_lib->vba.cache_num_pipes in dml_get_voltage_level()
60 || memcmp(pipes, mode_lib->vba.cache_pipes, in dml_get_voltage_level()
63 mode_lib->vba.soc = mode_lib->soc; in dml_get_voltage_level()
64 mode_lib->vba.ip = mode_lib->ip; in dml_get_voltage_level()
65 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
66 mode_lib->vba.cache_num_pipes = num_pipes; in dml_get_voltage_level()
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H A Ddisplay_mode_structs.h68 double UrgentWatermark;
69 double WritebackUrgentWatermark;
70 double DRAMClockChangeWatermark;
71 double FCLKChangeWatermark;
72 double WritebackDRAMClockChangeWatermark;
73 double WritebackFCLKChangeWatermark;
74 double StutterExitWatermark;
75 double StutterEnterPlusExitWatermark;
76 double Z8StutterExitWatermark;
77 double Z8StutterEnterPlusExitWatermark;
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H A Ddisplay_mode_vba.h34 #define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_…
75 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const dis…
148 double get_total_immediate_flip_bytes(
152 double get_total_immediate_flip_bw(
156 double get_total_prefetch_bw(
188 double dummy_single_array[2][DC__NUM_DPP__MAX];
190 double dummy_double_array[2][DC__NUM_DPP__MAX];
199 double HostVMInefficiencyFactor;
202 double dummy_unit_vector[DC__NUM_DPP__MAX];
203 double dummy_single[2];
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
H A Ddml2_core_dcn4_calcs.c1 // SPDX-License-Identifier: MIT
49 static double dml2_core_div_rem(double dividend, unsigned int divisor, unsigned int *remainder) in dml2_core_div_rem()
51 *remainder = ((dividend / divisor) - (int)(dividend / divisor) > 0); in dml2_core_div_rem()
59 if (!fail_only || support->ScaleRatioAndTapsSupport == 0) in dml2_print_mode_support_info()
60 …DML_LOG_VERBOSE("DML: support: ScaleRatioAndTapsSupport = %d\n", support->ScaleRatioAndTapsSupport… in dml2_print_mode_support_info()
61 if (!fail_only || support->SourceFormatPixelAndScanSupport == 0) in dml2_print_mode_support_info()
62 …DML_LOG_VERBOSE("DML: support: SourceFormatPixelAndScanSupport = %d\n", support->SourceFormatPixel… in dml2_print_mode_support_info()
63 if (!fail_only || support->ViewportSizeSupport == 0) in dml2_print_mode_support_info()
64 DML_LOG_VERBOSE("DML: support: ViewportSizeSupport = %d\n", support->ViewportSizeSupport); in dml2_print_mode_support_info()
65 if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1) in dml2_print_mode_support_info()
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/linux/Documentation/devicetree/bindings/power/supply/
H A Dmaxim,max17040.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
13 - $ref: power-supply.yaml#
18 - maxim,max17040
19 - maxim,max17041
20 - maxim,max17043
21 - maxim,max17044
22 - maxim,max17048
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.c42 static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib, in get_refcyc_per_delivery()
43 double refclk_freq_in_mhz, in get_refcyc_per_delivery()
44 double pclk_freq_in_mhz, in get_refcyc_per_delivery()
48 double vratio, in get_refcyc_per_delivery()
49 double hscale_pixel_rate, in get_refcyc_per_delivery()
53 double refcyc_per_delivery = 0.0; in get_refcyc_per_delivery()
57 refcyc_per_delivery = (double)refclk_freq_in_mhz * (double)((unsigned int)odm_combine*2) in get_refcyc_per_delivery()
58 * dml_min((double)recout_width, (double)hactive / ((unsigned int)odm_combine*2)) in get_refcyc_per_delivery()
59 / pclk_freq_in_mhz / (double)req_per_swath_ub; in get_refcyc_per_delivery()
61 refcyc_per_delivery = (double)refclk_freq_in_mhz * (double)recout_width in get_refcyc_per_delivery()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c34 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
38 * remain as-is as it provides us with a guarantee from HW that it is correct.
43 double *refcyc_per_req_delivery_pre_cur,
44 double *refcyc_per_req_delivery_cur,
45 double refclk_freq_in_mhz,
46 double ref_freq_to_pix_freq,
47 double hscale_pixel_rate_l,
48 double hscl_ratio,
49 double vratio_pre_l,
50 double vratio_l,
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20.c34 // pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
36 // rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
58 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
62 * remain as-is as it provides us with a guarantee from HW that it is correct.
66 double *refcyc_per_req_delivery_pre_cur,
67 double *refcyc_per_req_delivery_cur,
68 double refclk_freq_in_mhz,
69 double ref_freq_to_pix_freq,
70 double hscale_pixel_rate_l,
71 double hscl_ratio,
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H A Ddisplay_rq_dlg_calc_20v2.c34 // pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
36 // rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
58 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
62 * remain as-is as it provides us with a guarantee from HW that it is correct.
66 double *refcyc_per_req_delivery_pre_cur,
67 double *refcyc_per_req_delivery_cur,
68 double refclk_freq_in_mhz,
69 double ref_freq_to_pix_freq,
70 double hscale_pixel_rate_l,
71 double hscl_ratio,
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_util_32.c34 double BPP, in dml32_dscceComputeDelay()
87 p = 3 * wx - w; in dml32_dscceComputeDelay()
91 L = (ax + wx - 1) / wx; in dml32_dscceComputeDelay()
96 Delay = L * wx * (numSlices - 1) + ax + s + lstall + 22; in dml32_dscceComputeDelay()
123 // dscc - input deserializer in dml32_dscComputeDelay()
127 // dscc - input cdc fifo in dml32_dscComputeDelay()
131 // dscc - cdc uncertainty in dml32_dscComputeDelay()
133 // dscc - output cdc fifo in dml32_dscComputeDelay()
137 // dscc - cdc uncertainty in dml32_dscComputeDelay()
139 // dscc - output serializer in dml32_dscComputeDelay()
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H A Ddisplay_mode_vba_util_32.h37 double BPP,
54 double *BytePerPixelDETY,
55 double *BytePerPixelDETC,
66 double HRatio,
67 double HRatioChroma,
68 double VRatio,
69 double VRatioChroma,
70 double MaxDCHUBToPSCLThroughput,
71 double MaxPSCLToLBThroughput,
72 double PixelClock,
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/linux/sound/soc/
H A Dsoc-ops-test.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <sound/soc.h>
13 #include <sound/soc-component.h>
108 ITEST("Test Control", DOUBLE, BOOLEAN, volsw, 0, 1, 0, 1, 0, 0, 0),
109 ITEST("Test Volume", DOUBLE, INTEGER, volsw, 0, 1, 0, 1, 0, 0, 0),
110 ITEST("Test Volume Control", DOUBLE, BOOLEAN, volsw, 0, 1, 0, 1, 0, 0, 0),
114 ITEST("Test Control", DOUBLE, BOOLEAN, volsw, 0, 1, 0, 1, 0, 0, 1),
115 ITEST("Test Volume", DOUBLE, INTEGER, volsw, 0, 1, 0, 1, 0, 0, 1),
116 ITEST("Test Volume Control", DOUBLE, BOOLEAN, volsw, 0, 1, 0, 1, 0, 0, 1),
124 ITEST("Test Control", SINGLE, INTEGER, volsw, 0, 20, -10, 10, 0, 4, 0),
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H A Dsoc-ops.c1 // SPDX-License-Identifier: GPL-2.0+
3 // soc-ops.c -- Generic ASoC operations
11 // with code, comments and ideas from :-
26 #include <sound/soc.h>
30 * snd_soc_info_enum_double - enumerated double mixer info callback
34 * Callback to provide information about a double enumerated
42 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in snd_soc_info_enum_double()
44 return snd_ctl_enum_info(uinfo, e->shift_l == e->shift_r ? 1 : 2, in snd_soc_info_enum_double()
45 e->items, e->texts); in snd_soc_info_enum_double()
50 * snd_soc_get_enum_double - enumerated double mixer get callback
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/linux/Documentation/devicetree/bindings/edac/
H A Daspeed-sdram-edac.txt1 Aspeed BMC SoC EDAC node
3 The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
6 The memory controller supports SECDED (single bit error correction, double bit
14 - compatible: should be one of
15 - "aspeed,ast2400-sdram-edac"
16 - "aspeed,ast2500-sdram-edac"
17 - "aspeed,ast2600-sdram-edac"
18 - reg: sdram controller register set should be <0x1e6e0000 0x174>
19 - interrupts: should be AVIC interrupt #0
25 compatible = "aspeed,ast2500-sdram-edac";
/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra20-ehci.txt1 Tegra SOC USB controllers
4 SOC is as described in the document "Open Firmware Recommended
9 - compatible : For Tegra20, must contain "nvidia,tegra20-ehci".
10 For Tegra30, must contain "nvidia,tegra30-ehci". Otherwise, must contain
11 "nvidia,<chip>-ehci" plus at least one of the above, where <chip> is
13 - nvidia,phy : phandle of the PHY that the controller is connected to.
14 - clocks : Must contain one entry, for the module clock.
15 See ../clocks/clock-bindings.txt for details.
16 - resets : Must contain an entry for each entry in reset-names.
18 - reset-names : Must include the following entries:
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dumc_v6_7.h34 #define UMC_V6_7_CE_CNT_INIT (UMC_V6_7_CE_CNT_MAX - UMC_V6_7_CE_INT_THRESHOLD)
46 /* R14 bit shift should be considered, double the number */
48 /* The CH4 bit in SOC physical address */
50 /* The C2 bit in SOC physical address */
52 /* The R14 bit in SOC physical address */
61 (((pa) >> 20) & 0x1ULL & adev->df.hash_status.hash_64k) ^ \
62 (((pa) >> 25) & 0x1ULL & adev->df.hash_status.hash_2m) ^ \
63 (((pa) >> 34) & 0x1ULL & adev->df.hash_status.hash_1g))
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_translation_helper.c1 /* SPDX-License-Identifier: MIT */
36 switch (dml2->v20.dml_core_ctx.project) { in dml2_init_ip_params()
41 out->vblank_nom_default_us = 600; in dml2_init_ip_params()
42 out->rob_buffer_size_kbytes = 128; in dml2_init_ip_params()
43 out->config_return_buffer_size_in_kbytes = 1280; in dml2_init_ip_params()
44 out->config_return_buffer_segment_size_in_kbytes = 64; in dml2_init_ip_params()
45 out->compressed_buffer_segment_size_in_kbytes = 64; in dml2_init_ip_params()
46 out->meta_fifo_size_in_kentries = 22; in dml2_init_ip_params()
47 out->zero_size_buffer_entries = 512; in dml2_init_ip_params()
48 out->dpte_buffer_size_in_pte_reqs_luma = 68; in dml2_init_ip_params()
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnuvoton,npcm-memory-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nuvoton,npcm-memory-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marvin Lin <kflin@nuvoton.com>
11 - Stanley Chu <yschu@nuvoton.com>
14 The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction
17 The memory controller supports single bit error correction, double bit error
18 detection (in-line ECC in which a section (1/8th) of the memory device used to
26 - nuvoton,npcm750-memory-controller
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/linux/Documentation/devicetree/bindings/spi/
H A Dbrcm,spi-bcm-qspi.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
19 for flash reads and be configured to do single, double, quad lane
20 io with 3-byte and 4-byte addressing support.
28 - $ref: spi-controller.yaml#
33 - description: Second Instance of MSPI BRCMSTB SoCs
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/linux/arch/arm/boot/dts/marvell/
H A Darmada-39x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
18 model = "Marvell Armada 39x family SoC";
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "marvell,armada-390-smp";
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/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A Djkt-metrics.json4 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
54 "MetricGroup": "SoC",
59 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
75 "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/
H A Ddml21_translation_helper.c1 // SPDX-License-Identifier: MIT
17 bool disable_fams2 = !in_dc->debug.fams2_config.bits.enable; in dml21_populate_pmo_options()
20 pmo_options->disable_dyn_odm = !config->minimize_dispclk_using_odm; in dml21_populate_pmo_options()
21 pmo_options->disable_dyn_odm_for_multi_stream = true; in dml21_populate_pmo_options()
22 pmo_options->disable_dyn_odm_for_stream_with_svp = true; in dml21_populate_pmo_options()
24 pmo_options->disable_vblank = ((in_dc->debug.dml21_disable_pstate_method_mask >> 1) & 1); in dml21_populate_pmo_options()
27 pmo_options->disable_svp = ((in_dc->debug.dml21_disable_pstate_method_mask >> 2) & 1) || in dml21_populate_pmo_options()
28 in_dc->debug.force_disable_subvp || in dml21_populate_pmo_options()
30 pmo_options->disable_drr_clamped = ((in_dc->debug.dml21_disable_pstate_method_mask >> 3) & 1) || in dml21_populate_pmo_options()
32 pmo_options->disable_drr_var = ((in_dc->debug.dml21_disable_pstate_method_mask >> 4) & 1) || in dml21_populate_pmo_options()
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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
[all …]
H A Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
[all …]

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