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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
17 - reg : shall be the physical PLL register address for the pll clock.
[all …]
H A Dapm,xgene-device-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: APM X-Gene SoC device clocks
10 - Khuong Dinh <khuong@os.amperecomputing.com>
14 const: apm,xgene-device-clock
20 reg-names:
22 - enum: [ csr-reg, div-reg ]
23 - const: div-reg
[all …]
H A Daltr_socfpga.txt5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
18 - #clock-cells : from common clock binding, shall be set to 0.
21 - fixed-divider : If clocks have a fixed divider value, use this property.
22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
[all …]
H A Drenesas,h8300-div-clock.txt1 * Renesas H8/300 divider clock
5 - compatible: Must be "renesas,h8300-div-clock"
7 - clocks: Reference to the parent clocks ("extal1" and "extal2")
9 - #clock-cells: Must be 1
11 - reg: Base address and length of the divide rate selector
13 - renesas,width: bit width of selector
16 -------
19 compatible = "renesas,h8300-div-clock";
21 #clock-cells = <0>;
23 renesas,width = <2>;
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi_oc_tiny.txt4 - compatible : should be "opencores,tiny-spi-rtlsvn2".
5 - gpios : should specify GPIOs used for chipselect.
7 - clock-frequency : input clock frequency to the core.
8 - baud-width: width, in bits, of the programmable divider used to scale
11 The clock-frequency and baud-width properties are needed only if the divider
12 is programmable. They are not needed if the divider is fixed.
/freebsd/usr.bin/sdiff/
H A Dsdiff.c31 #define WIDTH 126 macro
68 static size_t line_width; /* width of a line (two columns and divider) */
69 static size_t width; /* width of each column */ variable
91 { "suppress-common-lines", no_argument, NULL, 's' },
92 { "width", required_argument, NULL, 'w' },
95 { "diff-program", required_argument, NULL, DIFFPROG_OPT },
98 { "ignore-fil
640 println(const char * s1,const char divider,const char * s2) println() argument
892 enqueue(char * left,char divider,char * right) enqueue() argument
[all...]
/freebsd/sys/dev/clk/allwinner/
H A Daw_clk.h1 /*-
46 Clock Source/Divider N/Divider M
47 Clock Source/Divider N/Divider M/2
48 Clock Source*N/(Divider M+1)/(Divider P+1)
79 uint32_t width; /* Number of bits for the factor */ member
106 if (factor->flags & AW_CLK_FACTOR_HAS_COND) { in aw_clk_get_factor()
107 cond = (val & factor->cond_mask) >> factor->cond_shift; in aw_clk_get_factor()
108 if (cond != factor->cond_value) in aw_clk_get_factor()
112 if (factor->flags & AW_CLK_FACTOR_FIXED) in aw_clk_get_factor()
113 return (factor->value); in aw_clk_get_factor()
[all …]
H A Dccu_a13.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/reset/sun5i-ccu.h>
50 /* Non-exported clocks */
101 CCU_GATE(CLK_DRAM_AXI, "axi-dram", "axi", 0x5c, 0)
103 CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0)
104 CCU_GATE(CLK_AHB_EHCI, "ahb-ehci", "ahb", 0x60, 1)
105 CCU_GATE(CLK_AHB_OHCI, "ahb-ohci", "ahb", 0x60, 2)
106 CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5)
[all …]
H A Dccu_a64.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #include <dt-bindings/clock/sun50i-a64-ccu.h>
48 #include <dt-bindings/reset/sun50i-a64-ccu.h>
50 /* Non-exported clocks */
141 CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1)
142 CCU_GATE(CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5)
143 CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6)
144 CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8)
145 CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9)
[all …]
H A Dccu_h3.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
55 #include <dt-bindings/clock/sun8i-h3-ccu.h>
56 #include <dt-bindings/reset/sun8i-h3-ccu.h>
58 /* Non-exported resets */
61 /* Non-exported clocks */
160 CCU_GATE(CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5)
161 CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6)
162 CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8)
163 CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9)
[all …]
/freebsd/sys/dev/clk/
H A Dclk_div.h1 /*-
32 #define CLK_DIV_ZERO_BASED 0x0001 /* Zero based divider. */
37 uint32_t divider; member
42 uint32_t offset; /* Divider register offset */
44 uint32_t i_width; /* Width of div bit field */
46 uint32_t f_width; /* set to 0 for int divider */
47 int div_flags; /* Divider-specific flags */
48 struct clk_div_table *div_table; /* Divider table */
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dexynos-dw-mshc.txt7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
25 - "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific
28 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
30 ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
[all …]
H A Dmarvell,xenon-sdhci.txt11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-ap807-sdhci": For controllers on Armada AP807.
16 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
18 - clocks:
23 - clock-names:
28 - reg:
29 * For "marvell,armada-3700-sdhci", two register areas.
[all …]
H A Dsamsung,exynos-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Jaehoon Chung <jh80.chung@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - enum:
19 - axis,artpec8-dw-mshc
20 - samsung,exynos4210-dw-mshc
21 - samsung,exynos4412-dw-mshc
[all …]
H A Dmarvell,xenon-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
29 - items:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/frequency/
H A Dadf4350.txt4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
21 - adi,reference-div2-enable: Enables reference divider.
[all …]
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
[all …]
/freebsd/sys/dev/clk/rockchip/
H A Drk_cru.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
73 /* Fixed factor multipier/divider. */
123 /* Fractional rate multipier/divider. */
157 /* Composite clock without mux (divider only). */
174 /* Complex clock without divider (multiplexer only). */
186 .width = _mw, \
194 /* Complex clock without divider (multiplexer only in GRF). */
206 .width = _mw, \
/freebsd/sys/arm/mv/clk/
H A Dperiph.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
69 .clk_def.full_dd.tbg_mux.width = 0x2, \
90 .clk_def.full_dd.clk_mux.width = 0x1, \
111 .clk_def.full_d.tbg_mux.width = 0x2, \
124 .clk_def.full_d.clk_mux.width = 0x1, \
144 .clk_def.cpu.tbg_mux.width = 0x2, \
157 .clk_def.cpu.clk_mux.width = 0x1, \
187 .clk_def.mdd.tbg_mux.width = 0x2, \
208 .clk_def.mdd.clk_mux.width = 0x1, \
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl-gw551x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/media/tda1997x.h>
8 #include <dt-bindings/input/linux-event-codes.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/sound/fsl-imx-audmux.h>
26 gpio-keys {
27 compatible = "gpio-keys";
29 user-pb {
35 user-pb1x {
[all …]
H A Dimx6qdl-gw51xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
24 gpio-keys {
25 compatible = "gpio-keys";
27 user-pb {
33 user-pb1x {
36 interrupt-parent = <&gsc>;
40 key-erased {
[all …]
H A Dimx6qdl-gw553x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
21 stdout-path = &uart2;
24 gpio-keys {
25 compatible = "gpio-keys";
27 user-pb {
33 user-pb1x {
36 interrupt-parent = <&gsc>;
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
42 #include <dt-bindings/clock/tegra210-car.h>
71 #define PLL_FLAG_PDIV_POWER2 0x01 /* P Divider is 2^n */
113 /* Post divider <-> register value mapping. */
115 uint32_t divider; /* real divider */ member
161 .width = w, \
164 /* Fractional divider (7.1) for PLL branch. */
179 /* P divider (2^n). for PLL branch. */
192 /* P divider (2^n). for PLL branch. */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-venice-gw702x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/net/ti-dp83867.h>
23 gpio-keys {
24 compatible = "gpio-keys";
26 key-user-pb {
32 key-user-pb1x {
35 interrupt-parent = <&gsc>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/altera/
H A Dsocfpga-clk-manager.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dinh Nguyen <dinguyen@kernel.org>
20 - const: altr,clk-mgr
30 "#address-cells":
33 "#size-cells":
37 "^osc[0-9]$":
40 "^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$":
[all …]

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