Lines Matching +full:divider +full:- +full:width
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
69 .clk_def.full_dd.tbg_mux.width = 0x2, \
90 .clk_def.full_dd.clk_mux.width = 0x1, \
111 .clk_def.full_d.tbg_mux.width = 0x2, \
124 .clk_def.full_d.clk_mux.width = 0x1, \
144 .clk_def.cpu.tbg_mux.width = 0x2, \
157 .clk_def.cpu.clk_mux.width = 0x1, \
187 .clk_def.mdd.tbg_mux.width = 0x2, \
208 .clk_def.mdd.clk_mux.width = 0x1, \
222 .clk_def.mux_gate.mux.width = 0x1, \
243 .clk_def.mux_gate_fixed.mux.width = 0x1, \
265 .clk_def.fixed.mux.width = 0x1, \
343 /* Double divider clock */
345 /* Single divider clock */
353 /* Clock with fixed frequency divider */
355 /* Clock with double divider, without gate */