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/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dmicrochip,corepwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Conor Dooley <conor.dooley@microchip.com>
16 https://www.microsemi.com/existing-parts/parts/152118
19 - $ref: pwm.yaml#
24 - const: microchip,corepwm-rtl-v4
32 "#pwm-cells":
37 microchip,sync-update-mask:
40 In synchronous mode, all channels are updated at the beginning of the PWM period,
[all …]
/freebsd/sys/dev/sound/pcm/
H A Dac97.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
51 unsigned mask:1; /* use only masked bits */ member
96 [SOUND_MIXER_IGAIN] = { -AC97_MIX_MIC, 1, 6, 0, 0, 0, 1, 1 },
100 [SOUND_MIXER_RECLEV] = { -AC97_MIX_RGAIN, 4, 0, 1, 1, 0, 0, 1 }
109 { 0x434d4900, "C-Media Electronics" },
180 { 0x43585430, 0x00, 0, "CX20468-21", 0 },
285 "18 bit DAC",
286 "20 bit DAC",
298 "center DAC",
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/freebsd/sys/arm/allwinner/
H A Da10_codec.c1 /*-
2 * Copyright (c) 2014-2016 Jared D. McNeill <jmcneill@invisible.ca>
61 /* toggle DAC/ADC mute */
84 #define AC_DAC_DPC(_sc) ((_sc)->cfg->DPC)
86 #define AC_DAC_FIFOC(_sc) ((_sc)->cfg->DAC_FIFOC)
110 #define AC_DAC_FIFOS(_sc) ((_sc)->cfg->DAC_FIFOS)
111 #define AC_DAC_TXDATA(_sc) ((_sc)->cfg->DAC_TXDATA)
112 #define AC_ADC_FIFOC(_sc) ((_sc)->cfg->ADC_FIFOC)
124 #define AC_ADC_FIFOS(_sc) ((_sc)->cfg->ADC_FIFOS)
125 #define AC_ADC_RXDATA(_sc) ((_sc)->cfg->ADC_RXDATA)
[all …]
/freebsd/sys/dev/sound/pci/
H A Dspicds.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
49 unsigned int dvc; /* De-emphasis and Volume Control */
59 if (codec->cif) in spicds_wrbit()
67 codec->ctrl(codec->devinfo, cs, 0, cdti); in spicds_wrbit()
69 codec->ctrl(codec->devinfo, cs, 1, cdti); in spicds_wrbit()
78 int mask; in spicds_wrcd() local
81 device_printf(codec->dev, "spicds_wrcd(codec, 0x%02x, 0x%02x)\n", reg, val); in spicds_wrcd()
84 if (codec->cif) in spicds_wrcd()
85 codec->ctrl(codec->devinfo, 1, 1, 0); in spicds_wrcd()
[all …]
H A Denvy24.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 /* -------------------------------------------------------------------- */
40 #define PCIR_MT 0x1c /* Professional Multi-Track I/O Base Address */
48 #define PCIM_LAC_MPU401 0x0008 /* MPU-401 I/O enable */
60 #define PCIM_LCC_MPUBASE 0x0006 /* MPU-401 base 300h-330h */
68 #define PCIM_SCFG_MPU 0x20 /* 1(0)/2(1) MPU-401 UART(s) */
71 #define PCIM_SCFG_ADC 0x0c /* 1-4 stereo ADC connected */
72 #define PCIM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */
74 #define PCIR_ACL 0x61 /* AC-Link Configuration Register */
[all …]
H A Dcs4281.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
65 /* ------------------------------------------------------------------------- */
101 /* -------------------------------------------------------------------- */
104 /* ADC/DAC control */
122 /* -------------------------------------------------------------------- */
143 /* -------------------------------------------------------------------- */
149 return bus_space_read_4(sc->st, sc->sh, regno); in cs4281_rd()
155 bus_space_write_4(sc->st, sc->sh, regno, data); in cs4281_wr()
160 cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask) in cs4281_clr4() argument
[all …]
H A Dvibes.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 /* ------------------------------------------------------------------------- */
59 /* ------------------------------------------------------------------------- */
115 /* ------------------------------------------------------------------------- */
123 return bus_space_read_1(sc->enh_st, sc->enh_sh, reg); in sv_direct_get()
130 bus_space_write_1(sc->enh_st, sc->enh_sh, reg, val); in _sv_direct_set()
134 …device_printf(sc->dev, "sv_direct_set register 0x%02x %d != %d from line %d\n", reg, n, val, line); in _sv_direct_set()
144 bus_space_write_1(sc->enh_st, sc->enh_sh, SV_CM_INDEX, reg); in sv_indirect_get()
145 return bus_space_read_1(sc->enh_st, sc->enh_sh, SV_CM_DATA); in sv_indirect_get()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dst,sti-asoc-card.txt3 The sti ASoC Sound Card can be used, for all sti SoCs using internal sti-sas
8 Documentation/devicetree/bindings/sound/simple-card.yaml.
10 1) sti-uniperiph-dai: audio dai device.
11 ---------------------------------------
14 - compatible: "st,stih407-uni-player-hdmi", "st,stih407-uni-player-pcm-out",
15 "st,stih407-uni-player-dac", "st,stih407-uni-player-spdif",
16 "st,stih407-uni-reader-pcm_in", "st,stih407-uni-reader-hdmi",
18 - st,syscfg: phandle to boot-device system configuration registers
20 - clock-names: name of the clocks listed in clocks property in the same order
22 - reg: CPU DAI IP Base address and size entries, listed in same
[all …]
/freebsd/contrib/ntp/include/
H A Dgps.h3 /* TrueTime GPS-VME and VME-SG */
23 #define MASKDAY 0x0FFF /* mask for units days */
27 W(0x0057), +(0x002B), - (0x002D) */
40 #define PMODE 0x00A4 /* Position mode */
43 #define DAC 0x0055 /* OSC Control (DAC) select */ macro
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp157c-ed1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 /dts-v1/;
10 #include "stm32mp15-pinctrl.dtsi"
11 #include "stm32mp15xxaa-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/mfd/st,stpmic1.h>
17 compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
24 stdout-path = "serial0:115200n8";
32 reserved-memory {
[all …]
H A Dstm32mp157c-emstamp-argon.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include "stm32mp15-pinctrl.dtsi"
10 #include "stm32mp15xxac-pinctrl.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/mfd/st,stpmic1.h>
23 stdout-path = "serial0:115200n8";
31 reserved-memory {
32 #address-cell
[all...]
H A Dstm32mp15xx-dhcom-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
6 #include "stm32mp15-pinctrl.dtsi"
7 #include "stm32mp15xxaa-pinctrl.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-binding
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/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dst_fdma.txt3 The FDMA is a general-purpose direct memory access controller capable of
10 - compatible : Should be one of
11 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
12 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
13 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
14 - reg : Should contain an entry for each name in reg-names
15 - reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries
16 - interrupts : Should contain one interrupt shared by all channels
17 - dma-channels : Number of channels supported by the controller
18 - #dma-cells : Must be <3>. See DMA client section below
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5312/
H A Dar5312_reset.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
62 #define V(r, c) (ia)->data[((r)*(ia)->cols) + (c)] in write_common()
66 for (i = 0; i < ia->rows; i++) { in write_common()
83 * vectors (as determined by the mode), and station configuration
110 HALASSERT(ah->ah_magic == AR5212_MAGIC); in ar5312Reset()
111 ee = AH_PRIVATE(ah)->ah_eeprom; in ar5312Reset()
121 __func__, chan->ic_freq, chan->ic_flags); in ar5312Reset()
[all …]
/freebsd/sys/dev/al_eth/
H A Dal_init_eth_lm.c1 /*-
73 /* 40GBASE-LR4 and 40GBASE-SR4 are optic modules */
111 uint8_t mask; member
115 {.addr = 0x0A, .value = 0x0C, .mask = 0xff },
116 {.addr = 0x2F, .value = 0x54, .mask = 0xff },
117 {.addr = 0x31, .value = 0x20, .mask = 0xff },
118 {.addr = 0x1E, .value = 0xE9, .mask = 0xff },
119 {.addr = 0x1F, .value = 0x0B, .mask = 0xff },
120 {.addr = 0xA6, .value = 0x43, .mask = 0xff },
121 {.addr = 0x2A, .value = 0x5A, .mask = 0xff },
[all …]
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_regs.h22 Boston, MA 02110-1301, USA.
32 /* N-PHY registers. */
41 #define BWN_NPHY_4WI_ADDR BWN_PHY_N(0x00B) /* Four-wire bus address */
42 #define BWN_NPHY_4WI_DATAHI BWN_PHY_N(0x00C) /* Four-wire bus data high */
43 #define BWN_NPHY_4WI_DATALO BWN_PHY_N(0x00D) /* Four-wire bus data low */
44 #define BWN_NPHY_BIST_STAT0 BWN_PHY_N(0x00E) /* Built-in self test status 0 */
45 #define BWN_NPHY_BIST_STAT1 BWN_PHY_N(0x00F) /* Built-in self test status 1 */
58 #define BWN_NPHY_C1_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */
116 #define BWN_NPHY_C2_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */
273 #define BWN_NPHY_SCRAM_SIGCTL_SCM 0x0080 /* Scram control mode */
[all …]
/freebsd/sys/kern/
H A Dsubr_acl_posix1e.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 1999-2006 Robert N. M. Watson
71 * Look for a normal, non-privileged way to access the file/directory in vaccess_acl_posix1e()
79 * Determine privileges now, but don't apply until we've found a DAC in vaccess_acl_posix1e()
119 for (i = 0; i < acl->acl_cnt; i++) { in vaccess_acl_posix1e()
120 switch (acl->acl_entry[i].ae_tag) { in vaccess_acl_posix1e()
122 if (file_uid != cred->cr_uid) in vaccess_acl_posix1e()
126 if (acl->acl_entry[i].ae_perm & ACL_EXECUTE) in vaccess_acl_posix1e()
128 if (acl->acl_entry[i].ae_perm & ACL_READ) in vaccess_acl_posix1e()
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_ssi.c1 /*-
60 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
62 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
74 #define SCR_I2S_MODE_S 5 /* I2S Mode Select. */
77 #define SCR_NET (1 << 3) /* Network mode */
125 #define SSI_STMSK 0x48 /* Transmit Time Slot Mask Register */
126 #define SSI_SRMSK 0x4C /* Receive Time Slot Mask Register */
156 * Fref ------/ | | | | | | | | | |
157 * PLL4 div select -/ | | | | | | | | |
158 * PLL4 num --------------/ | | | | | | | |
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210_reset.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2004 Atheros Communications, Inc.
41 /* gain delta pc dac */
51 * on the host machine (don't know--the problem was identified
64 * vectors (as determined by the mode), and station configuration
78 const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom; in ar5210Reset()
86 opmode, chan->ic_freq, chan->ic_flags, in ar5210Reset()
90 /* Only 11a mode */ in ar5210Reset()
[all …]
/freebsd/usr.sbin/bhyve/amd64/
H A Dvga.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
129 uint8_t gc_mode_rm; /* read mode */
130 uint8_t gc_mode_wm; /* write mode */
132 uint8_t gc_misc_gm; /* graphics mode */
159 * DAC
175 return (((sc->vga_seq.seq_clock_mode & SEQ_CM_SO) != 0) || in vga_in_reset()
176 ((sc->vga_seq.seq_reset & SEQ_RESET_ASYNC) == 0) || in vga_in_reset()
177 ((sc->vga_seq.seq_reset & SEQ_RESET_SYNC) == 0) || in vga_in_reset()
178 ((sc->vga_crtc.crtc_mode_ctrl & CRTC_MC_TE) == 0)); in vga_in_reset()
[all …]
/freebsd/sys/dev/vge/
H A Dif_vgereg.h1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
84 #define VGE_IMR 0x28 /* Interrupt mask register */
119 #define VGE_SSTIMER 0x74 /* single-shot timer */
188 #define VGE_RXCTL_RX_PROMISC 0x10 /* promisc mode */
233 #define VGE_CR3_INT_SWPEND 0x01 /* disable multi-level int bits */
234 #define VGE_CR3_INT_GMSK 0x02 /* mask off all interrupts */
[all …]
H A Dif_vge.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
46 * combines a tri-speed ethernet MAC and PHY, with the following
54 * o 64-bit multicast hash table filter
66 * receive data buffers must be aligned on a 32-bit boundary. This is
67 * not a problem where the VT6122 is used as a LOM device in x86-based
71 * The other issue has to do with the way 64-bit addresses are handled.
74 * I/O registers. If you only have a 32-bit system, then this isn't
75 * an issue, but if you have a 64-bit system and more than 4GB of
[all …]
/freebsd/stand/i386/libi386/
H A Dvbe.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
59 * palette array for 8-bit indexed colors. In this case, cmap does store
108 if (strcasecmp(res->name, cmp) == 0) in vbe_resolution_compare()
110 if (res->alias != NULL && strcasecmp(res->alias, cmp) == 0) in vbe_resolution_compare()
132 *width = res->width; in vbe_get_max_resolution()
133 *height = res->height; in vbe_get_max_resolution()
243 return ((vbe->Capabilities & VBE_CAP_NONVGA) == 0); in vbe_is_vga()
246 /* Actually assuming mode 3. */
248 bios_set_text_mode(int mode) in bios_set_text_mode() argument
[all …]
/freebsd/sys/dev/fb/
H A Dvga.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1999 Kazutaka YOKOTA <yokota@zodiac.mech.utsunomiya-u.ac.jp>
5 * Copyright (c) 1992-1998 Søren Schmidt
68 /* XXX machine/pc/bios.h has got too much i386-specific stuff in it */
83 error = (*sw->probe)(unit, &adp, NULL, flags); in vga_probe_unit()
100 error = (*sw->probe)(unit, &sc->adp, NULL, flags); in vga_attach_unit()
103 return (*sw->init)(unit, sc->adp, flags); in vga_attach_unit()
106 /* LOW-LEVEL */
113 #define probe_done(adp) ((adp)->va_flags & V_ADP_PROBED)
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300reg.h32 /* MAC Control Register - only write values of 1 have effect */
37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
51 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 // Mask of PCI core master request queue…
55 /* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */
109 #define AR_FTRIG 0x000003F0 // Mask for Frame trigger level
124 #define AR_RXCFG_ZLFDMA 0x00000010 // Enable DMA of zero-length frame
148 #define AR_TOPS_MASK 0x0000FFFF // Mask for timeout prescale
152 #define AR_RXNPTO_MASK 0x000003FF // Mask for no frame received timeout
156 #define AR_TXNPTO_MASK 0x000003FF // Mask for no frame transmitted timeout
[all …]

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