Lines Matching +full:dac +full:- +full:mode +full:- +full:mask
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
84 #define VGE_IMR 0x28 /* Interrupt mask register */
119 #define VGE_SSTIMER 0x74 /* single-shot timer */
188 #define VGE_RXCTL_RX_PROMISC 0x10 /* promisc mode */
233 #define VGE_CR3_INT_SWPEND 0x01 /* disable multi-level int bits */
234 #define VGE_CR3_INT_GMSK 0x02 /* mask off all interrupts */
245 #define VGE_INTCTL_MASK 0x18 /* multilayer int mask */
307 /* Interrupt mask register */
386 * - The behavior of the MAR0/MAR1 registers at offset 0x10 (the
389 * - The behavior of the interrupt holdoff timer register at offset
393 * - The behavior the WOL pattern programming registers at offset
400 #define VGE_CAMCTL_INTPKT_ENB 0x20 /* enable interesting packet mode */
433 #define VGE_PHYSTS_SPEED10 0x04 /* PHY in 10Mbps mode */
434 #define VGE_PHYSTS_SPEED1000 0x08 /* PHY in giga mode */
435 #define VGE_PHYSTS_FDX 0x10 /* PHY in full duplex mode */
445 #define VGE_MIICMD_MDP 0x10 /* enable direct programming mode */
446 #define VGE_MIICMD_WCMD 0x20 /* embedded mode write */
447 #define VGE_MIICMD_RCMD 0x40 /* embedded mode read */
456 #define VGE_CHIPCFG0_PACPI 0x01 /* pre-ACPI wakeup function */
470 #define VGE_CHIPCFG1_SLOTTIME 0x20 /* slot time 512/500 in giga mode */
480 #define VGE_CHIPCFG3_64BIT_DAC 0x20 /* enable 64bit via DAC */
481 #define VGE_CHIPCFG3_IODISABLE 0x80 /* disable I/O access mode */
537 #define VGE_TXCFG_NONBLK 0x02 /* priority TX/non-blocking mode */
538 #define VGE_TXCFG_NONBLK_THR 0x0C /* non-blocking threshold */
590 #define VGE_MIB_CNT (VGE_MIB_TX_LATECOLLS - VGE_MIB_RX_FRAMES + 1)
636 #define VGE_EECSR_DPM 0x10 /* direct program mode enable */
638 #define VGE_EECSR_EMBP 0x40 /* embedded program mode enable */
654 #define VGE_DIAGCTL_MACFORCE 0x10 /* MAC side force mode */
656 #define VGE_DIAGCTL_FDXFORCE 0x40 /* force full duplex mode */
657 #define VGE_DIAGCTL_GMII 0x80 /* force GMII mode, otherwise MII */