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/linux/include/linux/
H A Dtimecounter.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #define CYCLECOUNTER_MASK(bits) (u64)((bits) < 64 ? ((1ULL<<(bits))-1) : -1)
17 * struct cyclecounter - hardware abstraction for a free running counter
18 * Provides completely state-free accessors to the underlying hardware.
19 * Depending on which hardware it reads, the cycle counter may wrap
23 * @read: returns the current cycle value
25 * subtraction of non-64-bit counters,
27 * @mult: cycle to nanosecond multiplier
28 * @shift: cycle to nanosecond divisor (power of two)
38 * struct timecounter - layer above a &struct cyclecounter which counts nanoseconds
[all …]
/linux/drivers/staging/vme_user/
H A Dvme_fake.c1 // SPDX-License-Identifier: GPL-2.0-or-later
49 u32 cycle; member
57 u32 cycle; member
99 bridge = fake_bridge->driver_priv; in fake_VIRQ_tasklet()
101 vme_irq_handler(fake_bridge, bridge->int_level, bridge->int_statid); in fake_VIRQ_tasklet()
132 bridge = fake_bridge->driver_priv; in fake_irq_generate()
134 mutex_lock(&bridge->vme_int); in fake_irq_generate()
136 bridge->int_level = level; in fake_irq_generate()
138 bridge->int_statid = statid; in fake_irq_generate()
144 tasklet_schedule(&bridge->int_tasklet); in fake_irq_generate()
[all …]
H A Dvme_tsi148.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for the Tundra TSI148 VME-PCI Bridge Chip
20 #include <linux/dma-mapping.h>
80 wake_up(&bridge->dma_queue[0]); in tsi148_DMA_irqhandler()
84 wake_up(&bridge->dma_queue[1]); in tsi148_DMA_irqhandler()
468 tsi148_slave_set(struct vme_slave_resource * image,int enabled,unsigned long long vme_base,unsigned long long size,dma_addr_t pci_base,u32 aspace,u32 cycle) tsi148_slave_set() argument
611 tsi148_slave_get(struct vme_slave_resource * image,int * enabled,unsigned long long * vme_base,unsigned long long * size,dma_addr_t * pci_base,u32 * aspace,u32 * cycle) tsi148_slave_get() argument
800 tsi148_master_set(struct vme_master_resource * image,int enabled,unsigned long long vme_base,unsigned long long size,u32 aspace,u32 cycle,u32 dwidth) tsi148_master_set() argument
1035 __tsi148_master_get(struct vme_master_resource * image,int * enabled,unsigned long long * vme_base,unsigned long long * size,u32 * aspace,u32 * cycle,u32 * dwidth) __tsi148_master_get() argument
1144 tsi148_master_get(struct vme_master_resource * image,int * enabled,unsigned long long * vme_base,unsigned long long * size,u32 * aspace,u32 * cycle,u32 * dwidth) tsi148_master_get() argument
1163 u32 aspace, cycle, dwidth; tsi148_master_read() local
1248 u32 aspace, cycle, dwidth; tsi148_master_write() local
1401 tsi148_dma_set_vme_src_attributes(struct device * dev,__be32 * attr,u32 aspace,u32 cycle,u32 dwidth) tsi148_dma_set_vme_src_attributes() argument
1499 tsi148_dma_set_vme_dest_attributes(struct device * dev,__be32 * attr,u32 aspace,u32 cycle,u32 dwidth) tsi148_dma_set_vme_dest_attributes() argument
1902 tsi148_lm_set(struct vme_lm_resource * lm,unsigned long long lm_base,u32 aspace,u32 cycle) tsi148_lm_set() argument
1967 tsi148_lm_get(struct vme_lm_resource * lm,unsigned long long * lm_base,u32 * aspace,u32 * cycle) tsi148_lm_get() argument
[all...]
/linux/arch/alpha/lib/
H A Dev6-csum_ipv6_magic.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-csum_ipv6_magic.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17 * E - either cluster
18 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
32 * Then turn it back into a sign extended 32-bit item
35 * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
36 * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
[all …]
/linux/scripts/
H A Dheaderdep.pl2 # SPDX-License-Identifier: GPL-2.0
46 print " --all\n";
47 print " --graph\n";
49 print " -I includedir\n";
52 print " $0 --graph include/linux/kernel.h | dot -Tpng -o graph.png\n";
78 return $filename if -f $filename;
82 return $path if -f $path;
107 push @{$deps{$header}}, [$i + 1, $dep];
114 # $cycle[n] includes $cycle[n + 1];
115 # $cycle[-1] will be the culprit
[all …]
/linux/tools/testing/selftests/tc-testing/tc-tests/actions/
H A Dgate.json4 "name": "Add gate action with priority and sched-entry",
16 1,
20 … "cmdUnderTest": "$TC action add action gate priority 1 sched-entry close 100000000ns index 100",
23 "matchPattern": "action order [0-9]*: .*priority 1.*index 100 ref",
24 "matchCount": "1",
31 "name": "Add gate action with base-time",
43 1,
47 …"cmdUnderTest": "$TC action add action gate base-time 200000000000ns sched-entry close 100000000ns…
50 "matchPattern": "action order [0-9]*: .*base-time 200s.*index 10 ref",
51 "matchCount": "1",
[all …]
/linux/Documentation/hwmon/
H A Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
[all …]
H A Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
31 UCH1, bit 1 maps to UCH2 and so on. Setting a bit to 1
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
51 temp2), 1 dedicated voltage (in5) and 2 fans. Additionally, the chip
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
[all …]
H A Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
35 A "0" allows SMBus block data transactions if the host supports them. A "1"
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
[all …]
/linux/drivers/pwm/
H A Dpwm-sl28cpld.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * enough to be briefly explained. It consists of one 8-bit counter. The PWM
15 * +-----------+--------+--------------+-----------+---------------+
17 * +-----------+--------+--------------+-----------+---------------+
19 * | 1 | cnt[6] | cnt[5:0] | 500 Hz | 2000000 ns |
20 * | 2 | cnt[5] | cnt[4:0] | 1 kHz | 1000000 ns |
22 * +-----------+--------+--------------+-----------+---------------+
25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
26 * - The hardware cannot atomically set the prescaler and the counter value,
28 * - The counter is not reset if you switch the prescaler which leads
[all …]
H A Dpwm-xilinx.c1 // SPDX-License-Identifier: GPL-2.0+
6 * - When changing both duty cycle and period, we may end up with one cycle
7 * with the old duty cycle and the new period. This is because the counters
9 * automatically reloaded at the end of a cycle. If this automatic reload
11 * bad cycle. This could probably be fixed by reading TCR0 just before
13 * - Cannot produce 100% duty cycle by configuring the TLRs. This might be
14 * possible by stopping the counters at an appropriate point in the cycle,
16 * - Only produces "normal" output.
17 * - Always produces low output if disabled.
20 #include <clocksource/timer-xilinx.h>
[all …]
H A Dpwm-ntxec.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * e-book readers designed by the original design manufacturer Netronix, Inc.
13 * - The get_state callback is not implemented, because the current state of
15 * - The hardware can only generate normal polarity output.
16 * - The period and duty cycle can't be changed together in one atomic action.
44 * The time base used in the EC is 8MHz, or 125ns. Period and duty cycle are
62 * Changes to the period and duty cycle take effect as soon as the in ntxec_pwm_set_raw_period_and_duty_cycle()
65 * duty cycle is fully written. If, in such a case, the old duty cycle in ntxec_pwm_set_raw_period_and_duty_cycle()
68 * To minimize the time between the changes to period and duty cycle in ntxec_pwm_set_raw_period_and_duty_cycle()
79 return regmap_multi_reg_write(priv->ec->regmap, regs, ARRAY_SIZE(regs)); in ntxec_pwm_set_raw_period_and_duty_cycle()
[all …]
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_tas.c1 // SPDX-License-Identifier: GPL-2.0
7 #define SJA1105_TAS_CLKSRC_STANDALONE 1
10 #define SJA1105_GATE_MASK GENMASK_ULL(SJA1105_NUM_TC - 1, 0)
19 struct sja1105_tas_data *tas_data = &priv->tas_data; in sja1105_tas_set_runtime_params()
20 struct sja1105_gating_config *gating_cfg = &tas_data->gating_cfg; in sja1105_tas_set_runtime_params()
21 struct dsa_switch *ds = priv->ds; in sja1105_tas_set_runtime_params()
28 tas_data->enabled = false; in sja1105_tas_set_runtime_params()
30 for (port = 0; port < ds->num_ports; port++) { in sja1105_tas_set_runtime_params()
33 offload = tas_data->offload[port]; in sja1105_tas_set_runtime_params()
37 tas_data->enabled = true; in sja1105_tas_set_runtime_params()
[all …]
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
5 "CounterMask": "1",
14 "Counter": "0,1,2,3",
23 "Counter": "0,1,2,3",
32 "Counter": "0,1,2,3",
41 "Counter": "0,1,2,3",
49 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
50 "Counter": "0,1,2,3",
53 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
58 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
[all …]
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
5 "CounterMask": "1",
14 "Counter": "0,1,2,3",
23 "Counter": "0,1,2,3",
32 "Counter": "0,1,2,3",
41 "Counter": "0,1,2,3",
49 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
50 "Counter": "0,1,2,3",
53 …PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
58 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A Dfloating-point.json5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
20 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.",
27 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.",
34 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
[all …]
/linux/sound/firewire/
H A Damdtp-stream.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Audio and Music Data Transmission Protocol (IEC 61883-6) streams
4 * with Common Isochronous Packet (IEC 61883-1) headers
12 #include <linux/firewire-constants.h>
17 #include "amdtp-stream.h"
27 #include "amdtp-stream-trace.h"
34 #define TAG_CIP 1
39 #define CIP_EOH (1u << CIP_EOH_SHIFT)
83 * amdtp_stream_init - initialize an AMDTP stream structure
87 * @flags: the details of the streaming protocol consist of cip_flags enumeration-constants.
[all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A Dpipeline.json4 "Counter": "0,1,2,3",
7 "PEBS": "1",
13 "Counter": "0,1,2,3",
16 "PEBS": "1",
22 "Counter": "0,1,2,3",
25 "PEBS": "1",
31 "Counter": "0,1,2,3",
34 "PEBS": "1",
40 "Counter": "0,1,2,3",
43 "PEBS": "1",
[all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Dpipeline.json4 "Counter": "0,1,2,3",
7 "PEBS": "1",
13 "Counter": "0,1,2,3",
16 "PEBS": "1",
22 "Counter": "0,1,2,3",
25 "PEBS": "1",
31 "Counter": "0,1,2,3",
34 "PEBS": "1",
40 "Counter": "0,1,2,3",
43 "PEBS": "1",
[all …]
/linux/tools/perf/pmu-events/arch/x86/alderlaken/
H A Dpipeline.json4 "Counter": "0,1,2,3,4,5",
7 "PEBS": "1",
13 "Counter": "0,1,2,3,4,5",
14 "Deprecated": "1",
17 "PEBS": "1",
23 "Counter": "0,1,2,3,4,5",
26 "PEBS": "1",
32 "Counter": "0,1,2,3,4,5",
35 "PEBS": "1",
41 "Counter": "0,1,2,3,4,5",
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A Dfloating-point.json6 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
13 … Each increment represents a one-cycle dispatch event. This event is a speculative event. Since th…
20 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
26 "BriefDescription": "Total number uOps assigned to pipe 1.",
27 …- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric o…
34 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
40 …n": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e…
46 …-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The num…
52 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
58 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Drenesas,sh-msiof.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: spi-controller.yaml#
18 - items:
19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5
20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
22 - items:
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dpwm-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/pwm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
11 - Lee Jones <lee@kernel.org>
12 - Alexandre Courbot <acourbot@nvidia.com>
19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
23 is given to the user if the assumptions made in continuous-voltage mode do
[all …]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
5 "CounterMask": "1",
13 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
29 "Counter": "0,1,2,3",
37 "Counter": "0,1,2,3",
44 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
45 "Counter": "0,1,2,3",
52 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
53 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
5 "CounterMask": "1",
13 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
29 "Counter": "0,1,2,3",
37 "Counter": "0,1,2,3",
44 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issue…
45 "Counter": "0,1,2,3",
52 …"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issue…
53 "Counter": "0,1,2,3",
[all …]

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