Lines Matching +full:cycle +full:- +full:1
4 "Counter": "0,1,2,3,4,5",
5 "CounterMask": "1",
12 "BriefDescription": "Counts the number of active floating point and integer dividers per cycle.",
13 "Counter": "0,1,2,3,4,5",
20 "BriefDescription": "Counts the number of floating point and integer divider uops executed per cycle.",
21 "Counter": "0,1,2,3,4,5",
29 "Counter": "0,1,2,3,4,5",
30 "CounterMask": "1",
37 "BriefDescription": "Counts the number of active integer dividers per cycle.",
38 "Counter": "0,1,2,3,4,5",
45 "BriefDescription": "Counts the number of integer divider uops executed per cycle.",
46 "Counter": "0,1,2,3,4,5",
54 "Counter": "0,1,2,3,4,5",
62 "Counter": "0,1,2,3,4,5",
63 "Deprecated": "1",
71 "Counter": "0,1,2,3,4,5",
79 "Counter": "0,1,2,3,4,5",
87 "Counter": "0,1,2,3,4,5",
95 "Counter": "0,1,2,3,4,5",
103 "Counter": "0,1,2,3,4,5",
111 "Counter": "0,1,2,3,4,5",
112 "Deprecated": "1",
120 "Counter": "0,1,2,3,4,5",
121 "Deprecated": "1",
129 "Counter": "0,1,2,3,4,5",
137 "Counter": "0,1,2,3,4,5",
145 "Counter": "0,1,2,3,4,5",
153 "Counter": "0,1,2,3,4,5",
154 "Deprecated": "1",
162 "Counter": "0,1,2,3,4,5",
170 "Counter": "0,1,2,3,4,5",
171 "Deprecated": "1",
179 "Counter": "0,1,2,3,4,5",
180 "Deprecated": "1",
188 "Counter": "0,1,2,3,4,5",
191 "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
196 "Counter": "0,1,2,3,4,5",
204 "Counter": "0,1,2,3,4,5",
212 "Counter": "0,1,2,3,4,5",
220 "Counter": "0,1,2,3,4,5",
228 "Counter": "0,1,2,3,4,5",
229 "Deprecated": "1",
237 "Counter": "0,1,2,3,4,5",
238 "Deprecated": "1",
246 "Counter": "0,1,2,3,4,5",
254 "Counter": "0,1,2,3,4,5",
255 "Deprecated": "1",
263 "Counter": "0,1,2,3,4,5",
271 "Counter": "0,1,2,3,4,5",
272 "Deprecated": "1",
280 "Counter": "Fixed counter 1",
282 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
288 "Counter": "0,1,2,3,4,5",
296 "Counter": "0,1,2,3,4,5",
297 "Deprecated": "1",
313 "Counter": "0,1,2,3,4,5",
322 "Counter": "Fixed counter 1",
324 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
330 "Counter": "0,1,2,3,4,5",
346 "Counter": "0,1,2,3,4,5",
354 "Counter": "0,1,2,3,4,5",
355 "Deprecated": "1",
363 "Counter": "0,1,2,3,4,5",
371 "Counter": "0,1,2,3,4,5",
379 "Counter": "0,1,2,3,4,5",
387 "Counter": "0,1,2,3,4,5",
394 "BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.",
395 "Counter": "0,1,2,3,4,5",
403 "Counter": "0,1,2,3,4,5",
410 "BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.",
411 "Counter": "0,1,2,3,4,5",
419 "Counter": "0,1,2,3,4,5",
427 "BriefDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.",
428 "Counter": "0,1,2,3,4,5",
431 "PublicDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE.",
437 "Counter": "0,1,2,3,4,5",
444 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
445 "Counter": "0,1,2,3,4,5",
453 "Counter": "0,1,2,3,4,5",
460 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
461 "Counter": "0,1,2,3,4,5",
468 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).",
469 "Counter": "0,1,2,3,4,5",
476 "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
477 "Counter": "0,1,2,3,4,5",
483 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.",
484 "Counter": "0,1,2,3,4,5",
491 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
492 "Counter": "0,1,2,3,4,5",
499 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
500 "Counter": "0,1,2,3,4,5",
507 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
508 "Counter": "0,1,2,3,4,5",
515 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
516 "Counter": "0,1,2,3,4,5",
523 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
524 "Counter": "0,1,2,3,4,5",
531 "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.",
532 "Counter": "0,1,2,3,4,5",
538 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.",
539 "Counter": "0,1,2,3,4,5",
542 "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
547 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.",
548 "Counter": "0,1,2,3,4,5",
551 "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
556 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).",
557 "Counter": "0,1,2,3,4,5",
564 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.",
565 "Counter": "0,1,2,3,4,5",
572 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.",
573 "Counter": "0,1,2,3,4,5",
580 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.",
581 "Counter": "0,1,2,3,4,5",
588 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.",
589 "Counter": "0,1,2,3,4,5",
592 "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
597 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.",
598 "Counter": "0,1,2,3,4,5",
605 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.",
606 "Counter": "0,1,2,3,4,5",
614 "Counter": "0,1,2,3,4,5",
620 "BriefDescription": "Counts the number of uops issued by the front end every cycle.",
621 "Counter": "0,1,2,3,4,5",
624 "PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.",
629 "Counter": "0,1,2,3,4,5",
636 "Counter": "0,1,2,3,4,5",
643 "BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
644 "Counter": "0,1,2,3,4,5",
653 "Counter": "0,1,2,3,4,5",