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/linux/arch/powerpc/xmon/
H A Dppc-dis.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-dis.c -- Disassemble PowerPC instructions
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
15 #include "dis-asm.h"
18 the disassembler interface defined in dis-asm.h. Several functions
32 if (operand->extract) in operand_value_powerpc()
33 value = (*operand->extract) (insn, dialect, &invalid); in operand_value_powerpc()
36 if (operand->shift >= 0) in operand_value_powerpc()
37 value = (insn >> operand->shift) & operand->bitm; in operand_value_powerpc()
39 value = (insn << -operand->shift) & operand->bitm; in operand_value_powerpc()
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/linux/Documentation/devicetree/bindings/phy/
H A Dimg,pistachio-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/img,pistachio-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Bresticker <abrestic@chromium.org>
14 const: img,pistachio-usb-phy
19 clock-names:
21 - const: usb_phy
23 '#phy-cells':
26 phy-supply:
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/linux/Documentation/devicetree/bindings/sound/
H A Dimg,pistachio-internal-dac.txt5 - compatible: "img,pistachio-internal-dac"
7 - img,cr-top : Must contain a phandle to the top level control syscon
10 - VDD-supply : Digital power supply regulator (+1.8V or +3.3V)
14 internal_dac: internal-dac {
15 compatible = "img,pistachio-internal-dac";
16 img,cr-top = <&cr_top>;
17 VDD-supply = <&supply3v3>;
/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_vp8_if.c1 // SPDX-License-Identifier: GPL-2.0
52 * struct vdec_vp8_dec_info - decode misc information
59 * @resolution_changed: resolution change flag 1 - changed, 0 - not changed
76 * struct vdec_vp8_vsi - VPU shared information
92 * struct vdec_vp8_hw_reg_base - HW register base
95 * @top : base address for top
103 void __iomem *top; member
110 * struct vdec_vp8_vpu_inst - VPU instance for VP8 decode
112 * @signaled : 1 - Host has received ack message from VPU, 0 - not received
113 * @failure : VPU execution result status 0 - success, others - fail
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H A Dvdec_h264_req_if.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <media/v4l2-mem2mem.h>
6 #include <media/v4l2-h264.h>
7 #include <media/videobuf2-dma-contig.h>
17 * struct mtk_h264_dec_slice_param - parameters for decode current frame
28 * struct vdec_h264_dec_info - decode information
31 * @realloc_mv_buf : flag to notify driver to re-allocate mv buffer
33 * @bs_dma : Input bit-stream buffer dma address
50 * struct vdec_h264_vsi - shared memory for decode information exchange
55 * AP-W/R : AP is writer/reader on this item
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H A Dvdec_h264_if.c1 // SPDX-License-Identifier: GPL-2.0
35 * struct h264_fb - h264 decode frame buffer information
51 * struct h264_ring_fb_list - ring frame buffer list
67 * struct vdec_h264_dec_info - decode information
70 * @realloc_mv_buf : flag to notify driver to re-allocate mv buffer
72 * @bs_dma : Input bit-stream buffer dma address
89 * struct vdec_h264_vsi - shared memory for decode information exchange
94 * AP-W/R : AP is writer/reader on this item
95 * VPU-W/R: VPU is write/reader on this item
96 * @hdr_buf : Header parsing buffer (AP-W, VPU-R)
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H A Dvdec_vp9_if.c1 // SPDX-License-Identifier: GPL-2.0
5 * Kai-Sean Yang <kai-sean.yang@mediatek.com>
30 * struct vp9_dram_buf - contains buffer info for vpu
44 * struct vp9_fb_info - contains frame buffer info
54 * struct vp9_ref_cnt_buf - contains reference buffer information
65 * struct vp9_ref_buf - contains current frame's reference buffer information
77 * struct vp9_sf_ref_fb - contains frame buffer info
89 * struct vdec_vp9_vsi - shared buffer between host and VPU firmware
90 * AP-W/R : AP is writer/reader on this item
91 * VPU-W/R: VPU is write/reader on this item
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/linux/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
6 * Samsung EXYNOS5 SoC series G-Scaler driver
23 #include <media/v4l2-ioctl.h>
25 #include "gsc-core.h"
218 if (pixelformat && fmt->pixelformat == *pixelformat) in find_fmt()
220 if (mbus_code && fmt->mbus_code == *mbus_code) in find_fmt()
231 frame->f_width = width; in gsc_set_frame_size()
232 frame->f_height = height; in gsc_set_frame_size()
233 frame->crop.width = width; in gsc_set_frame_size()
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H A Dgsc-regs.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
6 * Samsung EXYNOS5 SoC series G-Scaler driver
12 #include "gsc-core.h"
16 writel(GSC_SW_RESET_SRESET, dev->regs + GSC_SW_RESET); in gsc_hw_set_sw_reset()
25 cfg = readl(dev->regs + GSC_SW_RESET); in gsc_wait_reset()
31 return -EBUSY; in gsc_wait_reset()
38 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
43 writel(cfg, dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
50 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_gsc_irq_enable()
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/linux/tools/perf/util/
H A Dthread-stack.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * thread-stack.c: Synthesize a thread's stack using call / return events
21 #include "call-path.h"
22 #include "thread-stack.h"
40 * struct thread_stack_entry - thread stack entry.
47 * @db_id: id used for db-export
68 * struct thread_stack - thread stack constructed from 'call' and 'return'
123 new_sz = ts->sz + STACK_GROWTH; in thread_stack__grow()
126 new_stack = realloc(ts->stack, sz); in thread_stack__grow()
128 return -ENOMEM; in thread_stack__grow()
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/linux/include/uapi/drm/
H A Ddrm_fourcc.h39 * further describe the buffer's format - for example tiling or compression.
42 * ---------
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/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
21 #include <media/media-entity.h>
22 #include <media/videobuf2-v4l2.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-mem2mem.h>
26 #include <media/v4l2-mediabus.h>
27 #include <media/drv-intf/exynos-fimc.h>
35 #define FIMC_DRIVER_NAME "exynos4-fimc"
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/linux/arch/powerpc/kernel/
H A Dhead_booke.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 * Macros used for common Book-e exception handling
32 * Note that entries 0-3 are used for the prolog code, and the remaining
53 mfcr r13; /* save CR in r13 for now */\
62 /* if from user, start at top of this thread's kernel stack */ \
63 lwz r11, TASK_STACK - THREAD(r10); \
101 addi r2, r2, -THREAD
122 mfcr r13 /* save CR in r13 for now */
139 lwz r1, TASK_STACK - THREAD(r10)
140 rlwinm r12,r12,0,4,2 /* Clear SO bit in CR */
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/linux/Documentation/fb/
H A Dpxafb.rst10 modprobe pxafb options=vmem:2M,mode:640x480-8,passive
14 video=pxafb:vmem:2M,mode:640x480-8,passive
21 mode:XRESxYRES[-BPP]
87 PXA27x and later processors support overlay1 and overlay2 on-top of the
88 base framebuffer (although under-neath the base is also possible). They
89 support palette and no-palette RGB formats, as well as YUV formats (only
96 1. overlay can start at a 32-bit word aligned position within the base
98 is encoded into var->nonstd (no, var->xoffset and var->yoffset are
104 var->xres_virtual * var->yres_virtual * bpp
106 bpp = 16 -- for RGB565 or RGBT555
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/linux/drivers/media/test-drivers/vicodec/
H A Dcodec-fwht.h1 /* SPDX-License-Identifier: LGPL-2.1+ */
17 * Each Y, Cb and Cr plane is compressed separately. If the compressed
23 * is run-length-encoded. Each macroblock starts with a 16 bit value.
24 * Bit 15 indicates if this is a P-coded macroblock (1) or not (0).
25 * P-coded macroblocks contain a delta against the previous frame.
27 * Bits 1-12 contain a number. If non-zero, then this same macroblock
31 * Following this macroblock header the MB coefficients are run-length
32 * encoded: the top 12 bits contain the coefficient, the bottom 4 bits
36 * All 16 and 32 bit values are stored in big-endian (network) order.
96 u8 *luma, *cb, *cr, *alpha; member
/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-regs.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include "camif-regs.h"
13 #define camif_write(_camif, _off, _val) writel(_val, (_camif)->io_base + (_off))
14 #define camif_read(_camif, _off) readl((_camif)->io_base + (_off))
27 if (camif->variant->ip_revision == S3C6410_CAMIF_IP_REV) in camif_hw_reset()
40 u32 cfg = camif_read(vp->camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_clear_pending_irq()
41 cfg |= CIGCTRL_IRQ_CLR(vp->id); in camif_hw_clear_pending_irq()
42 camif_write(vp->camif, S3C_CAMIF_REG_CIGCTRL, cfg); in camif_hw_clear_pending_irq()
58 unsigned int cr, unsigned int cb) in camif_hw_set_effect() argument
79 cfg = camif_read(camif, S3C_CAMIF_REG_CIIMGEFF(camif->vp->offset)); in camif_hw_set_effect()
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H A Dcamif-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 #include <media/media-entity.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-dev.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-mediabus.h>
25 #include <media/videobuf2-v4l2.h>
26 #include <media/drv-intf/s3c_camif.h>
28 #define S3C_CAMIF_DRIVER_NAME "s3c-camif"
39 #define S3C2450_CAMIF_IP_REV 0x30 /* 3.0 - not implemented, not tested */
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/linux/arch/mips/boot/dts/img/
H A Dpistachio.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/pistachio-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #include <dt-bindings/reset/pistachio-resets.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
22 #address-cells = <1>;
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/linux/drivers/media/pci/bt8xx/
H A Dbttv-risc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 bttv-risc.c -- interfaces to other kernel modules
7 - memory management
8 - generation
10 (c) 2000-2003 Gerd Knorr <kraxel@bytesex.org>
25 #include <media/v4l2-ioctl.h>
31 /* ---------------------------------------------------------- */
54 if ((rc = btcx_riscmem_alloc(btv->c.pci,risc,instructions)) < 0) in bttv_risc_packed()
58 rp = risc->cpu; in bttv_risc_packed()
62 while (skip_lines-- > 0) { in bttv_risc_packed()
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/linux/Documentation/devicetree/bindings/reset/
H A Dimg,pistachio-reset.txt6 control bits found in the Pistachio SoC top level registers.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
25 compatible = "img,pistachio-cr-periph", "syscon", "simple-mfd";
28 clock-names = "sys";
29 #clock-cells = <1>;
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
33 #reset-cells = <1>;
47 spdif_out: spdif-out@18100d00 {
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/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-codec-stateless.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _codec-stateless-controls:
18 .. _codec-stateless-control-id:
23 .. _v4l2-codec-stateless-h264:
43 .. flat-table:: struct v4l2_ctrl_h264_sps
44 :header-rows: 0
45 :stub-columns: 0
48 * - __u8
49 - ``profile_idc``
50 -
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/linux/drivers/media/platform/ti/am437x/
H A Dam437x-vpfe.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 - 2014 Texas Instruments, Inc.
12 #include <linux/am437x-vpfe.h>
20 #include <media/v4l2-dev.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-ioctl.h>
23 #include <media/videobuf2-v4l2.h>
24 #include <media/videobuf2-dma-contig.h>
26 #include "am437x-vpfe_regs.h"
36 /* BT656 - 8 bit */
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/linux/drivers/phy/
H A Dphy-pistachio-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <dt-bindings/phy/phy-pistachio-usb.h>
59 ret = clk_prepare_enable(p_phy->phy_clk); in pistachio_usb_phy_power_on()
61 dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret); in pistachio_usb_phy_power_on()
65 regmap_update_bits(p_phy->cr_top, USB_PHY_STRAP_CONTROL, in pistachio_usb_phy_power_on()
68 p_phy->refclk << USB_PHY_STRAP_CONTROL_REFCLK_SHIFT); in pistachio_usb_phy_power_on()
70 rate = clk_get_rate(p_phy->phy_clk); in pistachio_usb_phy_power_on()
71 if (p_phy->refclk == REFCLK_XO_CRYSTAL && rate != 12000000) { in pistachio_usb_phy_power_on()
72 dev_err(p_phy->dev, "Unsupported rate for XO crystal: %ld\n", in pistachio_usb_phy_power_on()
74 ret = -EINVAL; in pistachio_usb_phy_power_on()
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/linux/drivers/clocksource/
H A Dtimer-pistachio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Pistachio clocksource based on general-purpose timers
25 /* Top level reg */
80 raw_spin_lock_irqsave(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
81 overflow = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0); in pistachio_clocksource_read_cycles()
82 counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0); in pistachio_clocksource_read_cycles()
83 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
99 val = gpt_readl(pcs->base, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
105 gpt_writel(pcs->base, val, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
114 gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx); in pistachio_clksrc_enable()
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/linux/drivers/media/platform/st/sti/bdisp/
H A Dbdisp-hw.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "bdisp-filter.h"
11 #include "bdisp-reg.h"
27 bool cconv; /* RGB - YUV conversion */
371 dev_dbg(bdisp->dev, "%s\n", __func__); in bdisp_hw_reset()
374 writel(0, bdisp->regs + BLT_ITM0); in bdisp_hw_reset()
377 writel(readl(bdisp->regs + BLT_CTL) | BLT_CTL_RESET, in bdisp_hw_reset()
378 bdisp->regs + BLT_CTL); in bdisp_hw_reset()
379 writel(0, bdisp->regs + BLT_CTL); in bdisp_hw_reset()
383 if (readl(bdisp->regs + BLT_STA1) & BLT_STA1_IDLE) in bdisp_hw_reset()
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