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/freebsd/sys/contrib/device-tree/src/arm/intel/axm/
H A Daxm5516-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/boot/dts/axm5516-cpus.dtsi
10 #address-cells = <1>;
11 #size-cells = <0>;
13 cpu-map {
16 cpu = <&CPU0>;
19 cpu = <&CPU1>;
22 cpu = <&CPU2>;
25 cpu = <&CPU3>;
30 cpu = <&CPU4>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining
15 properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
34 cpus and cpu node bindings definition
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Dcpu-topology.txt2 CPU topology binding description
6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt6002.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
16 #include "multi-die-cpp.h"
18 #include "t600x-common.dtsi"
21 compatible = "apple,t6002", "apple,arm-platform";
23 #address-cells = <2>;
[all …]
H A Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
25 cpu = <&cpu_e00>;
28 cpu = <&cpu_e01>;
34 cpu = <&cpu_p00>;
37 cpu = <&cpu_p01>;
[all …]
H A Dt8015.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 interrupt-parent = <&aic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 clkref: clock-ref {
21 compatible = "fixed-clock";
[all …]
H A Dt7001.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/apple-aic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/pinctrl/apple.h>
15 interrupt-parent = <&aic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
23 clkref: clock-ref {
24 compatible = "fixed-clock";
[all …]
H A Dt8011.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 interrupt-parent = <&aic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 clkref: clock-ref {
21 compatible = "fixed-clock";
[all …]
H A Dt8103.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8103", "apple,arm-platform";
19 #address-cells = <2>;
20 #size-cells = <2>;
27 #address-cells = <2>;
[all …]
H A Dt8112.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8112", "apple,arm-platform";
19 #address-cells = <2>;
20 #size-cells = <2>;
27 #address-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Dfoundation-v8-spin-table.dtsi8 enable-method = "spin-table";
9 cpu-release-addr = <0x0 0x8000fff8>;
13 enable-method = "spin-table";
14 cpu-release-addr = <0x0 0x8000fff8>;
18 enable-method = "spin-table";
19 cpu-release-addr = <0x0 0x8000fff8>;
23 enable-method = "spin-table";
24 cpu-release-addr = <0x0 0x8000fff8>;
H A Drtsm_ve-aemv8a.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
38 #address-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10_swvp.dts1 // SPDX-License-Identifier: GPL-2.0
10 compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
27 stdout-path = "serial1:115200n8";
28 linux,initrd-start = <0x10000000>;
29 linux,initrd-end = <0x125c8324>;
39 enable-method = "spin-table";
40 cpu-release-addr = <0x0 0x0000fff8>;
44 enable-method = "spin-table";
45 cpu-release-addr = <0x0 0x0000fff8>;
49 enable-method = "spin-table";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/toshiba/
H A Dtmpv7708.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/clock/toshiba,tmpv770x.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Ds32v234.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
26 cpu0: cpu@0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstih418-b2264.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "st,stih418-b2264", "st,stih418";
14 stdout-path = &sbc_serial0;
23 cpu@0 {
24 operating-point
[all...]
H A Dstih418.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih418-clock.dtsi"
7 #include "stih407-family.dtsi"
8 #include "stih410-pinctrl.dtsi"
9 #include <dt-bindings/thermal/thermal.h>
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu2: cpu@2 {
15 device_type = "cpu";
16 compatible = "arm,cortex-a9";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8992-lg-h815.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 /dts-v1/;
13 #include <dt-bindings/leds/common.h>
16 /delete-node/ &cont_splash_mem;
19 /delete-node/ &dfps_data_mem;
24 chassis-type = "handset";
26 qcom,msm-id = <0xfb 0x0>;
27 qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>;
28 qcom,board-id = <0xb64 0x0>;
31 /delete-node/ psci;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 local_intc: interrupt-controller@40000000 {
13 compatible = "brcm,bcm2836-l1-intc";
15 interrupt-controller;
16 #interrupt-cells = <2>;
17 interrupt-parent = <&local_intc>;
21 arm-pmu {
22 compatible = "arm,cortex-a53-pmu";
23 interrupt-parent = <&local_intc>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Diss4xx-mpic.dts15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu@0 {
35 device_type = "cpu";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apm/
H A Dapm-shadowcat.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu@0 {
19 device_type = "cpu";
[all …]
/freebsd/sys/x86/x86/
H A Ducode.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
96 printf("CPU microcode: updated from %#jx to %#jx\n", in log_msg()
103 printf("CPU microcode: no matching update found\n"); in log_msg()
106 printf("CPU microcode: microcode verification failed\n"); in log_msg()
109 printf("CPU microcode load failed. BIOS update advised\n"); in log_msg()
177 size = hdr->total_size; in ucode_intel_verify()
182 if (hdr->header_version != 1) in ucode_intel_verify()
215 for (resid = *len; resid > 0; data += total_size, resid -= total_size) { in ucode_intel_match()
222 data_size = hdr->data_size; in ucode_intel_match()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/microchip/
H A Dsparx5_pcb_common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
14 enable-method = "spin-table";
15 cpu-release-addr = /bits/ 64 <0>;
19 enable-method = "spin-table";
20 cpu-release-addr = /bits/ 64 <0>;
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/bcm4908/
H A Dbcm4908.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/phy/phy.h>
6 #include <dt-bindings/soc/bcm-pmb.h>
8 /dts-v1/;
11 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
21 stdout-path = "serial0:115200n8";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/axiado/
H A Dax3000.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 /memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */
14 interrupt-parent = <&gic500>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <2>;
[all …]

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