1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5<import file="freedreno_copyright.xml"/> 6<import file="adreno/adreno_common.xml"/> 7<import file="adreno/adreno_pm4.xml"/> 8<import file="adreno/a6xx_enums.xml"/> 9<import file="adreno/a7xx_enums.xml"/> 10<import file="adreno/a8xx_enums.xml"/> 11<import file="adreno/a6xx_perfcntrs.xml"/> 12<import file="adreno/a7xx_perfcntrs.xml"/> 13<import file="adreno/a8xx_perfcntrs.xml"/> 14<import file="adreno/a6xx_descriptors.xml"/> 15<import file="adreno/a8xx_descriptors.xml"/> 16 17<!-- 18Each register that is actually being used by driver should have "usage" defined, 19currently there are following usages: 20- "init" - registers written (in ib1 generally, or ambles) to get the 21 GPU into a known state. 22- "cmd" - the register is used outside of renderpass and blits, 23 roughly corresponds to registers used in ib1 for Freedreno 24- "draw" - used by 3d draw cmds 25- "compute" - used by compute cmds 26- "blit" - used by CP_BLIT cmds 27- "resolve" - used by CCU_RESOLVE (resolve/unresolve/clear) events 28 29It is expected that register with "cmd" and "init" usage may be written into only at 30the start of the command buffer (ib1), while other usages indicates that register 31is either overwritten by renderpass/blit (ib2) or not used if not overwritten 32by a particular renderpass/blit. 33--> 34 35<domain name="A6XX" width="32" prefix="variant" varset="chip"> 36 <bitset name="A6XX_RBBM_INT_0_MASK" inline="no" varset="chip"> 37 <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/> 38 <bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/> 39 <bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/> 40 <bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/> 41 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/> 42 <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/> 43 <bitfield name="CP_SW" pos="8" type="boolean"/> 44 <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/> 45 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/> 46 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/> 47 <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/> 48 <bitfield name="CP_IB2" pos="13" type="boolean"/> 49 <bitfield name="CP_IB1" pos="14" type="boolean"/> 50 <bitfield name="CP_RB" pos="15" type="boolean" variants="A6XX"/> 51 <!-- Same as above but different name??: --> 52 <bitfield name="PM4CPINTERRUPT" pos="15" type="boolean" variants="A7XX-"/> 53 <bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean" variants="A7XX-"/> 54 <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/> 55 <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/> 56 <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/> 57 <bitfield name="CP_CACHE_FLUSH_TS_LPAC" pos="21" type="boolean" variants="A7XX-"/> 58 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/> 59 <bitfield name="RBBM_HANG_DETECT" pos="23" type="boolean"/> 60 <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/> 61 <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/> 62 <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/> 63 <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/> 64 <bitfield name="TSBWRITEERROR" pos="28" type="boolean" variants="A7XX-"/> 65 <bitfield name="SWFUSEVIOLATION" pos="29" type="boolean" variants="A7XX-"/> 66 <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/> 67 <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/> 68 </bitset> 69 70 <!-- 71 Note the _LPAC bits probably *actually* first appeared in a660, but the 72 _BV bits are new in a7xx 73 --> 74 <bitset name="A6XX_CP_INT" varset="chip"> 75 <bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/> 76 <bitfield name="CP_UCODE_ERROR" pos="1" type="boolean"/> 77 <bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/> 78 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/> 79 <bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/> 80 <bitfield name="CP_VSD_PARITY_ERROR" pos="6" type="boolean"/> 81 <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7" type="boolean"/> 82 <bitfield name="CP_OPCODE_ERROR_LPAC" pos="8" type="boolean" variants="A7XX-"/> 83 <bitfield name="CP_UCODE_ERROR_LPAC" pos="9" type="boolean" variants="A7XX-"/> 84 <bitfield name="CP_HW_FAULT_ERROR_LPAC" pos="10" type="boolean" variants="A7XX-"/> 85 <bitfield name="CP_REGISTER_PROTECTION_ERROR_LPAC" pos="11" type="boolean" variants="A7XX-"/> 86 <bitfield name="CP_ILLEGAL_INSTR_ERROR_LPAC" pos="12" type="boolean" variants="A7XX-"/> 87 <bitfield name="CP_OPCODE_ERROR_BV" pos="13" type="boolean" variants="A7XX-"/> 88 <bitfield name="CP_UCODE_ERROR_BV" pos="14" type="boolean" variants="A7XX-"/> 89 <bitfield name="CP_HW_FAULT_ERROR_BV" pos="15" type="boolean" variants="A7XX-"/> 90 <bitfield name="CP_REGISTER_PROTECTION_ERROR_BV" pos="16" type="boolean" variants="A7XX-"/> 91 <bitfield name="CP_ILLEGAL_INSTR_ERROR_BV" pos="17" type="boolean" variants="A7XX-"/> 92 </bitset> 93 94 <bitset name="A8XX_CP_GLOBAL_INT_MASK" inline="no" varset="chip"> 95 <bitfield name="HWFAULTBR" pos="0" type="boolean"/> 96 <bitfield name="HWFAULTBV" pos="1" type="boolean"/> 97 <bitfield name="HWFAULTLPAC" pos="2" type="boolean"/> 98 <bitfield name="HWFAULTAQE0" pos="3" type="boolean"/> 99 <bitfield name="HWFAULTAQE1" pos="4" type="boolean"/> 100 <bitfield name="HWFAULTDDEBR" pos="5" type="boolean"/> 101 <bitfield name="HWFAULTDDEBV" pos="6" type="boolean"/> 102 <bitfield name="SWFAULTBR" pos="16" type="boolean"/> 103 <bitfield name="SWFAULTBV" pos="17" type="boolean"/> 104 <bitfield name="SWFAULTLPAC" pos="18" type="boolean"/> 105 <bitfield name="SWFAULTAQE0" pos="19" type="boolean"/> 106 <bitfield name="SWFAULTAQE1" pos="20" type="boolean"/> 107 <bitfield name="SWFAULTDDEBR" pos="21" type="boolean"/> 108 <bitfield name="SWFAULTDDEBV" pos="22" type="boolean"/> 109 </bitset> 110 111 <bitset name="A8XX_CP_INTERRUPT_STATUS_MASK_PIPE" inline="no" varset="chip"> 112 <bitfield name="CSFRBWRAP" pos="0" type="boolean"/> 113 <bitfield name="CSFIB1WRAP" pos="1" type="boolean"/> 114 <bitfield name="CSFIB2WRAP" pos="2" type="boolean"/> 115 <bitfield name="CSFIB3WRAP" pos="3" type="boolean"/> 116 <bitfield name="CSFSDSWRAP" pos="4" type="boolean"/> 117 <bitfield name="CSFMRBWRAP" pos="5" type="boolean"/> 118 <bitfield name="CSFVSDWRAP" pos="6" type="boolean"/> 119 <bitfield name="OPCODEERROR" pos="8" type="boolean"/> 120 <bitfield name="VSDPARITYERROR" pos="9" type="boolean"/> 121 <bitfield name="REGISTERPROTECTIONERROR" pos="10" type="boolean"/> 122 <bitfield name="ILLEGALINSTRUCTION" pos="11" type="boolean"/> 123 <bitfield name="SMMUFAULT" pos="12" type="boolean"/> 124 <bitfield name="VBIFRESPCLIENT" pos="13" type="boolean"/> 125 <bitfield name="VBIFRESPTYPE" pos="19" type="boolean"/> 126 <bitfield name="VBIFRESPREAD" pos="21" type="boolean"/> 127 <bitfield name="VBIFRESP" pos="22" type="boolean"/> 128 <bitfield name="RTWROVF" pos="23" type="boolean"/> 129 <bitfield name="LRZRTWROVF" pos="24" type="boolean"/> 130 <bitfield name="LRZRTREFCNTOVF" pos="25" type="boolean"/> 131 <bitfield name="LRZRTCLRRESMISS" pos="26" type="boolean"/> 132 </bitset> 133 134 <bitset name="A8XX_CP_HW_FAULT_STATUS_MASK_PIPE" inline="no" varset="chip"> 135 <bitfield name="CSFRBFAULT" pos="0" type="boolean"/> 136 <bitfield name="CSFIB1FAULT" pos="1" type="boolean"/> 137 <bitfield name="CSFIB2FAULT" pos="2" type="boolean"/> 138 <bitfield name="CSFIB3FAULT" pos="3" type="boolean"/> 139 <bitfield name="CSFSDSFAULT" pos="4" type="boolean"/> 140 <bitfield name="CSFMRBFAULT" pos="5" type="boolean"/> 141 <bitfield name="CSFVSDFAULT" pos="6" type="boolean"/> 142 <bitfield name="SQEREADBURSTOVF" pos="8" type="boolean"/> 143 <bitfield name="EVENTENGINEOVF" pos="9" type="boolean"/> 144 <bitfield name="UCODEERROR" pos="10" type="boolean"/> 145 </bitset> 146 147 <reg64 offset="0x0800" name="CP_RB_BASE"/> 148 <reg32 offset="0x0802" name="CP_RB_CNTL"/> 149 <reg32 offset="0x0803" name="CP_RB_RPTR_WR" variants="A7XX-"/> 150 <reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/> 151 <reg32 offset="0x0806" name="CP_RB_RPTR"/> 152 <reg32 offset="0x0807" name="CP_RB_WPTR"/> 153 <reg32 offset="0x0808" name="CP_RB_RPTR_ADDR_BV" variants="A8XX-"/> 154 <reg32 offset="0x080a" name="CP_RB_RPTR_BV" variants="A8XX-"/> 155 <reg64 offset="0x080b" name="CP_RB_BASE_LPAC" variants="A8XX-"/> 156 <reg32 offset="0x080d" name="CP_RB_CNTL_LPAC" variants="A8XX-"/> 157 <reg32 offset="0x080e" name="CP_RB_RPTR_WR_LPAC" variants="A8XX-"/> 158 <reg64 offset="0x080f" name="CP_RB_RPTR_ADDR_LPAC" variants="A8XX-"/> 159 <reg32 offset="0x0811" name="CP_RB_RPTR_LPAC" variants="A8XX-"/> 160 <reg32 offset="0x0812" name="CP_RB_WPTR_LPAC" variants="A8XX-"/> 161 <reg32 offset="0x0814" name="CP_SMMU_STREAM_ID_LPAC" variants="A8XX-"/> 162 <reg32 offset="0x0808" name="CP_SQE_CNTL" variants="A6XX-A7XX"/> 163 <reg32 offset="0x0815" name="CP_SQE_CNTL" variants="A8XX-"/> 164 <reg64 offset="0x0816" name="CP_SQE_INSTR_BASE" variants="A8XX-"/> 165 <reg64 offset="0x0818" name="CP_AQE_INSTR_BASE_0" variants="A8XX-"/> 166 <reg64 offset="0x081a" name="CP_AQE_INSTR_BASE_1" variants="A8XX-"/> 167 <reg32 offset="0x0812" name="CP_CP2GMU_STATUS" variants="A6XX-A7XX"> 168 <!-- Note, layout defined by microcode --> 169 <bitfield name="IFPC" pos="0" type="boolean"/> 170 </reg32> 171 <reg32 offset="0x0822" name="CP_CP2GMU_STATUS" variants="A8XX-"> 172 <bitfield name="IFPC" pos="0" type="boolean"/> 173 </reg32> 174 <reg32 offset="0x0821" name="CP_HW_FAULT" variants="A6XX-A7XX"/> 175 <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT" variants="A6XX-A7XX"/> 176 177 <bitset name="a6xx_cp_protect_status" inline="yes"> 178 <bitfield name="ADDR" low="0" high="17"/> 179 <bitfield name="READ" pos="20" type="boolean"/> 180 <bitfield name="CP_HALTED" pos="21" type="boolean"/> 181 <bitfield name="ACCESS_VIOLATION" pos="22" type="boolean"/> 182 </bitset> 183 184 <reg32 offset="0x0824" name="CP_PROTECT_STATUS" type="a6xx_cp_protect_status" variants="A6XX-A7XX"/> 185 <reg32 offset="0x084f" name="CP_PROTECT_STATUS_PIPE" type="a6xx_cp_protect_status" variants="A8XX-"/> 186 <reg32 offset="0x0825" name="CP_STATUS_1" variants="A6XX-A7XX"/> 187 188 <reg32 offset="0x0825" name="CP_SEMAPHORE_REG_0" variants="A8XX-"/> 189 <array offset="0x082a" name="CP_SCRATCH_GLOBAL" stride="1" length="4" variants="A8XX-"> 190 <reg32 offset="0x0" name="REG"/> 191 </array> 192 <array offset="0x0830" name="CP_SCRATCH_PIPE" stride="1" length="5" variants="A8XX-"> 193 <reg32 offset="0x0" name="REG"/> 194 </array> 195 196 <reg32 offset="0x0840" name="CP_RL_ERROR_DETAILS_0" variants="A8XX-"/> 197 <reg32 offset="0x0841" name="CP_RL_ERROR_DETAILS_1" variants="A8XX-"/> 198 199 <reg64 offset="0x0830" name="CP_SQE_INSTR_BASE" variants="A6XX-A7XX"/> 200 <reg32 offset="0x0840" name="CP_MISC_CNTL" variants="A6XX-A7XX"/> 201 <reg32 offset="0x084c" name="CP_MISC_CNTL" variants="A8XX-"/> 202 203 <reg32 offset="0x08b0" name="CP_SQE_ICACHE_CNTL_PIPE" variants="A8XX-"/> 204 <reg32 offset="0x08b1" name="CP_SQE_DCACHE_CNTL_PIPE" variants="A8XX-"/> 205 <reg32 offset="0x08b3" name="CP_HW_FAULT_STATUS_PIPE" variants="A8XX-"/> 206 <reg32 offset="0x08b4" name="CP_HW_FAULT_STATUS_MASK_PIPE" variants="A8XX-"/> 207 <reg32 offset="0x08b5" name="CP_INTERRUPT_STATUS_GLOBAL" type="A8XX_CP_GLOBAL_INT_MASK" variants="A8XX-"/> 208 <reg32 offset="0x08b6" name="CP_INTERRUPT_STATUS_MASK_GLOBAL" type="A8XX_CP_GLOBAL_INT_MASK" variants="A8XX-"/> 209 <reg32 offset="0x08b7" name="CP_INTERRUPT_STATUS_PIPE" type="A8XX_CP_INTERRUPT_STATUS_MASK_PIPE" variants="A8XX-"/> 210 <reg32 offset="0x08b8" name="CP_INTERRUPT_STATUS_MASK_PIPE" variants="A8XX-"/> 211 <reg32 offset="0x08b9" name="CP_PIPE_STATUS_PIPE" variants="A8XX-"/> 212 <reg32 offset="0x08ba" name="CP_GPU_BATCH_ID_PIPE" variants="A8XX-"/> 213 <reg32 offset="0x08bb" name="CP_SQE_STATUS_PIPE" variants="A8XX-"/> 214 215 <bitset name="a6xx_cp_apriv_cntl" inline="yes"> 216 <!-- Crashdumper writes --> 217 <bitfield pos="6" name="CDWRITE" type="boolean"/> 218 <!-- Crashdumper reads --> 219 <bitfield pos="5" name="CDREAD" type="boolean"/> 220 <!-- CP Scratch reg copy to mem --> 221 <bitfield pos="4" name="SCRATCHWT" type="boolean"/> 222 <!-- RPTR shadow writes --> 223 <bitfield pos="3" name="RBRPWB" type="boolean"/> 224 <!-- Memory accesses from PM4 packets in the ringbuffer --> 225 <bitfield pos="2" name="RBPRIVLEVEL" type="boolean"/> 226 <!-- Ringbuffer reads --> 227 <bitfield pos="1" name="RBFETCH" type="boolean"/> 228 <!-- Instruction cache fetches --> 229 <bitfield pos="0" name="ICACHE" type="boolean"/> 230 </bitset> 231 232 <reg32 offset="0x0844" name="CP_APRIV_CNTL" type="a6xx_cp_apriv_cntl" variants="A6XX-A7XX"/> 233 <reg32 offset="0x084d" name="CP_APRIV_CNTL_PIPE" type="a6xx_cp_apriv_cntl" variants="A8XX-"/> 234 235 <!-- Preemptions taking longer than this threshold increment PERF_CP_LONG_PREEMPTIONS: --> 236 <reg32 offset="0x08c0" name="CP_PREEMPT_THRESHOLD" variants="A6XX-A7XX"/> 237 <reg32 offset="0x08ec" name="CP_PREEMPT_THRESHOLD" variants="A8XX-"/> 238 <!-- all the threshold values seem to be in units of quad-dwords: --> 239 <reg32 offset="0x08c1" name="CP_ROQ_THRESHOLDS_1" variants="A6XX"> 240 <doc> 241 b0..7 identifies where MRB data starts (and RB data ends) 242 b8.15 identifies where VSD data starts (and MRB data ends) 243 b16..23 identifies where IB1 data starts (and RB data ends) 244 b24..31 identifies where IB2 data starts (and IB1 data ends) 245 </doc> 246 <bitfield name="MRB_START" low="0" high="7" shr="2"/> 247 <bitfield name="VSD_START" low="8" high="15" shr="2"/> 248 <bitfield name="IB1_START" low="16" high="23" shr="2"/> 249 <bitfield name="IB2_START" low="24" high="31" shr="2"/> 250 </reg32> 251 <reg32 offset="0x08c2" name="CP_ROQ_THRESHOLDS_2" variants="A6XX"> 252 <doc> 253 low bits identify where CP_SET_DRAW_STATE stateobj 254 processing starts (and IB2 data ends). I'm guessing 255 b8 is part of this since (from downstream kgsl): 256 257 /* ROQ sizes are twice as big on a640/a680 than on a630 */ 258 if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) { 259 kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 260 kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C); 261 } ... 262 </doc> 263 <bitfield name="SDS_START" low="0" high="8" shr="2"/> 264 <!-- total ROQ size: --> 265 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/> 266 </reg32> 267 <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE" variants="A6XX"/> 268 <reg32 offset="0x0841" name="CP_CHICKEN_DBG" variants="A6XX-A7XX"/> 269 <reg32 offset="0x08b2" name="CP_CHICKEN_DBG_PIPE" variants="A8XX-"/> 270 <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 271 <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL" variants="A6XX-A7XX"/> 272 <reg32 offset="0x084b" name="CP_DBG_ECO_CNTL" variants="A8XX-"/> 273 274 <bitset name="a6xx_cp_protect_cntl" inline="yes"> 275 <bitfield pos="3" name="LAST_SPAN_INF_RANGE" type="boolean"/> 276 <bitfield pos="1" name="ACCESS_FAULT_ON_VIOL_EN" type="boolean"/> 277 <bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/> 278 </bitset> 279 280 <reg32 offset="0x084f" name="CP_PROTECT_CNTL" type="a6xx_cp_protect_cntl" variants="A6XX-A7XX"/> 281 <bitset name="a8xx_cp_protect_cntl" inline="yes"> 282 <bitfield name="HALT_SQE_RANGE" low="16" high="31"/> 283 <bitfield name="LAST_SPAN_INF_RANGE" pos="3" type="boolean"/> 284 <bitfield name="ACCESS_FAULT_ON_VIOL_EN" pos="1" type="boolean"/> 285 <bitfield name="ACCESS_PROT_EN" pos="0" type="boolean"/> 286 </bitset> 287 288 <reg32 offset="0x084e" name="CP_PROTECT_CNTL_PIPE" type="a8xx_cp_protect_cntl" variants="A8XX-"/> 289 290 <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8" variants="A6XX-A7XX"> 291 <reg32 offset="0x0" name="REG" type="uint"/> 292 </array> 293 <array offset="0x0850" name="CP_PROTECT" stride="1" length="32" variants="A6XX-A7XX"> 294 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> 295 </array> 296 <array offset="0x0850" name="CP_PROTECT_GLOBAL" stride="1" length="64" variants="A8XX-"> 297 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> 298 </array> 299 <array offset="0x08a0" name="CP_PROTECT_PIPE" stride="1" length="16" variants="A8XX-"> 300 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> 301 </array> 302 303 <bitset name="a6xx_cp_context_switch_cntl" inline="yes"> 304 <bitfield name="STOP" pos="0" type="boolean"/> 305 <bitfield name="LEVEL" low="6" high="7"/> 306 <bitfield name="USES_GMEM" pos="8" type="boolean"/> 307 <bitfield name="SKIP_SAVE_RESTORE" pos="9" type="boolean"/> 308 </bitset> 309 310 <reg32 offset="0x08a0" name="CP_CONTEXT_SWITCH_CNTL" type="a6xx_cp_context_switch_cntl" variants="A6XX-A7XX"/> 311 <reg32 offset="0x08c0" name="CP_CONTEXT_SWITCH_CNTL" type="a6xx_cp_context_switch_cntl" variants="A8XX-"/> 312 313 <reg64 offset="0x08a1" name="CP_CONTEXT_SWITCH_SMMU_INFO" variants="A6XX-A7XX"/> 314 <reg64 offset="0x08a3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR" variants="A6XX-A7XX"/> 315 <reg64 offset="0x08a5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR" variants="A6XX-A7XX"/> 316 <reg64 offset="0x08a7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR" variants="A6XX-A7XX"/> 317 <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX"/> 318 319 <reg64 offset="0x08c1" name="CP_CONTEXT_SWITCH_SMMU_INFO" variants="A8XX-"/> 320 <reg64 offset="0x08c3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR" variants="A8XX-"/> 321 <reg64 offset="0x08c5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR" variants="A8XX-"/> 322 <reg64 offset="0x08c7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR" variants="A8XX-"/> 323 <reg32 offset="0x08cb" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A8XX-"/> 324 325 <array offset="0x08d0" name="CP_PERFCTR_CP_SEL" stride="1" length="14" variants="A6XX-A7XX"/> 326 <array offset="0x08d0" name="CP_PERFCTR_CP_SEL" stride="1" length="21" variants="A8XX-"/> 327 <array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX"/> 328 <reg64 offset="0x0900" name="CP_CRASH_DUMP_SCRIPT_BASE" variants="A6XX-A7XX"/> 329 <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL" variants="A6XX-A7XX"/> 330 <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS" variants="A6XX-A7XX"/> 331 <reg64 offset="0x0842" name="CP_CRASH_DUMP_SCRIPT_BASE" variants="A8XX-"/> 332 <reg32 offset="0x0844" name="CP_CRASH_DUMP_CNTL" variants="A8XX-"/> 333 <reg32 offset="0x0845" name="CP_CRASH_DUMP_STATUS" variants="A8XX-"/> 334 <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR" variants="A6XX-A7XX"/> 335 <reg32 offset="0x0909" name="CP_SQE_STAT_DATA" variants="A6XX-A7XX"/> 336 <reg32 offset="0x090a" name="CP_DRAW_STATE_ADDR" variants="A6XX-A7XX"/> 337 <reg32 offset="0x090b" name="CP_DRAW_STATE_DATA" variants="A6XX-A7XX"/> 338 <reg32 offset="0x090c" name="CP_ROQ_DBG_ADDR" variants="A6XX-A7XX"/> 339 <reg32 offset="0x090d" name="CP_ROQ_DBG_DATA" variants="A6XX-A7XX"/> 340 <reg32 offset="0x090e" name="CP_MEM_POOL_DBG_ADDR" variants="A6XX-A7XX"/> 341 <reg32 offset="0x090f" name="CP_MEM_POOL_DBG_DATA" variants="A6XX-A7XX"/> 342 <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR" variants="A6XX-A7XX"/> 343 <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA" variants="A6XX-A7XX"/> 344 345 <reg32 offset="0x08f0" name="CP_SQE_STAT_ADDR_PIPE" variants="A8XX-"/> 346 <reg32 offset="0x08f1" name="CP_SQE_STAT_DATA_PIPE" variants="A8XX-"/> 347 <reg32 offset="0x08f2" name="CP_DRAW_STATE_ADDR_PIPE" variants="A8XX-"/> 348 <reg32 offset="0x08f3" name="CP_DRAW_STATE_DATA_PIPE" variants="A8XX-"/> 349 <reg32 offset="0x08f4" name="CP_ROQ_DBG_ADDR_PIPE" variants="A8XX-"/> 350 <reg32 offset="0x08f5" name="CP_ROQ_DBG_DATA_PIPE" variants="A8XX-"/> 351 <reg32 offset="0x08f6" name="CP_MEM_POOL_DBG_ADDR_PIPE" variants="A8XX-"/> 352 <reg32 offset="0x08f7" name="CP_MEM_POOL_DBG_DATA_PIPE" variants="A8XX-"/> 353 <reg32 offset="0x08f8" name="CP_SQE_UCODE_DBG_ADDR_PIPE" variants="A8XX-"/> 354 <reg32 offset="0x08f9" name="CP_SQE_UCODE_DBG_DATA_PIPE" variants="A8XX-"/> 355 <reg32 offset="0x08fa" name="CP_RESOURCE_TABLE_DBG_ADDR_BV" variants="A8XX-"/> 356 <reg32 offset="0x08fb" name="CP_RESOURCE_TABLE_DBG_DATA_BV" variants="A8XX-"/> 357 <reg32 offset="0x08fc" name="CP_FIFO_DBG_ADDR_LPAC" variants="A8XX-"/> 358 <reg32 offset="0x08fd" name="CP_FIFO_DBG_DATA_LPAC" variants="A8XX-"/> 359 <reg32 offset="0x08fe" name="CP_FIFO_DBG_ADDR_DDE_PIPE" variants="A8XX-"/> 360 <reg32 offset="0x08ff" name="CP_FIFO_DBG_DATA_DDE_PIPE" variants="A8XX-"/> 361 362 <reg32 offset="0x0b00" name="CP_SLICE_MEM_POOL_DBG_ADDR_PIPE" variants="A8XX-"/> 363 <reg32 offset="0x0b01" name="CP_SLICE_MEM_POOL_DBG_DATA_PIPE" variants="A8XX-"/> 364 <reg32 offset="0x0b93" name="CP_SLICE_CHICKEN_DBG_PIPE" variants="A8XX-"/> 365 366 <reg64 offset="0x0928" name="CP_IB1_BASE" variants="A6XX-A7XX"/> 367 <reg32 offset="0x092a" name="CP_IB1_REM_SIZE" variants="A6XX-A7XX"/> 368 <reg64 offset="0x092b" name="CP_IB2_BASE" variants="A6XX-A7XX"/> 369 <reg32 offset="0x092d" name="CP_IB2_REM_SIZE" variants="A6XX-A7XX"/> 370 <!-- SDS == CP_SET_DRAW_STATE: --> 371 <reg64 offset="0x092e" name="CP_SDS_BASE" variants="A6XX-A7XX"/> 372 <reg32 offset="0x0930" name="CP_SDS_REM_SIZE" variants="A6XX-A7XX"/> 373 <!-- MRB == MEM_READ_ADDR/$addr in SQE firmware --> 374 <reg64 offset="0x0931" name="CP_MRB_BASE" variants="A6XX-A7XX"/> 375 <reg32 offset="0x0933" name="CP_MRB_REM_SIZE" variants="A6XX-A7XX"/> 376 <!-- 377 VSD == Visibility Stream Decode 378 This is used by CP to read the draw stream and skip empty draws 379 --> 380 <reg64 offset="0x0934" name="CP_VSD_BASE" variants="A6XX-A7XX"/> 381 382 <reg64 offset="0x0900" name="CP_IB1_BASE" variants="A8XX-"/> 383 <reg32 offset="0x0902" name="CP_IB1_REM_SIZE" variants="A8XX-"/> 384 <reg32 offset="0x0903" name="CP_IB1_INIT_SIZE" variants="A8XX-"/> 385 <reg64 offset="0x0904" name="CP_IB2_BASE" variants="A8XX-"/> 386 <reg32 offset="0x0906" name="CP_IB2_REM_SIZE" variants="A8XX-"/> 387 <reg32 offset="0x0907" name="CP_IB2_INIT_SIZE" variants="A8XX-"/> 388 <reg64 offset="0x0908" name="CP_IB3_BASE" variants="A8XX-"/> 389 <reg32 offset="0x090a" name="CP_IB3_REM_SIZE" variants="A8XX-"/> 390 <reg32 offset="0x090b" name="CP_IB3_INIT_SIZE" variants="A8XX-"/> 391 <reg64 offset="0x090c" name="CP_SDS_BASE" variants="A8XX-"/> 392 <reg32 offset="0x090e" name="CP_SDS_REM_SIZE" variants="A8XX-"/> 393 <reg32 offset="0x090f" name="CP_SDS_INIT_SIZE" variants="A8XX-"/> 394 <reg64 offset="0x0910" name="CP_MRB_BASE" variants="A8XX-"/> 395 <reg32 offset="0x0912" name="CP_MRB_REM_SIZE" variants="A8XX-"/> 396 <reg32 offset="0x0913" name="CP_MRB_INIT_SIZE" variants="A8XX-"/> 397 <reg64 offset="0x0914" name="CP_VSD_BASE" variants="A8XX-"/> 398 <reg32 offset="0x0916" name="CP_VSD_REM_SIZE" variants="A8XX-"/> 399 <reg32 offset="0x0917" name="CP_VSD_INIT_SIZE" variants="A8XX-"/> 400 401 <bitset name="a6xx_roq_status" inline="yes"> 402 <bitfield name="RPTR" low="0" high="9"/> 403 <bitfield name="WPTR" low="16" high="25"/> 404 </bitset> 405 <reg32 offset="0x0939" name="CP_ROQ_RB_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 406 <reg32 offset="0x093a" name="CP_ROQ_IB1_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 407 <reg32 offset="0x093b" name="CP_ROQ_IB2_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 408 <reg32 offset="0x093c" name="CP_ROQ_SDS_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 409 <reg32 offset="0x093d" name="CP_ROQ_MRB_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 410 <reg32 offset="0x093e" name="CP_ROQ_VSD_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 411 412 <reg32 offset="0x0920" name="CP_ROQ_RB_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 413 <reg32 offset="0x0921" name="CP_ROQ_IB1_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 414 <reg32 offset="0x0922" name="CP_ROQ_IB2_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 415 <reg32 offset="0x0923" name="CP_ROQ_IB3_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 416 <reg32 offset="0x0924" name="CP_ROQ_SDS_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 417 <reg32 offset="0x0925" name="CP_ROQ_MRB_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 418 <reg32 offset="0x0926" name="CP_ROQ_VSD_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 419 420 <reg32 offset="0x0943" name="CP_IB1_INIT_SIZE" variants="A6XX-A7XX"/> 421 <reg32 offset="0x0944" name="CP_IB2_INIT_SIZE" variants="A6XX-A7XX"/> 422 <reg32 offset="0x0945" name="CP_SDS_INIT_SIZE" variants="A6XX-A7XX"/> 423 <reg32 offset="0x0946" name="CP_MRB_INIT_SIZE" variants="A6XX-A7XX"/> 424 <reg32 offset="0x0947" name="CP_VSD_INIT_SIZE" variants="A6XX-A7XX"/> 425 426 <bitset name="a6xx_cp_roq_avail" inline="yes"> 427 <doc>number of remaining dwords incl current dword being consumed?</doc> 428 <bitfield name="REM" low="16" high="31"/> 429 </bitset> 430 431 <reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 432 <reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 433 <reg32 offset="0x094a" name="CP_ROQ_AVAIL_IB2" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 434 <reg32 offset="0x094b" name="CP_ROQ_AVAIL_SDS" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 435 <reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 436 <reg32 offset="0x094d" name="CP_ROQ_AVAIL_VSD" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 437 438 <reg32 offset="0x0918" name="CP_ROQ_AVAIL_RB" type="a6xx_cp_roq_avail" variants="A8XX-"/> 439 <reg32 offset="0x0919" name="CP_ROQ_AVAIL_IB1" type="a6xx_cp_roq_avail" variants="A8XX-"/> 440 <reg32 offset="0x091a" name="CP_ROQ_AVAIL_IB2" type="a6xx_cp_roq_avail" variants="A8XX-"/> 441 <reg32 offset="0x091b" name="CP_ROQ_AVAIL_IB3" type="a6xx_cp_roq_avail" variants="A8XX-"/> 442 <reg32 offset="0x091c" name="CP_ROQ_AVAIL_SDS" type="a6xx_cp_roq_avail" variants="A8XX-"/> 443 <reg32 offset="0x091d" name="CP_ROQ_AVAIL_MRB" type="a6xx_cp_roq_avail" variants="A8XX-"/> 444 <reg32 offset="0x091e" name="CP_ROQ_AVAIL_VSD" type="a6xx_cp_roq_avail" variants="A8XX-"/> 445 446 <bitset name="a7xx_aperture_cntl" inline="yes"> 447 <bitfield name="PIPE" low="12" high="13" type="adreno_pipe"/> 448 <bitfield name="CLUSTER" low="8" high="10" type="a7xx_cluster"/> 449 <bitfield name="CONTEXT" low="4" high="5"/> 450 </bitset> 451 <reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER" variants="A6XX-A7XX"/> 452 <reg64 offset="0x0982" name="CP_ALWAYS_ON_CONTEXT" variants="A6XX-A7XX"/> 453 <reg64 offset="0x08e7" name="CP_ALWAYS_ON_COUNTER" variants="A8XX-"/> 454 <reg64 offset="0x08e9" name="CP_ALWAYS_ON_CONTEXT" variants="A8XX-"/> 455 <reg32 offset="0x098d" name="CP_AHB_CNTL" variants="A6XX-A7XX"/> 456 <reg32 offset="0x0838" name="CP_AHB_CNTL" variants="A8XX-"/> 457 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/> 458 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX"/> 459 <reg32 offset="0x0A01" name="CP_APERTURE_CNTL_SQE" variants="A6XX"/> 460 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/> 461 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX"/> 462 463 <array offset="0x0a9c" name="CP_RESERVED_REG" stride="1" length="4" variants="A7XX"/> 464 <array offset="0x0958" name="CP_RESERVED_REG" stride="1" length="4" variants="A8XX-"/> 465 466 <bitset name="a8xx_aperture_cntl" inline="yes"> 467 <bitfield name="CONTEXTID3D" low="4" high="5"/> 468 <bitfield name="CLUSTERID" low="8" high="11"/> 469 <bitfield name="PIPEID" low="12" high="15"/> 470 <bitfield name="SLICEID" low="16" high="18"/> 471 <bitfield name="USESLICEID" pos="23" type="boolean"/> 472 </bitset> 473 474 <reg32 offset="0x081c" name="CP_APERTURE_CNTL_HOST" type="a8xx_aperture_cntl" variants="A8XX-"/> 475 <reg32 offset="0x081d" name="CP_APERTURE_CNTL_GMU" type="a8xx_aperture_cntl" variants="A8XX-"/> 476 <reg32 offset="0x081e" name="CP_APERTURE_CNTL_CD" type="a8xx_aperture_cntl" variants="A8XX-"/> 477 478 <reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX"/> 479 <reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX"/> 480 <reg32 offset="0x0a66" name="CP_BV_RB_RPTR" variants="A7XX"/> 481 <reg64 offset="0x0a6d" name="CP_BV_IB1_BASE" variants="A7XX"/> 482 <reg32 offset="0x0a70" name="CP_BV_IB1_REM_SIZE" variants="A7XX"/> 483 <reg64 offset="0x0a71" name="CP_BV_IB2_BASE" variants="A7XX"/> 484 <reg32 offset="0x0a74" name="CP_BV_IB2_REM_SIZE" variants="A7XX"/> 485 <reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX"/> 486 <reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX"/> 487 <reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX"/> 488 <reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX"/> 489 <reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX"/> 490 <reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX"/> 491 <reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX"/> 492 <reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX"/> 493 494 <reg32 offset="0x0a8f" name="CP_BV_ROQ_AVAIL_RB" variants="A7XX"> 495 <doc>number of remaining dwords incl current dword being consumed?</doc> 496 <bitfield name="REM" low="16" high="31"/> 497 </reg32> 498 <reg32 offset="0x0a90" name="CP_BV_ROQ_AVAIL_IB1" variants="A7XX"> 499 <doc>number of remaining dwords incl current dword being consumed?</doc> 500 <bitfield name="REM" low="16" high="31"/> 501 </reg32> 502 <reg32 offset="0x0a91" name="CP_BV_ROQ_AVAIL_IB2" variants="A7XX"> 503 <doc>number of remaining dwords incl current dword being consumed?</doc> 504 <bitfield name="REM" low="16" high="31"/> 505 </reg32> 506 507 <reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX"/> 508 <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX"/> 509 <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX"/> 510 511 <reg32 offset="0x0a9a" name="CP_RESOURCE_TABLE_DBG_ADDR" variants="A7XX"/> 512 <reg32 offset="0x0a9b" name="CP_RESOURCE_TABLE_DBG_DATA" variants="A7XX"/> 513 <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX"/> 514 <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX"/> 515 516 <reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX"/> 517 <reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX"/> 518 <reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX"/> 519 <reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX"/> 520 <reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX"/> 521 <reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX"/> 522 <reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX"/> 523 524 <reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX"/> 525 <reg32 offset="0x0b34" name="CP_LPAC_PROG_FIFO_SIZE" variants="A7XX"/> 526 <reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX"/> 527 <reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX"/> 528 <reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX"/> 529 <reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL" variants="A6XX-A7XX"/> 530 <reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE" variants="A6XX-A7XX"/> 531 532 <reg64 offset="0x0b70" name="CP_AQE_INSTR_BASE_0" variants="A7XX"/> 533 <reg64 offset="0x0b72" name="CP_AQE_INSTR_BASE_1" variants="A7XX"/> 534 <reg32 offset="0x0b78" name="CP_AQE_APRIV_CNTL" variants="A7XX"/> 535 536 <reg32 offset="0x0ba8" name="CP_AQE_ROQ_DBG_ADDR_0" variants="A7XX"/> 537 <reg32 offset="0x0ba9" name="CP_AQE_ROQ_DBG_ADDR_1" variants="A7XX"/> 538 <reg32 offset="0x0bac" name="CP_AQE_ROQ_DBG_DATA_0" variants="A7XX"/> 539 <reg32 offset="0x0bad" name="CP_AQE_ROQ_DBG_DATA_1" variants="A7XX"/> 540 <reg32 offset="0x0bb0" name="CP_AQE_UCODE_DBG_ADDR_0" variants="A7XX"/> 541 <reg32 offset="0x0bb1" name="CP_AQE_UCODE_DBG_ADDR_1" variants="A7XX"/> 542 <reg32 offset="0x0bb4" name="CP_AQE_UCODE_DBG_DATA_0" variants="A7XX"/> 543 <reg32 offset="0x0bb5" name="CP_AQE_UCODE_DBG_DATA_1" variants="A7XX"/> 544 <reg32 offset="0x0bb8" name="CP_AQE_STAT_ADDR_0" variants="A7XX"/> 545 <reg32 offset="0x0bb9" name="CP_AQE_STAT_ADDR_1" variants="A7XX"/> 546 <reg32 offset="0x0bbc" name="CP_AQE_STAT_DATA_0" variants="A7XX"/> 547 <reg32 offset="0x0bbd" name="CP_AQE_STAT_DATA_1" variants="A7XX"/> 548 549 <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 550 <reg32 offset="0x0018" name="RBBM_GPR0_CNTL" variants="A6XX"/> 551 <reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK" variants="A6XX-A7XX"/> 552 <reg32 offset="0x006a" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK" variants="A8XX-"/> 553 <reg32 offset="0x0210" name="RBBM_STATUS" variants="A6XX-A7XX"> 554 <bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/> 555 <bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/> 556 <bitfield pos="21" name="HLSQ_BUSY" type="boolean"/> 557 <bitfield pos="20" name="VSC_BUSY" type="boolean"/> 558 <bitfield pos="19" name="TPL1_BUSY" type="boolean"/> 559 <bitfield pos="18" name="SP_BUSY" type="boolean"/> 560 <bitfield pos="17" name="UCHE_BUSY" type="boolean"/> 561 <bitfield pos="16" name="VPC_BUSY" type="boolean"/> 562 <bitfield pos="15" name="VFD_BUSY" type="boolean"/> 563 <bitfield pos="14" name="TESS_BUSY" type="boolean"/> 564 <bitfield pos="13" name="PC_VSD_BUSY" type="boolean"/> 565 <bitfield pos="12" name="PC_DCALL_BUSY" type="boolean"/> 566 <bitfield pos="11" name="COM_DCOM_BUSY" type="boolean"/> 567 <bitfield pos="10" name="LRZ_BUSY" type="boolean"/> 568 <bitfield pos="9" name="A2D_BUSY" type="boolean"/> 569 <bitfield pos="8" name="CCU_BUSY" type="boolean"/> 570 <bitfield pos="7" name="RB_BUSY" type="boolean"/> 571 <bitfield pos="6" name="RAS_BUSY" type="boolean"/> 572 <bitfield pos="5" name="TSE_BUSY" type="boolean"/> 573 <bitfield pos="4" name="VBIF_BUSY" type="boolean"/> 574 <bitfield pos="3" name="GFX_DBGC_BUSY" type="boolean"/> 575 <bitfield pos="2" name="CP_BUSY" type="boolean"/> 576 <bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/> 577 <bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/> 578 </reg32> 579 <reg32 offset="0x0211" name="RBBM_STATUS1" variants="A6XX-A7XX"/> 580 <reg32 offset="0x0212" name="RBBM_STATUS2" variants="A6XX-A7XX"/> 581 <reg32 offset="0x0213" name="RBBM_STATUS3" variants="A6XX-A7XX"> 582 <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/> 583 </reg32> 584 585 <reg32 offset="0x012" name="RBBM_STATUS" variants="A8XX-"> 586 <bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/> 587 <bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/> 588 <bitfield pos="21" name="SLICE_BUSY_IGN_CP" type="boolean"/> 589 <bitfield pos="20" name="CP_SLICE_BUSY" type="boolean"/> 590 <bitfield pos="19" name="UNSLICE_BUSY_IGN_AHB" type="boolean"/> 591 <bitfield pos="18" name="UNSLICE_BUSY_IGN_AHB_CP" type="boolean"/> 592 <bitfield pos="17" name="CP_SLICE_RL_BUSY" type="boolean"/> 593 <bitfield pos="14" name="UNSLICE_TOP_BUSY" type="boolean"/> 594 <bitfield pos="13" name="UFC_BUSY" type="boolean"/> 595 <bitfield pos="12" name="HLSQ_BUSY" type="boolean"/> 596 <bitfield pos="11" name="VSC_BUSY" type="boolean"/> 597 <bitfield pos="10" name="UCHE_BUSY" type="boolean"/> 598 <bitfield pos="9" name="VPC_BUSY" type="boolean"/> 599 <bitfield pos="8" name="PC_BUSY" type="boolean"/> 600 <bitfield pos="7" name="CMP_BUSY" type="boolean"/> 601 <bitfield pos="6" name="DCMP_BUSY" type="boolean"/> 602 <bitfield pos="5" name="VBIF_GX_BUSY" type="boolean"/> 603 <bitfield pos="4" name="DBGC_PERF_BUSY" type="boolean"/> 604 <bitfield pos="3" name="GFX_DBGC_BUSY" type="boolean"/> 605 <bitfield pos="2" name="CP_BUSY" type="boolean"/> 606 <bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/> 607 <bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/> 608 </reg32> 609 <reg32 offset="0x013" name="RBBM_STATUS1" variants="A8XX-"/> 610 <reg32 offset="0x015" name="RBBM_GFX_STATUS" variants="A8XX-"/> 611 <reg32 offset="0x016" name="RBBM_GFX_STATUS1" variants="A8XX-"/> 612 <reg32 offset="0x018" name="RBBM_LPAC_STATUS" variants="A8XX-"/> 613 <reg32 offset="0x01a" name="RBBM_GFX_BR_STATUS" variants="A8XX-"/> 614 <reg32 offset="0x01c" name="RBBM_GFX_BV_STATUS" variants="A8XX-"/> 615 <reg32 offset="0x01e" name="RBBM_MISC_STATUS" variants="A8XX-"> 616 <bitfield pos="0" name="SMMU_STALLED_ON_FAULT" type="boolean"/> 617 </reg32> 618 619 <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS" variants="A6XX"/> 620 621 <reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX"/> 622 <reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX"/> 623 <reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX"/> 624 <reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX"/> 625 <reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX"/> 626 <reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX"/> 627 628 <reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX"/> 629 <reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX"/> 630 <reg32 offset="0x0071" name="RBBM_SW_FUSE_INT_STATUS" variants="A8XX-"/> 631 <reg32 offset="0x0072" name="RBBM_SW_FUSE_INT_MASK" variants="A8XX-"/> 632 633 <array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/> 634 <array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/> 635 <array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A6XX"/> 636 <array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A6XX"/> 637 <array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A6XX"/> 638 <array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A6XX"/> 639 <array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A6XX"/> 640 <array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A6XX"/> 641 <array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A6XX"/> 642 <array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A6XX"/> 643 <array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A6XX"/> 644 <array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A6XX"/> 645 <array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A6XX"/> 646 <array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A6XX"/> 647 <array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A6XX"/> 648 <array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A6XX"/> 649 650 <array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX"/> 651 <array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX"/> 652 <array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX"/> 653 <array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX"/> 654 <array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX"/> 655 <array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX"/> 656 <array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX"/> 657 <array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX"/> 658 <array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX"/> 659 <array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX"/> 660 <array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX"/> 661 <array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX"/> 662 <array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX"/> 663 <array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX"/> 664 <array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX"/> 665 <array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX"/> 666 <array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX"/> 667 <array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX"/> 668 <array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX"/> 669 <array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX"/> 670 <array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX"/> 671 <array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX"/> 672 <array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX"/> 673 <array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX"/> 674 <array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX"/> 675 <array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX"/> 676 <array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX"/> 677 <array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX"/> 678 679 <array offset="0x01b0" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A8XX"/> 680 <array offset="0x01cc" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A8XX"/> 681 <array offset="0x01d4" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A8XX"/> 682 <array offset="0x01e4" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A8XX"/> 683 <array offset="0x01f4" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A8XX"/> 684 <array offset="0x0200" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A8XX"/> 685 <array offset="0x020c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A8XX"/> 686 <array offset="0x0216" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A8XX"/> 687 <array offset="0x021e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A8XX"/> 688 <array offset="0x0226" name="RBBM_PERFCTR_UCHE" stride="2" length="24" variants="A8XX"/> 689 <array offset="0x0256" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A8XX"/> 690 <array offset="0x026e" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A8XX"/> 691 <array offset="0x029e" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A8XX"/> 692 <array offset="0x02ae" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A8XX"/> 693 <array offset="0x02b2" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A8XX"/> 694 <array offset="0x02ba" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A8XX"/> 695 <array offset="0x02c2" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A8XX"/> 696 <array offset="0x02e2" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A8XX"/> 697 <array offset="0x02ee" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A8XX"/> 698 <array offset="0x02fc" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A8XX"/> 699 <array offset="0x0314" name="RBBM_PERFCTR2_TP" stride="2" length="8" variants="A8XX"/> 700 <array offset="0x0324" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A8XX"/> 701 <array offset="0x0328" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A8XX"/> 702 <array offset="0x0338" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A8XX"/> 703 <array offset="0x0348" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A8XX"/> 704 <array offset="0x0354" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A8XX"/> 705 <array offset="0x035c" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A8XX"/> 706 <array offset="0x0364" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A8XX"/> 707 <array offset="0x036c" name="RBBM_PERFCTR_BV_CCU" stride="2" length="3" variants="A8XX"/> 708 <array offset="0x0372" name="RBBM_PERFCTR_BV_RB" stride="2" length="6" variants="A8XX"/> 709 710 <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL" variants="A6XX-A7XX"/> 711 <reg32 offset="0x0460" name="RBBM_PERFCTR_CNTL" variants="A8XX-"/> 712 <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0" variants="A6XX"/> 713 <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1" variants="A6XX"/> 714 <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2" variants="A6XX"/> 715 <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3" variants="A6XX"/> 716 <reg64 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE" variants="A6XX"/> 717 <array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4" variants="A6XX-A7XX"/> 718 <array offset="0x0441" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4" variants="A8XX-"/> 719 <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED" variants="A6XX-A7XX"/> 720 <reg32 offset="0x019e" name="RBBM_PERFCTR_GPU_BUSY_MASKED" variants="A8XX-"/> 721 <reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD" variants="A6XX-A7XX"/> 722 <reg32 offset="0x0449" name="RBBM_PERFCTR_SRAM_INIT_CMD" variants="A8XX-"/> 723 <reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS" variants="A6XX-A7XX"/> 724 <reg32 offset="0x019f" name="RBBM_PERFCTR_SRAM_INIT_STATUS" variants="A8XX-"/> 725 <reg32 offset="0x01a1" name="RBBM_PERFCTR_FLUSH_HOST_STATUS" variants="A8XX-"/> 726 <reg32 offset="0x044c" name="RBBM_PERFCTR_FLUSH_HOST_CMD" variants="A8XX-"/> 727 <reg32 offset="0x0533" name="RBBM_ISDB_CNT" variants="A6XX-A7XX"/> 728 <reg32 offset="0x002d" name="RBBM_ISDB_CNT" variants="A8XX-"/> 729 <reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL" variants="A6XX-A7XX"/> 730 <reg32 offset="0x0440" name="RBBM_NC_MODE_CNTL" variants="A8XX-"/> 731 <reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX"/> 732 <reg32 offset="0x002e" name="RBBM_SNAPSHOT_STATUS" variants="A8XX-"/> 733 734 <reg32 offset="0x500" name="RBBM_SLICE_PERFCTR_CNTL" variants="A8XX-"/> 735 <reg32 offset="0x58f" name="RBBM_SLICE_INTERFACE_HANG_INT_CNTL" variants="A8XX-"/> 736 <array offset="0x5e0" name="RBBM_SLICE_PERFCTR_RBBM_SEL" stride="1" length="4" variants="A8XX-"/> 737 <reg32 offset="0x5e8" name="RBBM_SLICE_PERFCTR_SRAM_INIT_CMD" variants="A8XX-"/> 738 <reg32 offset="0x5eb" name="RBBM_SLICE_PERFCTR_FLUSH_HOST_CMD" variants="A8XX-"/> 739 <reg32 offset="0x5ec" name="RBBM_SLICE_NC_MODE_CNTL" variants="A8XX-"/> 740 741 <!--- 742 This block of registers aren't tied to perf counters. They 743 count various geometry stats, for example number of 744 vertices in, number of primnitives assembled etc. 745 --> 746 747 <reg64 offset="0x0540" name="RBBM_PIPESTAT_IAVERTICES" variants="A6XX-A7XX"/> 748 <reg64 offset="0x0542" name="RBBM_PIPESTAT_IAPRIMITIVES" variants="A6XX-A7XX"/> 749 <reg64 offset="0x0544" name="RBBM_PIPESTAT_VSINVOCATIONS" variants="A6XX-A7XX"/> 750 <reg64 offset="0x0546" name="RBBM_PIPESTAT_HSINVOCATIONS" variants="A6XX-A7XX"/> 751 <reg64 offset="0x0548" name="RBBM_PIPESTAT_DSINVOCATIONS" variants="A6XX-A7XX"/> 752 <reg64 offset="0x054a" name="RBBM_PIPESTAT_GSINVOCATIONS" variants="A6XX-A7XX"/> 753 <reg64 offset="0x054c" name="RBBM_PIPESTAT_GSPRIMITIVES" variants="A6XX-A7XX"/> 754 <reg64 offset="0x054e" name="RBBM_PIPESTAT_CINVOCATIONS" variants="A6XX-A7XX"/> 755 <reg64 offset="0x0550" name="RBBM_PIPESTAT_CPRIMITIVES" variants="A6XX-A7XX"/> 756 <reg64 offset="0x0552" name="RBBM_PIPESTAT_PSINVOCATIONS" variants="A6XX-A7XX"/> 757 <reg64 offset="0x0554" name="RBBM_PIPESTAT_CSINVOCATIONS" variants="A6XX-A7XX"/> 758 759 <reg64 offset="0x0380" name="RBBM_PIPESTAT_IAVERTICES" variants="A8XX-"/> 760 <reg64 offset="0x0382" name="RBBM_PIPESTAT_IAPRIMITIVES" variants="A8XX-"/> 761 <reg64 offset="0x0384" name="RBBM_PIPESTAT_VSINVOCATIONS" variants="A8XX-"/> 762 <reg64 offset="0x0386" name="RBBM_PIPESTAT_GSINVOCATIONS" variants="A8XX-"/> 763 <reg64 offset="0x0388" name="RBBM_PIPESTAT_GSPRIMITIVES" variants="A8XX-"/> 764 <reg64 offset="0x038a" name="RBBM_PIPESTAT_CINVOCATIONS" variants="A8XX-"/> 765 <reg64 offset="0x038c" name="RBBM_PIPESTAT_CPRIMITIVES" variants="A8XX-"/> 766 <reg64 offset="0x038e" name="RBBM_PIPESTAT_PSINVOCATIONS" variants="A8XX-"/> 767 <reg64 offset="0x0390" name="RBBM_PIPESTAT_HSINVOCATIONS" variants="A8XX-"/> 768 <reg64 offset="0x0392" name="RBBM_PIPESTAT_DSINVOCATIONS" variants="A8XX-"/> 769 <reg64 offset="0x0394" name="RBBM_PIPESTAT_CSINVOCATIONS" variants="A8XX-"/> 770 <reg64 offset="0x0396" name="RBBM_PIPESTAT_ASINVOCATIONS" variants="A8XX-"/> 771 <reg64 offset="0x0398" name="RBBM_PIPESTAT_MSINVOCATIONS" variants="A8XX-"/> 772 <reg64 offset="0x039a" name="RBBM_PIPESTAT_MSPRIMITIVES" variants="A8XX-"/> 773 774 <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/> 775 <reg64 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/> 776 <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/> 777 <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/> 778 <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 779 <reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX-"/> 780 <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL" variants="A6XX"/> 781 <reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL" variants="A6XX-A7XX"/> 782 <reg32 offset="0x00008" name="RBBM_GBIF_CLIENT_QOS_CNTL" variants="A8XX-"/> 783 <reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A6XX-A7XX"/> 784 <reg32 offset="0x0000a" name="RBBM_GBIF_HALT" variants="A8XX-"/> 785 <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A6XX-A7XX"/> 786 <reg32 offset="0x0000b" name="RBBM_GBIF_HALT_ACK" variants="A8XX-"/> 787 <reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD" variants="A6XX"> 788 <bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/> 789 </reg32> 790 791 <reg32 offset="0x01a" name="RBBM_WAIT_IDLE_CLOCKS_CNTL" variants="A6XX-A7XX"/> 792 <reg32 offset="0x01b" name="RBBM_WAIT_IDLE_CLOCKS_CNTL2" variants="A6XX-A7XX"/> 793 <reg32 offset="0x010" name="RBBM_WAIT_IDLE_CLOCKS_CNTL" variants="A8XX-"/> 794 <reg32 offset="0x011" name="RBBM_WAIT_IDLE_CLOCKS_CNTL2" variants="A8XX-"/> 795 796 <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL" variants="A6XX-A7XX"/> 797 <reg32 offset="0x0002f" name="RBBM_INTERFACE_HANG_INT_CNTL" variants="A8XX-"/> 798 <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK" variants="A6XX-A7XX"/> 799 <reg32 offset="0x00061" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK" variants="A8XX-"/> 800 <reg32 offset="0x00038" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK" variants="A6XX-A7XX"/> 801 <reg32 offset="0x00062" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK" variants="A8XX-"/> 802 <reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX"/> 803 <reg32 offset="0x00064" name="RBBM_INT_2_MASK" variants="A8XX-"/> 804 <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT" variants="A6XX-A7XX"/> 805 <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD" variants="A6XX-A7XX"/> 806 <reg32 offset="0x00073" name="RBBM_SW_RESET_CMD" variants="A8XX-"/> 807 <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT" variants="A6XX-A7XX"/> 808 <reg32 offset="0x00029" name="RBBM_RAC_THRESHOLD_CNT" variants="A8XX-"/> 809 <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD" variants="A6XX"/> 810 <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2" variants="A6XX"/> 811 <reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX"/> 812 <reg32 offset="0x0009a" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A8XX-"/> 813 <reg32 offset="0x07d" name="RBBM_POWER_UP_RESET_SW_OVERRIDE" variants="A8XX-"/> 814 <reg32 offset="0x07e" name="RBBM_POWER_UP_RESET_SW_BV_OVERRIDE" variants="A8XX-"/> 815 <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL" variants="A6XX-A7XX"/> 816 <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0" variants="A6XX-A7XX"/> 817 <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1" variants="A6XX-A7XX"/> 818 <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2" variants="A6XX-A7XX"/> 819 <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3" variants="A6XX-A7XX"/> 820 <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0" variants="A6XX-A7XX"/> 821 <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1" variants="A6XX-A7XX"/> 822 <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2" variants="A6XX-A7XX"/> 823 <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3" variants="A6XX-A7XX"/> 824 <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0" variants="A6XX-A7XX"/> 825 <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1" variants="A6XX-A7XX"/> 826 <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2" variants="A6XX-A7XX"/> 827 <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3" variants="A6XX-A7XX"/> 828 <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0" variants="A6XX-A7XX"/> 829 <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1" variants="A6XX-A7XX"/> 830 <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2" variants="A6XX-A7XX"/> 831 <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3" variants="A6XX-A7XX"/> 832 <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0" variants="A6XX-A7XX"/> 833 <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1" variants="A6XX-A7XX"/> 834 <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2" variants="A6XX-A7XX"/> 835 <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3" variants="A6XX-A7XX"/> 836 <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0" variants="A6XX-A7XX"/> 837 <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1" variants="A6XX-A7XX"/> 838 <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2" variants="A6XX-A7XX"/> 839 <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3" variants="A6XX-A7XX"/> 840 <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0" variants="A6XX-A7XX"/> 841 <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1" variants="A6XX-A7XX"/> 842 <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2" variants="A6XX-A7XX"/> 843 <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3" variants="A6XX-A7XX"/> 844 <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0" variants="A6XX-A7XX"/> 845 <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1" variants="A6XX-A7XX"/> 846 <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2" variants="A6XX-A7XX"/> 847 <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3" variants="A6XX-A7XX"/> 848 <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0" variants="A6XX-A7XX"/> 849 <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1" variants="A6XX-A7XX"/> 850 <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2" variants="A6XX-A7XX"/> 851 <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3" variants="A6XX-A7XX"/> 852 <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0" variants="A6XX-A7XX"/> 853 <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1" variants="A6XX-A7XX"/> 854 <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2" variants="A6XX-A7XX"/> 855 <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3" variants="A6XX-A7XX"/> 856 <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0" variants="A6XX-A7XX"/> 857 <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1" variants="A6XX-A7XX"/> 858 <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2" variants="A6XX-A7XX"/> 859 <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3" variants="A6XX-A7XX"/> 860 <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0" variants="A6XX-A7XX"/> 861 <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1" variants="A6XX-A7XX"/> 862 <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2" variants="A6XX-A7XX"/> 863 <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3" variants="A6XX-A7XX"/> 864 <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0" variants="A6XX-A7XX"/> 865 <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1" variants="A6XX-A7XX"/> 866 <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2" variants="A6XX-A7XX"/> 867 <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3" variants="A6XX-A7XX"/> 868 <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0" variants="A6XX-A7XX"/> 869 <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1" variants="A6XX-A7XX"/> 870 <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2" variants="A6XX-A7XX"/> 871 <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3" variants="A6XX-A7XX"/> 872 <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0" variants="A6XX-A7XX"/> 873 <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1" variants="A6XX-A7XX"/> 874 <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2" variants="A6XX-A7XX"/> 875 <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3" variants="A6XX-A7XX"/> 876 <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0" variants="A6XX-A7XX"/> 877 <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1" variants="A6XX-A7XX"/> 878 <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2" variants="A6XX-A7XX"/> 879 <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3" variants="A6XX-A7XX"/> 880 <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0" variants="A6XX-A7XX"/> 881 <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1" variants="A6XX-A7XX"/> 882 <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2" variants="A6XX-A7XX"/> 883 <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3" variants="A6XX-A7XX"/> 884 <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0" variants="A6XX-A7XX"/> 885 <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1" variants="A6XX-A7XX"/> 886 <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2" variants="A6XX-A7XX"/> 887 <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3" variants="A6XX-A7XX"/> 888 <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0" variants="A6XX-A7XX"/> 889 <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1" variants="A6XX-A7XX"/> 890 <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2" variants="A6XX-A7XX"/> 891 <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3" variants="A6XX-A7XX"/> 892 <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0" variants="A6XX-A7XX"/> 893 <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1" variants="A6XX-A7XX"/> 894 <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2" variants="A6XX-A7XX"/> 895 <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3" variants="A6XX-A7XX"/> 896 <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC" variants="A6XX-A7XX"/> 897 <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC" variants="A6XX-A7XX"/> 898 <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC" variants="A6XX-A7XX"/> 899 <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC" variants="A6XX-A7XX"/> 900 <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM" variants="A6XX-A7XX"/> 901 <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM" variants="A6XX-A7XX"/> 902 <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM" variants="A6XX-A7XX"/> 903 <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE" variants="A6XX-A7XX"/> 904 <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE" variants="A6XX-A7XX"/> 905 <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE" variants="A6XX-A7XX"/> 906 <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE" variants="A6XX-A7XX"/> 907 <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE" variants="A6XX-A7XX"/> 908 <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE" variants="A6XX-A7XX"/> 909 <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD" variants="A6XX-A7XX"/> 910 <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD" variants="A6XX-A7XX"/> 911 <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD" variants="A6XX-A7XX"/> 912 <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC" variants="A6XX-A7XX"/> 913 <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC" variants="A6XX-A7XX"/> 914 <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC" variants="A6XX-A7XX"/> 915 <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2" variants="A6XX-A7XX"/> 916 <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX" variants="A6XX-A7XX"/> 917 <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX" variants="A6XX-A7XX"/> 918 <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX" variants="A6XX-A7XX"/> 919 <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ" variants="A6XX-A7XX"/> 920 <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ" variants="A6XX-A7XX"/> 921 <reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ" variants="A6XX-A7XX"/> 922 <reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX"/> 923 <reg32 offset="0x0009b" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A8XX-"/> 924 <reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX"/> 925 <reg32 offset="0x0009c" name="RBBM_CGC_P2S_TRIG_CMD" variants="A8XX-"/> 926 <reg32 offset="0x00120" name="RBBM_CGC_P2S_CNTL" variants="A7XX"/> 927 <reg32 offset="0x0009d" name="RBBM_CGC_P2S_CNTL" variants="A8XX-"/> 928 <reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE" variants="A6XX"/> 929 <reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE" variants="A6XX-A7XX"/> 930 <reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE" variants="A6XX"/> 931 <reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX"> 932 <bitfield name="TXDONE" pos="0" type="boolean"/> 933 </reg32> 934 <reg32 offset="0x09f" name="RBBM_CGC_P2S_STATUS" variants="A8XX-"> 935 <bitfield name="TXDONE" pos="0" type="boolean"/> 936 </reg32> 937 <reg32 offset="0x00123" name="RBBM_CLOCK_CNTL_FCHE" variants="A6XX-A7XX"/> 938 <reg32 offset="0x00124" name="RBBM_CLOCK_DELAY_FCHE" variants="A6XX-A7XX"/> 939 <reg32 offset="0x00125" name="RBBM_CLOCK_HYST_FCHE" variants="A6XX-A7XX"/> 940 <reg32 offset="0x00126" name="RBBM_CLOCK_CNTL_MHUB" variants="A6XX-A7XX"/> 941 <reg32 offset="0x00127" name="RBBM_CLOCK_DELAY_MHUB" variants="A6XX-A7XX"/> 942 <reg32 offset="0x00128" name="RBBM_CLOCK_HYST_MHUB" variants="A6XX-A7XX"/> 943 <reg32 offset="0x00129" name="RBBM_CLOCK_DELAY_GLC" variants="A6XX-A7XX"/> 944 <reg32 offset="0x0012a" name="RBBM_CLOCK_HYST_GLC" variants="A6XX-A7XX"/> 945 <reg32 offset="0x0012b" name="RBBM_CLOCK_CNTL_GLC" variants="A6XX-A7XX"/> 946 <reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX"/> 947 <reg32 offset="0x00195" name="RBBM_CGC_0_PC" variants="A7XX"/> 948 <reg32 offset="0x0010b" name="RBBM_CGC_0_PC" variants="A8XX-"/> 949 950 <reg32 offset="0x005ff" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL" variants="A6XX-A7XX"/> 951 <reg32 offset="0x00009" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL" variants="A8XX-"/> 952 953 <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/> 954 <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/> 955 <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/> 956 <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D" variants="A6XX"> 957 <bitfield high="7" low="0" name="PING_INDEX"/> 958 <bitfield high="15" low="8" name="PING_BLK_SEL"/> 959 </reg32> 960 <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D" variants="A7XX-"> 961 <bitfield high="7" low="0" name="PING_INDEX"/> 962 <bitfield high="24" low="16" name="PING_BLK_SEL"/> 963 </reg32> 964 <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT"> 965 <bitfield high="5" low="0" name="TRACEEN"/> 966 <bitfield high="14" low="12" name="GRANU"/> 967 <bitfield high="31" low="28" name="SEGT"/> 968 </reg32> 969 <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM"> 970 <bitfield high="27" low="24" name="ENABLE"/> 971 </reg32> 972 <reg32 offset="0x0606" name="DBGC_CFG_DBGBUS_OPL"/> 973 <reg32 offset="0x0607" name="DBGC_CFG_DBGBUS_OPE"/> 974 <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/> 975 <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/> 976 <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/> 977 <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/> 978 <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/> 979 <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/> 980 <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/> 981 <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/> 982 <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0"> 983 <bitfield high="3" low="0" name="BYTEL0"/> 984 <bitfield high="7" low="4" name="BYTEL1"/> 985 <bitfield high="11" low="8" name="BYTEL2"/> 986 <bitfield high="15" low="12" name="BYTEL3"/> 987 <bitfield high="19" low="16" name="BYTEL4"/> 988 <bitfield high="23" low="20" name="BYTEL5"/> 989 <bitfield high="27" low="24" name="BYTEL6"/> 990 <bitfield high="31" low="28" name="BYTEL7"/> 991 </reg32> 992 <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1"> 993 <bitfield high="3" low="0" name="BYTEL8"/> 994 <bitfield high="7" low="4" name="BYTEL9"/> 995 <bitfield high="11" low="8" name="BYTEL10"/> 996 <bitfield high="15" low="12" name="BYTEL11"/> 997 <bitfield high="19" low="16" name="BYTEL12"/> 998 <bitfield high="23" low="20" name="BYTEL13"/> 999 <bitfield high="27" low="24" name="BYTEL14"/> 1000 <bitfield high="31" low="28" name="BYTEL15"/> 1001 </reg32> 1002 <reg32 offset="0x0612" name="DBGC_CFG_DBGBUS_IVTE_0"/> 1003 <reg32 offset="0x0613" name="DBGC_CFG_DBGBUS_IVTE_1"/> 1004 <reg32 offset="0x0614" name="DBGC_CFG_DBGBUS_IVTE_2"/> 1005 <reg32 offset="0x0615" name="DBGC_CFG_DBGBUS_IVTE_3"/> 1006 <reg32 offset="0x0616" name="DBGC_CFG_DBGBUS_MASKE_0"/> 1007 <reg32 offset="0x0617" name="DBGC_CFG_DBGBUS_MASKE_1"/> 1008 <reg32 offset="0x0618" name="DBGC_CFG_DBGBUS_MASKE_2"/> 1009 <reg32 offset="0x0619" name="DBGC_CFG_DBGBUS_MASKE_3"/> 1010 <reg32 offset="0x061a" name="DBGC_CFG_DBGBUS_NIBBLEE"/> 1011 <reg32 offset="0x061b" name="DBGC_CFG_DBGBUS_PTRC0"/> 1012 <reg32 offset="0x061c" name="DBGC_CFG_DBGBUS_PTRC1"/> 1013 <reg32 offset="0x061d" name="DBGC_CFG_DBGBUS_LOADREG"/> 1014 <reg32 offset="0x061e" name="DBGC_CFG_DBGBUS_IDX"/> 1015 <reg32 offset="0x061f" name="DBGC_CFG_DBGBUS_CLRC"/> 1016 <reg32 offset="0x0620" name="DBGC_CFG_DBGBUS_LOADIVT"/> 1017 <reg32 offset="0x0621" name="DBGC_VBIF_DBG_CNTL"/> 1018 <reg32 offset="0x0622" name="DBGC_DBG_LO_HI_GPIO"/> 1019 <reg32 offset="0x0623" name="DBGC_EXT_TRACE_BUS_CNTL"/> 1020 <reg32 offset="0x0624" name="DBGC_READ_AHB_THROUGH_DBG"/> 1021 <reg32 offset="0x0625" name="DBGC_CFG_DBGBUS_EVENT_LOGIC"/> 1022 <reg32 offset="0x0626" name="DBGC_CFG_DBGBUS_OVER"/> 1023 <reg32 offset="0x0627" name="DBGC_CFG_DBGBUS_COUNT0"/> 1024 <reg32 offset="0x0628" name="DBGC_CFG_DBGBUS_COUNT1"/> 1025 <reg32 offset="0x0629" name="DBGC_CFG_DBGBUS_COUNT2"/> 1026 <reg32 offset="0x062a" name="DBGC_CFG_DBGBUS_COUNT3"/> 1027 <reg32 offset="0x062b" name="DBGC_CFG_DBGBUS_COUNT4"/> 1028 <reg32 offset="0x062c" name="DBGC_CFG_DBGBUS_COUNT5"/> 1029 <reg32 offset="0x062d" name="DBGC_CFG_DBGBUS_TRACE_ADDR"/> 1030 <reg32 offset="0x062e" name="DBGC_CFG_DBGBUS_TRACE_BUF0"/> 1031 <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/> 1032 <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/> 1033 <reg32 offset="0x0631" name="DBGC_CFG_DBGBUS_TRACE_BUF3"/> 1034 <reg32 offset="0x0632" name="DBGC_CFG_DBGBUS_TRACE_BUF4"/> 1035 <reg32 offset="0x0633" name="DBGC_CFG_DBGBUS_MISR0"/> 1036 <reg32 offset="0x0634" name="DBGC_CFG_DBGBUS_MISR1"/> 1037 <reg32 offset="0x0635" name="DBGC_EVT_CFG"/> 1038 <reg32 offset="0x0636" name="DBGC_EVT_INTF_SEL_0"/> 1039 <reg32 offset="0x0637" name="DBGC_EVT_INTF_SEL_1"/> 1040 <reg32 offset="0x0638" name="DBGC_EVT_SLICE_CFG"/> 1041 <reg32 offset="0x0639" name="DBGC_QDSS_TIMESTAMP_0"/> 1042 <reg32 offset="0x063a" name="DBGC_QDSS_TIMESTAMP_1"/> 1043 <reg32 offset="0x063b" name="DBGC_ECO_CNTL"/> 1044 <reg32 offset="0x063c" name="DBGC_AHB_DBG_CNTL"/> 1045 <reg32 offset="0x063d" name="DBGC_EVT_INTF_SEL_2"/> 1046 <reg32 offset="0x0640" name="DBGC_CFG_DBGBUS_PONG_SEL_A"/> 1047 <reg32 offset="0x0641" name="DBGC_CFG_DBGBUS_PONG_SEL_B"/> 1048 <reg32 offset="0x0642" name="DBGC_CFG_DBGBUS_PONG_SEL_C"/> 1049 <reg32 offset="0x0643" name="DBGC_CFG_DBGBUS_PONG_SEL_D"/> 1050 <reg32 offset="0x0644" name="DBGC_CFG_DBGBUS_MISC_MODE"/> 1051 <reg32 offset="0x0650" name="DBGC_EVT_INTF_SEL_3_0"/> 1052 <reg32 offset="0x0651" name="DBGC_EVT_INTF_SEL_3_1"/> 1053 <reg32 offset="0x0652" name="DBGC_EVT_INTF_SEL_3_2"/> 1054 <reg32 offset="0x0653" name="DBGC_EVT_INTF_SEL_3_3"/> 1055 <reg32 offset="0x0654" name="DBGC_EVT_INTF_SEL_3_4"/> 1056 <reg32 offset="0x0655" name="DBGC_EVT_INTF_SEL_3_5"/> 1057 <reg32 offset="0x0660" name="DBGC_TRACE_BUFFER_STATUS"/> 1058 <reg32 offset="0x0661" name="DBGC_TRACE_BUFFER_CMD"/> 1059 <reg32 offset="0x0662" name="DBGC_DBG_TRACE_BUFFER_RD_ADDR"/> 1060 <reg32 offset="0x0663" name="DBGC_DBG_TRACE_BUFFER_RD_DATA"/> 1061 <reg32 offset="0x0664" name="DBGC_TRACE_BUFFER_ATB_RD_STATUS"/> 1062 <reg32 offset="0x0665" name="DBGC_SMMU_FAULT_BLOCK_HALT_CFG"/> 1063 <reg32 offset="0x0666" name="DBGC_DBG_LOPC_SB_RD_ADDR"/> 1064 <reg32 offset="0x0667" name="DBGC_DBG_LOPC_SB_RD_DATA"/> 1065 <reg32 offset="0x0668" name="DBGC_DBG_LOPC_SB_WR_ADDR"/> 1066 <reg32 offset="0x0669" name="DBGC_DBG_LOPC_SB_WR_DATA"/> 1067 <reg32 offset="0x066a" name="DBGC_INTERRUPT_STATUS"/> 1068 <reg64 offset="0x0680" name="DBGC_GBIF_DBG_BASE"/> 1069 <reg32 offset="0x0682" name="DBGC_GBIF_DBG_BUFF_SIZE"/> 1070 <reg32 offset="0x0683" name="DBGC_GBIF_DBG_CNTL"/> 1071 <reg32 offset="0x0684" name="DBGC_GBIF_DBG_CMD"/> 1072 <reg32 offset="0x0685" name="DBGC_GBIF_DBG_STATUS"/> 1073 1074 <reg32 offset="0x0700" name="DBGC_SCOPE_PERF_COUNTER_CFG_US" variants="A8XX-"/> 1075 <reg32 offset="0x0701" name="DBGC_CFG_PERF_TRIG_CLUSTER_FE_US" variants="A8XX-"/> 1076 <reg32 offset="0x0702" name="DBGC_CFG_PERF_TRIG_CLUSTER_VPC_US" variants="A8XX-"/> 1077 <reg32 offset="0x0703" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_VS_US" variants="A8XX-"/> 1078 <reg32 offset="0x0704" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_PS_US" variants="A8XX-"/> 1079 <reg32 offset="0x0707" name="DBGC_CFG_PERF_TRIG_CLUSTER_NONE_US" variants="A8XX-"/> 1080 <reg32 offset="0x0708" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_FE_US" variants="A8XX-"/> 1081 <reg32 offset="0x0709" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_VPC_US" variants="A8XX-"/> 1082 <reg32 offset="0x070a" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_SP_VS_US" variants="A8XX-"/> 1083 <reg32 offset="0x070f" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_NONE_US" variants="A8XX-"/> 1084 <reg32 offset="0x0710" name="DBGC_CFG_PERF_COUNTER_SEL_FE_US" variants="A8XX-"/> 1085 <reg32 offset="0x0711" name="DBGC_CFG_PERF_COUNTER_SEL_FE_US_1" variants="A8XX-"/> 1086 <reg32 offset="0x0712" name="DBGC_CFG_PERF_COUNTER_SEL_FE_US_2" variants="A8XX-"/> 1087 <reg32 offset="0x0713" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_US" variants="A8XX-"/> 1088 <reg32 offset="0x0714" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_US_1" variants="A8XX-"/> 1089 <reg32 offset="0x0715" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_US" variants="A8XX-"/> 1090 <reg32 offset="0x0716" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_US" variants="A8XX-"/> 1091 <reg32 offset="0x0720" name="DBGC_CFG_PERF_COUNTER_SEL_NONE_US" variants="A8XX-"/> 1092 <reg32 offset="0x0721" name="DBGC_CFG_PERF_COUNTER_SEL_NONE_US_1" variants="A8XX-"/> 1093 <reg32 offset="0x0722" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_US" variants="A8XX-"/> 1094 <reg32 offset="0x0723" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_US_1" variants="A8XX-"/> 1095 <reg32 offset="0x0724" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_US_2" variants="A8XX-"/> 1096 <reg32 offset="0x0730" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_US" variants="A8XX-"/> 1097 <reg32 offset="0x0731" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_US_1" variants="A8XX-"/> 1098 <reg32 offset="0x0732" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_US" variants="A8XX-"/> 1099 <reg32 offset="0x0740" name="DBGC_CFG_BV_PERF_COUNTER_SEL_NONE_US" variants="A8XX-"/> 1100 <reg32 offset="0x0742" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_US" variants="A8XX-"/> 1101 <reg32 offset="0x0743" name="DBGC_CFG_BV_PERF_TIMESTAMP_TRIG_SEL_US" variants="A8XX-"/> 1102 <reg64 offset="0x0744" name="DBGC_CFG_GBIF_BR_PERF_CNTR_BASE" variants="A8XX-"/> 1103 <reg32 offset="0x0746" name="DBGC_CFG_GBIF_BR_BUFFER_SIZE" variants="A8XX-"/> 1104 <reg64 offset="0x0747" name="DBGC_CFG_GBIF_BV_PERF_CNTR_BASE" variants="A8XX-"/> 1105 <reg32 offset="0x0749" name="DBGC_CFG_GBIF_BV_BUFFER_SIZE" variants="A8XX-"/> 1106 <reg32 offset="0x074a" name="DBGC_CFG_GBIF_QOS_CTRL" variants="A8XX-"/> 1107 <reg32 offset="0x0750" name="DBGC_GBIF_BR_PERF_CNTR_WRITE_POINTER" variants="A8XX-"/> 1108 <reg32 offset="0x0751" name="DBGC_GBIF_BV_PERF_CNTR_WRITE_POINTER" variants="A8XX-"/> 1109 <reg32 offset="0x0752" name="DBGC_PERF_COUNTER_FE_LOCAL_BATCH_ID" variants="A8XX-"/> 1110 <reg32 offset="0x0753" name="DBGC_CFG_PERF_WAIT_IDLE_CLOCKS_CNTL" variants="A8XX-"/> 1111 <reg32 offset="0x0754" name="DBGC_PERF_COUNTER_SCOPING_CMD_US" variants="A8XX-"/> 1112 <reg32 offset="0x0755" name="DBGC_PERF_SKEW_BUFFER_INIT_CMD" variants="A8XX-"/> 1113 <reg32 offset="0x0759" name="DBGC_LOPC_INTERRUPT_STATUS" variants="A8XX-"/> 1114 <reg32 offset="0x075a" name="DBGC_LOPC_BUFFER_PTR_STATUS" variants="A8XX-"/> 1115 <reg32 offset="0x075b" name="DBGC_PERF_SCOPING_STATUS" variants="A8XX-"/> 1116 <reg32 offset="0x075c" name="DBGC_PERF_COUNTER_PKT_STATUS" variants="A8XX-"/> 1117 <reg32 offset="0x0760" name="DBGC_GC_LIVE_MBX_PKT_STATUS" variants="A8XX-"/> 1118 <reg32 offset="0x0761" name="DBGC_GC_ALW_MBX_PKT_STATUS" variants="A8XX-"/> 1119 <reg32 offset="0x0762" name="DBGC_AO_CNTR_LO_STATUS" variants="A8XX-"/> 1120 <reg32 offset="0x0763" name="DBGC_AO_CNTR_HI_STATUS" variants="A8XX-"/> 1121 <reg32 offset="0x0770" name="DBGC_LOPC_GC_SB_DEPTH_STATUS" variants="A8XX-"/> 1122 <reg32 offset="0x0780" name="DBGC_LPAC_SCOPE_PERF_COUNTER_CFG_US" variants="A8XX-"/> 1123 <reg32 offset="0x0781" name="DBGC_CFG_PERF_TRIG_LPAC_US" variants="A8XX-"/> 1124 <reg32 offset="0x0782" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_US" variants="A8XX-"/> 1125 <reg32 offset="0x0783" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_US_1" variants="A8XX-"/> 1126 <reg32 offset="0x0784" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_US_2" variants="A8XX-"/> 1127 <reg32 offset="0x0785" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_LPAC_US" variants="A8XX-"/> 1128 <reg64 offset="0x0786" name="DBGC_CFG_GBIF_LPAC_PERF_CNTR_BASE" variants="A8XX-"/> 1129 <reg32 offset="0x0788" name="DBGC_CFG_GBIF_LPAC_BUFFER_SIZE" variants="A8XX-"/> 1130 <reg32 offset="0x0789" name="DBGC_GBIF_LPAC_PERF_CNTR_WRITE_POINTER" variants="A8XX-"/> 1131 <reg32 offset="0x078a" name="DBGC_CFG_LPAC_PERF_WAIT_IDLE_CLOCKS_CNTL" variants="A8XX-"/> 1132 <reg32 offset="0x078b" name="DBGC_LPAC_PERF_COUNTER_SCOPING_CMD_US" variants="A8XX-"/> 1133 <reg32 offset="0x078c" name="DBGC_LPAC_MBX_PKT_STATUS" variants="A8XX-"/> 1134 <reg32 offset="0x078d" name="DBGC_LPAC_PERF_SCOPING_STATUS" variants="A8XX-"/> 1135 <reg32 offset="0x0790" name="DBGC_LOPC_LPAC_SB_DEPTH_STATUS" variants="A8XX-"/> 1136 <reg32 offset="0x07a0" name="DBGC_SCOPE_PERF_COUNTER_CFG_S" variants="A8XX-"/> 1137 <reg32 offset="0x07a1" name="DBGC_CFG_PERF_TRIG_CLUSTER_FE_S" variants="A8XX-"/> 1138 <reg32 offset="0x07a2" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_VS" variants="A8XX-"/> 1139 <reg32 offset="0x07a3" name="DBGC_CFG_PERF_TRIG_CLUSTER_VPC_VS" variants="A8XX-"/> 1140 <reg32 offset="0x07a4" name="DBGC_CFG_PERF_TRIG_CLUSTER_GRAS" variants="A8XX-"/> 1141 <reg32 offset="0x07a5" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_PS" variants="A8XX-"/> 1142 <reg32 offset="0x07a6" name="DBGC_CFG_PERF_TRIG_CLUSTER_VPC_PS" variants="A8XX-"/> 1143 <reg32 offset="0x07a7" name="DBGC_CFG_PERF_TRIG_CLUSTER_PS" variants="A8XX-"/> 1144 <reg32 offset="0x07a8" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_FE_S" variants="A8XX-"/> 1145 <reg32 offset="0x07a9" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_SP_VS" variants="A8XX-"/> 1146 <reg32 offset="0x07aa" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_VPC_VS" variants="A8XX-"/> 1147 <reg32 offset="0x07ab" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_GRAS" variants="A8XX-"/> 1148 <reg32 offset="0x07ac" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_VPC_PS" variants="A8XX-"/> 1149 <reg32 offset="0x07ad" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S" variants="A8XX-"/> 1150 <reg32 offset="0x07ae" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S_1" variants="A8XX-"/> 1151 <reg32 offset="0x07af" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S_2" variants="A8XX-"/> 1152 <reg32 offset="0x07b0" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S_3" variants="A8XX-"/> 1153 <reg32 offset="0x07b1" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS" variants="A8XX-"/> 1154 <reg32 offset="0x07b2" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_1" variants="A8XX-"/> 1155 <reg32 offset="0x07b3" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_2" variants="A8XX-"/> 1156 <reg32 offset="0x07b4" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_3" variants="A8XX-"/> 1157 <reg32 offset="0x07b5" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_VS" variants="A8XX-"/> 1158 <reg32 offset="0x07b6" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_VS_1" variants="A8XX-"/> 1159 <reg32 offset="0x07b7" name="DBGC_CFG_PERF_COUNTER_SEL_GRAS" variants="A8XX-"/> 1160 <reg32 offset="0x07b8" name="DBGC_CFG_PERF_COUNTER_SEL_GRAS_1" variants="A8XX-"/> 1161 <reg32 offset="0x07b9" name="DBGC_CFG_PERF_COUNTER_SEL_GRAS_2" variants="A8XX-"/> 1162 <reg32 offset="0x07ba" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS" variants="A8XX-"/> 1163 <reg32 offset="0x07bb" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_1" variants="A8XX-"/> 1164 <reg32 offset="0x07bc" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_2" variants="A8XX-"/> 1165 <reg32 offset="0x07bd" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_3" variants="A8XX-"/> 1166 <reg32 offset="0x07be" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_PS" variants="A8XX-"/> 1167 <reg32 offset="0x07bf" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_PS_1" variants="A8XX-"/> 1168 <reg32 offset="0x07c0" name="DBGC_CFG_PERF_COUNTER_SEL_PS" variants="A8XX-"/> 1169 <reg32 offset="0x07c1" name="DBGC_CFG_PERF_COUNTER_SEL_PS_1" variants="A8XX-"/> 1170 <reg32 offset="0x07c2" name="DBGC_CFG_PERF_COUNTER_SEL_PS_2" variants="A8XX-"/> 1171 <reg32 offset="0x07c3" name="DBGC_CFG_PERF_COUNTER_SEL_PS_3" variants="A8XX-"/> 1172 <reg32 offset="0x07c4" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_S" variants="A8XX-"/> 1173 <reg32 offset="0x07c5" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S" variants="A8XX-"/> 1174 <reg32 offset="0x07c6" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S_1" variants="A8XX-"/> 1175 <reg32 offset="0x07c7" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S_2" variants="A8XX-"/> 1176 <reg32 offset="0x07c8" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S_3" variants="A8XX-"/> 1177 <reg32 offset="0x07c9" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS" variants="A8XX-"/> 1178 <reg32 offset="0x07ca" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_1" variants="A8XX-"/> 1179 <reg32 offset="0x07cb" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_2" variants="A8XX-"/> 1180 <reg32 offset="0x07cc" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_3" variants="A8XX-"/> 1181 <reg32 offset="0x07cd" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_VS" variants="A8XX-"/> 1182 <reg32 offset="0x07ce" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_VS_1" variants="A8XX-"/> 1183 <reg32 offset="0x07cf" name="DBGC_CFG_BV_PERF_COUNTER_SEL_GRAS" variants="A8XX-"/> 1184 <reg32 offset="0x07d0" name="DBGC_CFG_BV_PERF_COUNTER_SEL_GRAS_1" variants="A8XX-"/> 1185 <reg32 offset="0x07d1" name="DBGC_CFG_BV_PERF_COUNTER_SEL_GRAS_2" variants="A8XX-"/> 1186 <reg32 offset="0x07d2" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_PS" variants="A8XX-"/> 1187 <reg32 offset="0x07d3" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_PS_1" variants="A8XX-"/> 1188 <reg32 offset="0x07d4" name="DBGC_CFG_BV_PERF_TIMESTAMP_TRIG_SEL_S" variants="A8XX-"/> 1189 <reg32 offset="0x07d5" name="DBGC_PERF_COUNTER_SCOPING_CMD_S" variants="A8XX-"/> 1190 <reg32 offset="0x07e0" name="DBGC_LPAC_SCOPE_PERF_COUNTER_CFG_S" variants="A8XX-"/> 1191 <reg32 offset="0x07e1" name="DBGC_CFG_PERF_TRIG_LPAC_S" variants="A8XX-"/> 1192 <reg32 offset="0x07e2" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_S" variants="A8XX-"/> 1193 <reg32 offset="0x07e3" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_S_1" variants="A8XX-"/> 1194 <reg32 offset="0x07e4" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_S_2" variants="A8XX-"/> 1195 <reg32 offset="0x07e5" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_LPAC_S" variants="A8XX-"/> 1196 <reg32 offset="0x07e6" name="DBGC_LPAC_PERF_COUNTER_SCOPING_CMD_S" variants="A8XX-"/> 1197 1198 <array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/> 1199 <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/> 1200 <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/> 1201 <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 1202 <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/> 1203 <reg64 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX" variants="A6XX"/> 1204 <reg64 offset="0x0E07" name="UCHE_WRITE_THRU_BASE" variants="A6XX-A7XX"/> 1205 <reg64 offset="0x0E06" name="UCHE_WRITE_THRU_BASE" variants="A8XX-"/> 1206 <reg64 offset="0x0E09" name="UCHE_TRAP_BASE" variants="A6XX-A7XX"/> 1207 <reg64 offset="0x0E08" name="UCHE_TRAP_BASE" variants="A8XX-"/> 1208 <reg64 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN" variants="A6XX-A7XX"/> 1209 <reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX" variants="A6XX-A7XX"/> 1210 <reg32 offset="0x0e17" name="UCHE_CACHE_WAYS" variants="A6XX-A7XX" usage="init"/> 1211 <reg32 offset="0x0e04" name="UCHE_CACHE_WAYS" variants="A8XX-"/> 1212 <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/> 1213 <reg32 offset="0x0e19" name="UCHE_CLIENT_PF" variants="A6XX-A7XX" usage="init"> 1214 <bitfield high="7" low="0" name="PERFSEL"/> 1215 </reg32> 1216 <array offset="0x0e1c" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12" variants="A6XX-A7XX"/> 1217 <array offset="0x0e20" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="24" variants="A8XX-"/> 1218 <reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG" variants="A6XX-A7XX"/> 1219 <reg32 offset="0x0e12" name="UCHE_GBIF_GX_CONFIG" variants="A8XX-"/> 1220 <reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG" variants="A6XX-A7XX"/> 1221 1222 <reg32 offset="0x0f01" name="UCHE_CCHE_MODE_CNTL" variants="A8XX-"/> 1223 <reg32 offset="0x0f02" name="UCHE_CCHE_CACHE_WAYS" variants="A8XX-"/> 1224 <reg64 offset="0x0f04" name="UCHE_CCHE_WRITE_THRU_BASE" variants="A8XX-"/> 1225 <reg64 offset="0x0f06" name="UCHE_CCHE_TRAP_BASE" variants="A8XX-"/> 1226 <reg64 offset="0x0f08" name="UCHE_CCHE_GC_GMEM_RANGE_MIN" variants="A8XX-"/> 1227 <reg64 offset="0x0f0a" name="UCHE_CCHE_LPAC_GMEM_RANGE_MIN" variants="A8XX-"/> 1228 <reg32 offset="0x0f0c" name="UCHE_CCHE_HW_DBG_CNTL" variants="A8XX-"/> 1229 1230 <!-- VBIF only existed on early a6xx, and was later replaced with GBIF --> 1231 1232 <reg32 offset="0x3000" name="VBIF_VERSION" variants="A6XX"/> 1233 <reg32 offset="0x3001" name="VBIF_CLKON" variants="A6XX"> 1234 <bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/> 1235 </reg32> 1236 <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN" variants="A6XX"/> 1237 <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0" variants="A6XX"/> 1238 <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1" variants="A6XX"/> 1239 <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL" variants="A6XX"/> 1240 <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0" variants="A6XX"/> 1241 <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1" variants="A6XX"> 1242 <bitfield low="0" high="3" name="DATA_SEL"/> 1243 </reg32> 1244 <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0" variants="A6XX"/> 1245 <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1" variants="A6XX"> 1246 <bitfield low="0" high="8" name="DATA_SEL"/> 1247 </reg32> 1248 <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT" variants="A6XX"/> 1249 <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" variants="A6XX"/> 1250 <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" variants="A6XX"/> 1251 <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" variants="A6XX"/> 1252 <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" variants="A6XX"/> 1253 <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0" variants="A6XX"/> 1254 <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1" variants="A6XX"/> 1255 <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2" variants="A6XX"/> 1256 <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3" variants="A6XX"/> 1257 <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0" variants="A6XX"/> 1258 <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1" variants="A6XX"/> 1259 <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2" variants="A6XX"/> 1260 <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3" variants="A6XX"/> 1261 <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0" variants="A6XX"/> 1262 <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1" variants="A6XX"/> 1263 <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2" variants="A6XX"/> 1264 <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0" variants="A6XX"/> 1265 <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1" variants="A6XX"/> 1266 <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2" variants="A6XX"/> 1267 <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0" variants="A6XX"/> 1268 <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1" variants="A6XX"/> 1269 <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2" variants="A6XX"/> 1270 1271 <reg32 offset="0x3c00" name="GBIF_CX_CONFIG" variants="A6XX-"/> 1272 <reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/> 1273 <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/> 1274 <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/> 1275 <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/> 1276 <reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/> 1277 <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/> 1278 <reg32 offset="0x3c45" name="GBIF_HALT"/> 1279 <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/> 1280 <reg32 offset="0x3c49" name="GBIF_REINIT_ENABLE" variants="A8XX-"/> 1281 <reg32 offset="0x3c4a" name="GBIF_REINIT_DONE" variants="A8XX-"/> 1282 <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/> 1283 <reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/> 1284 <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/> 1285 <reg32 offset="0x3cc3" name="GBIF_PERF_CNT_SEL_1" variants="A8XX-"/> 1286 1287 <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL" variants="A6XX-A7XX"/> 1288 <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0" variants="A6XX-A7XX"/> 1289 <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1" variants="A6XX-A7XX"/> 1290 <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2" variants="A6XX-A7XX"/> 1291 <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3" variants="A6XX-A7XX"/> 1292 <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0" variants="A6XX-A7XX"/> 1293 <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1" variants="A6XX-A7XX"/> 1294 <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2" variants="A6XX-A7XX"/> 1295 <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3" variants="A6XX-A7XX"/> 1296 <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0" variants="A6XX-A7XX"/> 1297 <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1" variants="A6XX-A7XX"/> 1298 <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2" variants="A6XX-A7XX"/> 1299 <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0" variants="A6XX-A7XX"/> 1300 <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1" variants="A6XX-A7XX"/> 1301 <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2" variants="A6XX-A7XX"/> 1302 1303 <reg32 offset="0x3cc4" name="GBIF_PWR_CNT_SEL" variants="A8XX"/> 1304 <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LO_0" variants="A8XX"/> 1305 <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_HI_0" variants="A8XX"/> 1306 <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_LO_1" variants="A8XX"/> 1307 <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HI_1" variants="A8XX"/> 1308 <reg32 offset="0x3cca" name="GBIF_PERF_CNT_LO_2" variants="A8XX"/> 1309 <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HI_2" variants="A8XX"/> 1310 <reg32 offset="0x3ccc" name="GBIF_PERF_CNT_LO_3" variants="A8XX"/> 1311 <reg32 offset="0x3ccd" name="GBIF_PERF_CNT_HI_3" variants="A8XX"/> 1312 <reg32 offset="0x3cce" name="GBIF_PERF_CNT_LO_4" variants="A8XX"/> 1313 <reg32 offset="0x3ccf" name="GBIF_PERF_CNT_HI_4" variants="A8XX"/> 1314 <reg32 offset="0x3cd0" name="GBIF_PERF_CNT_LO_5" variants="A8XX"/> 1315 <reg32 offset="0x3cd1" name="GBIF_PERF_CNT_HI_5" variants="A8XX"/> 1316 <reg32 offset="0x3cd2" name="GBIF_PERF_CNT_LO_6" variants="A8XX"/> 1317 <reg32 offset="0x3cd3" name="GBIF_PERF_CNT_HI_6" variants="A8XX"/> 1318 <reg32 offset="0x3cd4" name="GBIF_PERF_CNT_LO_7" variants="A8XX"/> 1319 <reg32 offset="0x3cd5" name="GBIF_PERF_CNT_HI_7" variants="A8XX"/> 1320 <reg32 offset="0x3ce0" name="GBIF_PWR_CNT_LO_0" variants="A8XX"/> 1321 <reg32 offset="0x3ce1" name="GBIF_PWR_CNT_LO_1" variants="A8XX"/> 1322 <reg32 offset="0x3ce2" name="GBIF_PWR_CNT_LO_2" variants="A8XX"/> 1323 <reg32 offset="0x3ce3" name="GBIF_PWR_CNT_HI_0" variants="A8XX"/> 1324 <reg32 offset="0x3ce4" name="GBIF_PWR_CNT_HI_1" variants="A8XX"/> 1325 <reg32 offset="0x3ce5" name="GBIF_PWR_CNT_HI_2" variants="A8XX"/> 1326 1327 <reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/> 1328 <reg32 offset="0x0df0" name="VSC_KMD_DBG_ECO_CNTL" variants="A8XX-"/> 1329 <reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="cmd" variants="A6XX-A7XX"> 1330 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/> 1331 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/> 1332 </reg32> 1333 1334 <bitset name="a8xx_bin_size" inline="yes"> 1335 <bitfield name="BINW" low="0" high="9" shr="5" type="uint"/> 1336 <bitfield name="BINH" low="16" high="26" shr="4" type="uint"/> 1337 </bitset> 1338 1339 <reg32 offset="0x0c02" name="VSC_BIN_SIZE" type="a8xx_bin_size" usage="cmd" variants="A8XX"/> 1340 <reg64 offset="0x0c03" name="VSC_SIZE_BASE" type="waddress" usage="cmd"/> 1341 <reg32 offset="0x0c06" name="VSC_EXPANDED_BIN_CNTL" usage="cmd"> 1342 <bitfield name="NX" low="1" high="10" type="uint"/> 1343 <bitfield name="NY" low="11" high="20" type="uint"/> 1344 </reg32> 1345 <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32" usage="cmd"> 1346 <reg32 offset="0x0" name="REG"> 1347 <doc> 1348 Configures the mapping between VSC_PIPE buffer and 1349 bin, X/Y specify the bin index in the horiz/vert 1350 direction (0,0 is upper left, 0,1 is leftmost bin 1351 on second row, and so on). W/H specify the number 1352 of bins assigned to this VSC_PIPE in the horiz/vert 1353 dimension. 1354 </doc> 1355 <bitfield name="X" low="0" high="9" type="uint"/> 1356 <bitfield name="Y" low="10" high="19" type="uint"/> 1357 <bitfield name="W" low="20" high="25" type="uint"/> 1358 <bitfield name="H" low="26" high="31" type="uint"/> 1359 </reg32> 1360 </array> 1361 <!-- 1362 HW binning primitive & draw streams, which enable draws and primitives 1363 within a draw to be skipped in the main tile pass. See: 1364 https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format 1365 1366 Compared to a5xx and earlier, we just program the address of the first 1367 stream and hw adds (pipe_num * VSC_*_STRM_PITCH) 1368 1369 LIMIT is set to PITCH - 64, to make room for a bit of overflow 1370 --> 1371 <reg64 offset="0x0c30" name="VSC_PIPE_DATA_PRIM_BASE" type="waddress" usage="cmd"/> 1372 <reg32 offset="0x0c32" name="VSC_PIPE_DATA_PRIM_STRIDE" usage="cmd"/> 1373 <reg32 offset="0x0c33" name="VSC_PIPE_DATA_PRIM_LENGTH" usage="cmd"/> 1374 <reg64 offset="0x0c34" name="VSC_PIPE_DATA_DRAW_BASE" type="waddress" usage="cmd"/> 1375 <reg32 offset="0x0c36" name="VSC_PIPE_DATA_DRAW_STRIDE" usage="cmd"/> 1376 <reg32 offset="0x0c37" name="VSC_PIPE_DATA_DRAW_LENGTH" usage="cmd"/> 1377 1378 <array offset="0x0c38" name="VSC_CHANNEL_VISIBILITY" stride="1" length="32" usage="cmd"> 1379 <doc> 1380 Seems to be a bitmap of which tiles mapped to the VSC 1381 pipe contain geometry. 1382 1383 I suppose we can connect a maximum of 32 tiles to a 1384 single VSC pipe. 1385 </doc> 1386 <reg32 offset="0x0" name="REG"/> 1387 </array> 1388 1389 <array offset="0x0c58" name="VSC_PIPE_DATA_PRIM_SIZE" stride="1" length="32" variants="A6XX" usage="cmd"> 1390 <doc> 1391 Has the size of data written to corresponding VSC_PRIM_STRM 1392 buffer. 1393 </doc> 1394 <reg32 offset="0x0" name="REG"/> 1395 </array> 1396 1397 <array offset="0x0c78" name="VSC_PIPE_DATA_DRAW_SIZE" stride="1" length="32" variants="A6XX" usage="cmd"> 1398 <doc> 1399 Has the size of data written to corresponding VSC pipe, ie. 1400 same thing that is written out to VSC_SIZE_BASE 1401 </doc> 1402 <reg32 offset="0x0" name="REG"/> 1403 </array> 1404 1405 <reg32 offset="0x0d08" name="VSC_UNKNOWN_0D08" variants="A7XX-" usage="cmd"/> 1406 1407 <reg32 offset="0x0e10" name="UCHE_UNKNOWN_0E10" variants="A7XX" usage="init"/> 1408 <reg32 offset="0x0e10" name="UCHE_VARB_IDLE_TIMEOUT" variants="A8XX-"/> 1409 <reg32 offset="0x0e11" name="UCHE_UNKNOWN_0E11" variants="A7XX" usage="init"/> 1410 <reg32 offset="0x0e11" name="UCHE_CLIENT_PF" variants="A8XX-"/> 1411 <!-- always 0x03200000 ? --> 1412 <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12" variants="A6XX-A7XX" usage="init"/> 1413 <reg32 offset="0x0e15" name="UCHE_DBG_ECO_CNTL_0" variants="A8XX-"/> 1414 <reg32 offset="0x0e16" name="UCHE_HW_DBG_CNTL" variants="A8XX-"/> 1415 1416 <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 --> 1417 <bitset name="a6xx_reg_xy" inline="yes"> 1418 <bitfield name="X" low="0" high="13" type="uint"/> 1419 <bitfield name="Y" low="16" high="29" type="uint"/> 1420 </bitset> 1421 1422 <bitset name="a6xx_gras_cl_cntl" inline="yes"> 1423 <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/> 1424 <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/> 1425 <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/> 1426 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/> 1427 <!-- controls near z clip behavior (set for vulkan) --> 1428 <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/> 1429 <!-- guess based on a3xx and meaning of bits 8 and 9 1430 if the guess is right then this is related to point sprite clipping --> 1431 <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/> 1432 <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/> 1433 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/> 1434 </bitset> 1435 1436 <reg32 offset="0x8000" name="GRAS_CL_CNTL" type="a6xx_gras_cl_cntl" variants="A6XX-A7XX" usage="draw"/> 1437 <reg32 offset="0x8200" name="GRAS_CL_CNTL" type="a6xx_gras_cl_cntl" variants="A8XX-" usage="draw"/> 1438 1439 <bitset name="a6xx_gras_xs_clip_cull_distance" inline="yes"> 1440 <bitfield name="CLIP_MASK" low="0" high="7"/> 1441 <bitfield name="CULL_MASK" low="8" high="15"/> 1442 </bitset> 1443 <reg32 offset="0x8001" name="GRAS_CL_VS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="draw" variants="A6XX-A7XX" /> 1444 <reg32 offset="0x8002" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="draw" variants="A6XX-A7XX" /> 1445 <reg32 offset="0x8003" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="draw" variants="A6XX-A7XX" /> 1446 <reg32 offset="0x8004" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="draw" variants="A6XX-A7XX" /> 1447 1448 <reg32 offset="0x8201" name="GRAS_CL_VS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="draw" variants="A8XX" /> 1449 <reg32 offset="0x8202" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="draw" variants="A8XX" /> 1450 <reg32 offset="0x8203" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="draw" variants="A8XX" /> 1451 <reg32 offset="0x8204" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="draw" variants="A8XX" /> 1452 1453 <bitset name="a6xx_gras_cl_interp_cntl" inline="yes"> 1454 <!-- see also RB_INTERP_CNTL --> 1455 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> 1456 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> 1457 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/> 1458 <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/> 1459 <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/> 1460 <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/> 1461 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> 1462 <bitfield name="UNK10" pos="10" type="boolean" variants="A7XX-"/> 1463 <bitfield name="UNK11" pos="11" type="boolean" variants="A7XX-"/> 1464 </bitset> 1465 1466 <reg32 offset="0x8005" name="GRAS_CL_INTERP_CNTL" type="a6xx_gras_cl_interp_cntl" variants="A6XX-A7XX" usage="draw"/> 1467 <reg32 offset="0x8080" name="GRAS_CL_INTERP_CNTL" type="a6xx_gras_cl_interp_cntl" variants="A8XX-" usage="draw"/> 1468 1469 <bitset name="a6xx_gras_cl_guardband_clip_adj" inline="true"> 1470 <bitfield name="HORZ" low="0" high="8" type="uint"/> 1471 <bitfield name="VERT" low="10" high="18" type="uint"/> 1472 </bitset> 1473 1474 <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" type="a6xx_gras_cl_guardband_clip_adj" variants="A6XX-A7XX" usage="draw"/> 1475 <reg32 offset="0x8205" name="GRAS_CL_GUARDBAND_CLIP_ADJ" type="a6xx_gras_cl_guardband_clip_adj" variants="A8XX-" usage="draw"/> 1476 1477 <!-- the scale/offset is per view, with up to 6 views --> 1478 <bitset name="a6xx_gras_bin_foveat" inline="yes"> 1479 <bitfield name="BINSCALEEN" pos="6" type="boolean"/> 1480 <enum name="a7xx_bin_scale"> 1481 <value value="0" name="NOSCALE"/> 1482 <value value="1" name="SCALE2X"/> 1483 <value value="2" name="SCALE4X"/> 1484 </enum> 1485 <bitfield name="XSCALE_0" low="8" high="9" type="a7xx_bin_scale"/> 1486 <bitfield name="YSCALE_0" low="10" high="11" type="a7xx_bin_scale"/> 1487 <bitfield name="XSCALE_1" low="12" high="13" type="a7xx_bin_scale"/> 1488 <bitfield name="YSCALE_1" low="14" high="15" type="a7xx_bin_scale"/> 1489 <bitfield name="XSCALE_2" low="16" high="17" type="a7xx_bin_scale"/> 1490 <bitfield name="YSCALE_2" low="18" high="19" type="a7xx_bin_scale"/> 1491 <bitfield name="XSCALE_3" low="20" high="21" type="a7xx_bin_scale"/> 1492 <bitfield name="YSCALE_3" low="22" high="23" type="a7xx_bin_scale"/> 1493 <bitfield name="XSCALE_4" low="24" high="25" type="a7xx_bin_scale"/> 1494 <bitfield name="YSCALE_4" low="26" high="27" type="a7xx_bin_scale"/> 1495 <bitfield name="XSCALE_5" low="28" high="29" type="a7xx_bin_scale"/> 1496 <bitfield name="YSCALE_5" low="30" high="31" type="a7xx_bin_scale"/> 1497 </bitset> 1498 1499 <reg32 offset="0x8008" name="GRAS_BIN_FOVEAT" type="a6xx_gras_bin_foveat" variants="A7XX" usage="cmd"/> 1500 <reg32 offset="0x8206" name="GRAS_BIN_FOVEAT" type="a6xx_gras_bin_foveat" variants="A8XX-" usage="cmd"> 1501 <bitfield name="FDM_OFFSET_EN" pos="7" type="boolean"/> 1502 </reg32> 1503 1504 <reg32 offset="0x8009" name="GRAS_BIN_FOVEAT_OFFSET_0" variants="A7XX" usage="cmd"> 1505 <bitfield name="XOFFSET_0" low="0" high="9" shr="2" type="uint"/> 1506 <bitfield name="XOFFSET_1" low="10" high="19" shr="2" type="uint"/> 1507 <bitfield name="XOFFSET_2" low="20" high="29" shr="2" type="uint"/> 1508 </reg32> 1509 <reg32 offset="0x800a" name="GRAS_BIN_FOVEAT_OFFSET_1" variants="A7XX" usage="cmd"> 1510 <bitfield name="XOFFSET_3" low="0" high="9" shr="2" type="uint"/> 1511 <bitfield name="XOFFSET_4" low="10" high="19" shr="2" type="uint"/> 1512 <bitfield name="XOFFSET_5" low="20" high="29" shr="2" type="uint"/> 1513 </reg32> 1514 <reg32 offset="0x800b" name="GRAS_BIN_FOVEAT_OFFSET_2" variants="A7XX" usage="cmd"> 1515 <bitfield name="YOFFSET_0" low="0" high="9" shr="2" type="uint"/> 1516 <bitfield name="YOFFSET_1" low="10" high="19" shr="2" type="uint"/> 1517 <bitfield name="YOFFSET_2" low="20" high="29" shr="2" type="uint"/> 1518 </reg32> 1519 <reg32 offset="0x800c" name="GRAS_BIN_FOVEAT_OFFSET_3" variants="A7XX" usage="cmd"> 1520 <bitfield name="YOFFSET_3" low="0" high="9" shr="2" type="uint"/> 1521 <bitfield name="YOFFSET_4" low="10" high="19" shr="2" type="uint"/> 1522 <bitfield name="YOFFSET_5" low="20" high="29" shr="2" type="uint"/> 1523 </reg32> 1524 1525 <bitset name="a8xx_bin_foveat_xy" inline="yes"> 1526 <bitfield name="XOFFSET" low="0" high="13" type="uint"/> 1527 <bitfield name="YOFFSET" low="16" high="29" type="uint"/> 1528 </bitset> 1529 1530 <array offset="0x8220" name="GRAS_BIN_FOVEAT_XY" stride="1" length="6" variants="A8XX-" usage="cmd"> 1531 <reg32 offset="0" name="OFFSET" type="a8xx_bin_foveat_xy"/> 1532 </array> 1533 1534 <array offset="0x8228" name="GRAS_BIN_FOVEAT_XY_FDM" stride="1" length="6" variants="A8XX-" usage="cmd"> 1535 <reg32 offset="0" name="OFFSET" type="a8xx_bin_foveat_xy"/> 1536 </array> 1537 1538 <!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> --> 1539 1540 <!-- 0x8006-0x800f invalid --> 1541 <array offset="0x8010" name="GRAS_CL_VIEWPORT" stride="6" length="16" variants="A6XX-A7XX" usage="draw"> 1542 <reg32 offset="0" name="XOFFSET" type="float"/> 1543 <reg32 offset="1" name="XSCALE" type="float"/> 1544 <reg32 offset="2" name="YOFFSET" type="float"/> 1545 <reg32 offset="3" name="YSCALE" type="float"/> 1546 <reg32 offset="4" name="ZOFFSET" type="float"/> 1547 <reg32 offset="5" name="ZSCALE" type="float"/> 1548 </array> 1549 1550 <array offset="0x82d0" name="GRAS_CL_VIEWPORT" stride="6" length="16" variants="A8XX-" usage="draw"> 1551 <reg32 offset="0" name="XOFFSET" type="float"/> 1552 <reg32 offset="1" name="XSCALE" type="float"/> 1553 <reg32 offset="2" name="YOFFSET" type="float"/> 1554 <reg32 offset="3" name="YSCALE" type="float"/> 1555 <reg32 offset="4" name="ZOFFSET" type="float"/> 1556 <reg32 offset="5" name="ZSCALE" type="float"/> 1557 </array> 1558 1559 <array offset="0x8070" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" variants="A6XX-A7XX" usage="draw"> 1560 <reg32 offset="0" name="MIN" type="float"/> 1561 <reg32 offset="1" name="MAX" type="float"/> 1562 </array> 1563 <array offset="0x80c0" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" variants="A8XX-" usage="draw"> 1564 <reg32 offset="0" name="MIN" type="float"/> 1565 <reg32 offset="1" name="MAX" type="float"/> 1566 </array> 1567 1568 <bitset name="a6xx_gras_su_cntl" inline="yes"> 1569 <bitfield name="CULL_FRONT" pos="0" type="boolean"/> 1570 <bitfield name="CULL_BACK" pos="1" type="boolean"/> 1571 <bitfield name="FRONT_CW" pos="2" type="boolean"/> 1572 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/> 1573 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/> 1574 <bitfield name="UNK12" pos="12"/> 1575 <bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/> 1576 <bitfield name="UNK15" low="15" high="16"/> 1577 <!-- 1578 On gen1 only MULTIVIEW_ENABLE exists. On gen3 we have 1579 the ability to add the view index to either the RT array 1580 index or the viewport index, and it seems that 1581 MULTIVIEW_ENABLE doesn't do anything, instead we need to 1582 set at least one of RENDERTARGETINDEXINCR or 1583 VIEWPORTINDEXINCR to enable multiview. The blob still 1584 sets MULTIVIEW_ENABLE regardless. 1585 TODO: what about gen2 (a640)? 1586 --> 1587 <bitfield name="MULTIVIEW_ENABLE" pos="17" type="boolean"/> 1588 </bitset> 1589 <reg32 offset="0x8090" name="GRAS_SU_CNTL" type="a6xx_gras_su_cntl" variants="A6XX-A7XX" usage="draw"> 1590 <bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/> 1591 <bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/> 1592 <bitfield name="UNK20" low="20" high="22"/> 1593 </reg32> 1594 <reg32 offset="0x8209" name="GRAS_SU_CNTL" type="a6xx_gras_su_cntl" variants="A8XX-" usage="draw"/> 1595 1596 <!-- Fields moved from GRAS_SU_CNTL on earlier gens: --> 1597 <reg32 offset="0x820c" name="GRAS_SU_STEREO_CNTL" variants="A8XX-" usage="draw"> 1598 <bitfield name="RENDERTARGETINDEXINCR" pos="0" type="boolean"/> 1599 <bitfield name="VIEWPORTINDEXINCR" pos="1" type="boolean"/> 1600 </reg32> 1601 1602 <bitset name="a6xx_gras_su_point_minmax" inline="yes"> 1603 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/> 1604 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/> 1605 </bitset> 1606 1607 <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" type="a6xx_gras_su_point_minmax" variants="A6XX-A7XX" usage="draw"/> 1608 <reg32 offset="0x820a" name="GRAS_SU_POINT_MINMAX" type="a6xx_gras_su_point_minmax" variants="A8XX-" usage="draw"/> 1609 1610 <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" variants="A6XX-A7XX" usage="draw"/> 1611 <reg32 offset="0x820b" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" variants="A8XX-" usage="draw"/> 1612 1613 <bitset name="a6xx_gras_su_depth_cntl" inline="yes"> 1614 <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> 1615 </bitset> 1616 1617 <reg32 offset="0x8114" name="GRAS_SU_DEPTH_CNTL" variants="A6XX-A7XX" type="a6xx_gras_su_depth_cntl" usage="draw"/> 1618 <reg32 offset="0x8086" name="GRAS_SU_DEPTH_CNTL" variants="A8XX-" type="a6xx_gras_su_depth_cntl" usage="draw"/> 1619 1620 <bitset name="a6xx_gras_su_stencil_cntl" inline="yes"> 1621 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 1622 </bitset> 1623 1624 <reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" type="a6xx_gras_su_stencil_cntl" variants="A6XX-A7XX" usage="draw"/> 1625 <reg32 offset="0x8087" name="GRAS_SU_STENCIL_CNTL" type="a6xx_gras_su_stencil_cntl" variants="A8XX-" usage="draw"/> 1626 1627 <bitset name="a6xx_gras_su_render_cntl" inline="yes"> 1628 <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 1629 </bitset> 1630 1631 <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" type="a6xx_gras_su_render_cntl" variants="A7XX" usage="draw"/> 1632 <reg32 offset="0x8088" name="GRAS_SU_RENDER_CNTL" type="a6xx_gras_su_render_cntl" variants="A8XX-" usage="draw"/> 1633 1634 <!-- 0x8093 invalid --> 1635 <bitset name="a6xx_depth_plane_cntl" inline="yes"> 1636 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/> 1637 </bitset> 1638 1639 <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" variants="A6XX-A7XX" usage="draw"/> 1640 <reg32 offset="0x8089" name="GRAS_SU_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" variants="A8XX-" usage="draw"/> 1641 1642 <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" variants="A6XX-A7XX" usage="draw"/> 1643 <reg32 offset="0x808a" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" variants="A8XX-" usage="draw"/> 1644 1645 <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" variants="A6XX-A7XX" usage="draw"/> 1646 <reg32 offset="0x808b" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" variants="A8XX-" usage="draw"/> 1647 1648 <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" variants="A6XX-A7XX" usage="draw"/> 1649 <reg32 offset="0x808c" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" variants="A8XX-" usage="draw"/> 1650 1651 <bitset name="a6xx_depth_buffer_info" inline="yes"> 1652 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 1653 <bitfield name="READ_ONLY" pos="3" type="boolean"/> 1654 </bitset> 1655 1656 <!-- duplicates RB_DEPTH_BUFFER_INFO: --> 1657 <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A6XX-A7XX" usage="draw"/> 1658 <reg32 offset="0x808d" name="GRAS_SU_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A8XX-" usage="draw"/> 1659 1660 <bitset name="a6xx_gras_su_conservative_ras_cntl" inline="yes"> 1661 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 1662 <enum name="a6xx_shift_amount"> 1663 <value value="0" name="NO_SHIFT"/> 1664 <value value="1" name="HALF_PIXEL_SHIFT"/> 1665 <value value="2" name="FULL_PIXEL_SHIFT"/> 1666 </enum> 1667 <bitfield name="SHIFTAMOUNT" low="1" high="2" type="a6xx_shift_amount"/> 1668 <bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/> 1669 <bitfield name="UNK4" low="4" high="5"/> 1670 </bitset> 1671 1672 <reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_gras_su_conservative_ras_cntl" variants="A6XX-A7XX" usage="cmd"/> 1673 <reg32 offset="0x820d" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_gras_su_conservative_ras_cntl" variants="A8XX-" usage="cmd"/> 1674 1675 <reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL"> 1676 <bitfield name="UNK0" pos="0" type="boolean"/> 1677 <bitfield name="LINELENGTHEN" pos="1" type="boolean"/> 1678 </reg32> 1679 1680 <bitset name="a6xx_gras_us_xs_siv_cntl" inline="yes"> 1681 <bitfield name="WRITES_LAYER" pos="0" type="boolean"/> 1682 <bitfield name="WRITES_VIEW" pos="1" type="boolean"/> 1683 </bitset> 1684 <reg32 offset="0x809b" name="GRAS_SU_VS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="draw"/> 1685 <reg32 offset="0x809c" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="draw"/> 1686 <reg32 offset="0x809d" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="draw"/> 1687 1688 <reg32 offset="0x820e" name="GRAS_SU_VS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A8XX" usage="draw"/> 1689 <reg32 offset="0x820f" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A8XX" usage="draw"/> 1690 <reg32 offset="0x8210" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A8XX" usage="draw"/> 1691 1692 <bitset name="a6xx_rast_cntl" inline="yes"> 1693 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 1694 </bitset> 1695 1696 <reg32 offset="0x8211" name="GRAS_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX-" usage="draw"/> 1697 1698 <enum name="a6xx_sequenced_thread_dist"> 1699 <value value="0x0" name="DIST_SCREEN_COORD"/> 1700 <value value="0x1" name="DIST_ALL_TO_RB0"/> 1701 </enum> 1702 1703 <enum name="a6xx_single_prim_mode"> 1704 <value value="0x0" name="NO_FLUSH"/> 1705 <doc> 1706 In addition to FLUSH_PER_OVERLAP, guarantee that UCHE 1707 and CCU don't get out of sync when fetching the previous 1708 value for the current pixel. With NO_FLUSH, there's the 1709 possibility that the flags for the current pixel are 1710 flushed before the data or vice-versa, leading to 1711 texture fetches via UCHE getting out of sync values. 1712 This mode should eliminate that. It's used in bypass 1713 mode for coherent blending 1714 (GL_KHR_blend_equation_advanced_coherent) as well as 1715 non-coherent blending. 1716 </doc> 1717 <value value="0x1" name="FLUSH_PER_OVERLAP_AND_OVERWRITE"/> 1718 <doc> 1719 Invalidate UCHE and wait for any pending work to finish 1720 if there was possibly an overlapping primitive prior to 1721 the current one. This is similar to a combination of 1722 GRAS_SC_CONTROL::INJECT_L2_INVALIDATE_EVENT and 1723 WAIT_RB_IDLE_ALL_TRI on a3xx. It's used in GMEM mode for 1724 coherent blending 1725 (GL_KHR_blend_equation_advanced_coherent). 1726 </doc> 1727 <value value="0x3" name="FLUSH_PER_OVERLAP"/> 1728 </enum> 1729 1730 <!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE --> 1731 <enum name="a6xx_raster_mode"> 1732 <value value="0x0" name="TYPE_TILED"/> 1733 <value value="0x1" name="TYPE_WRITER"/> 1734 </enum> 1735 1736 <!-- I'm guessing this is the same as a3xx --> 1737 <enum name="a6xx_raster_direction"> 1738 <value value="0x0" name="LR_TB"/> 1739 <value value="0x1" name="RL_TB"/> 1740 <value value="0x2" name="LR_BT"/> 1741 <value value="0x3" name="RB_BT"/> 1742 </enum> 1743 1744 <bitset name="a6xx_gras_sc_cntl" inline="yes"> 1745 <bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/> 1746 <bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/> 1747 <bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/> 1748 <bitfield name="SEQUENCED_THREAD_DISTRIBUTION" pos="8" type="a6xx_sequenced_thread_dist"/> 1749 <!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set --> 1750 <bitfield name="UNK9" pos="9" type="boolean"/> 1751 <bitfield name="ROTATION" low="10" high="11" type="uint"/> 1752 <bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/> 1753 </bitset> 1754 1755 <reg32 offset="0x80a0" name="GRAS_SC_CNTL" type="a6xx_gras_sc_cntl" variants="A6XX-A7XX" usage="draw"> 1756 <bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2" variants="A6XX-A7XX"/> 1757 </reg32> 1758 <reg32 offset="0x8230" name="GRAS_SC_CNTL" type="a6xx_gras_sc_cntl" variants="A8XX-" usage="draw"/> 1759 1760 <enum name="a6xx_render_mode"> 1761 <value value="0x0" name="RENDERING_PASS"/> 1762 <value value="0x1" name="BINNING_PASS"/> 1763 </enum> 1764 1765 <enum name="a6xx_buffers_location"> 1766 <value value="0" name="BUFFERS_IN_GMEM"/> 1767 <value value="3" name="BUFFERS_IN_SYSMEM"/> 1768 </enum> 1769 1770 <enum name="a6xx_lrz_feedback_mask"> 1771 <value value="0x0" name="LRZ_FEEDBACK_NONE"/> 1772 <value value="0x1" name="LRZ_FEEDBACK_EARLY_Z"/> 1773 <value value="0x2" name="LRZ_FEEDBACK_EARLY_Z_LATE_Z"/> 1774 <!-- We don't have a flag type and this flags combination is often used --> 1775 <value value="0x3" name="LRZ_FEEDBACK_EARLY_Z_OR_EARLY_Z_LATE_Z"/> 1776 <value value="0x4" name="LRZ_FEEDBACK_LATE_Z"/> 1777 </enum> 1778 1779 <bitset name="a6xx_bin_cntl" inline="yes"> 1780 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1781 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1782 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> 1783 <doc>Disable LRZ feedback writes</doc> 1784 <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/> 1785 <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location" variants="A6XX"/> 1786 <doc> 1787 Allows draws that don't have GRAS_LRZ_CNTL.LRZ_WRITE but have 1788 GRAS_LRZ_CNTL.ENABLE to contribute to LRZ during RENDERING pass. 1789 In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered. 1790 </doc> 1791 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/> 1792 <bitfield name="FORCE_LRZ_DIS" pos="27" type="boolean"/> 1793 </bitset> 1794 1795 <reg32 offset="0x80a1" name="GRAS_SC_BIN_CNTL" type="a6xx_bin_cntl" variants="A6XX-A7XX" usage="cmd"/> 1796 1797 <!-- Common fields for RB_CNTL and GRAS_SC_BIN_CNTL --> 1798 <bitset name="a8xx_bin_cntl" inline="yes"> 1799 <bitfield name="BINW" low="0" high="9" shr="5" type="uint"/> 1800 <bitfield name="BINH" low="16" high="26" shr="4" type="uint"/> 1801 <bitfield name="RENDER_MODE" low="11" high="13" type="a6xx_render_mode"/> 1802 <doc> 1803 Allows draws that don't have GRAS_LRZ_CNTL.LRZ_WRITE but have 1804 GRAS_LRZ_CNTL.ENABLE to contribute to LRZ during RENDERING pass. 1805 In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered. 1806 </doc> 1807 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="28" high="30" type="a6xx_lrz_feedback_mask"/> 1808 <doc>Disable LRZ feedback writes</doc> 1809 <bitfield name="FORCE_LRZ_WRITE_DIS" pos="31" type="boolean"/> 1810 </bitset> 1811 1812 <reg32 offset="0x8231" name="GRAS_SC_BIN_CNTL" type="a8xx_bin_cntl" variants="A8XX-" usage="cmd"> 1813 <bitfield name="CONS_VIS_IN_BINNING" pos="10" type="boolean"/> 1814 <bitfield name="FORCE_BI_DIR_LRZ_DISABLE" pos="14" type="boolean"/> 1815 <bitfield name="FORCE_LRZ_DIS" pos="15" type="boolean"/> 1816 <bitfield name="BIN_VRS_DIS" pos="27" type="boolean"/> 1817 </reg32> 1818 1819 <bitset name="a6xx_gras_sc_ras_msaa_cntl" inline="yes"> 1820 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1821 <bitfield name="UNK2" pos="2"/> 1822 <bitfield name="UNK3" pos="3"/> 1823 </bitset> 1824 1825 <reg32 offset="0x80a2" name="GRAS_SC_RAS_MSAA_CNTL" type="a6xx_gras_sc_ras_msaa_cntl" variants="A6XX-A7XX" usage="draw"/> 1826 <reg32 offset="0x8232" name="GRAS_SC_RAS_MSAA_CNTL" type="a6xx_gras_sc_ras_msaa_cntl" variants="A8XX-" usage="draw"/> 1827 1828 <bitset name="a6xx_gras_sc_dest_msaa_cntl" inline="yes"> 1829 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1830 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 1831 </bitset> 1832 1833 <reg32 offset="0x80a3" name="GRAS_SC_DEST_MSAA_CNTL" type="a6xx_gras_sc_dest_msaa_cntl" variants="A6XX-A7XX" usage="draw"/> 1834 <reg32 offset="0x8233" name="GRAS_SC_DEST_MSAA_CNTL" type="a6xx_gras_sc_dest_msaa_cntl" variants="A8XX-" usage="draw"/> 1835 1836 <bitset name="a6xx_msaa_sample_pos_cntl" inline="yes"> 1837 <bitfield name="UNK0" pos="0"/> 1838 <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/> 1839 </bitset> 1840 1841 <bitset name="a6xx_programmable_msaa_pos" inline="yes"> 1842 <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/> 1843 <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/> 1844 <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/> 1845 <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/> 1846 <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/> 1847 <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/> 1848 <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/> 1849 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/> 1850 </bitset> 1851 1852 <reg32 offset="0x80a4" name="GRAS_SC_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" variants="A6XX-A7XX" usage="draw"/> 1853 <reg32 offset="0x80a5" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" variants="A6XX-A7XX" usage="draw"/> 1854 <reg32 offset="0x80a6" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" variants="A6XX-A7XX" usage="draw"/> 1855 1856 <reg32 offset="0x8237" name="GRAS_SC_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" variants="A8XX-" usage="draw"/> 1857 <reg32 offset="0x8238" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="draw"/> 1858 <reg32 offset="0x8239" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="draw"/> 1859 <reg32 offset="0x823a" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_2" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="draw"/> 1860 <reg32 offset="0x823b" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_3" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="draw"/> 1861 1862 <reg32 offset="0x80a7" name="GRAS_ROTATION_CNTL" variants="A7XX" usage="cmd"/> 1863 <reg32 offset="0x8207" name="GRAS_ROTATION_CNTL" variants="A8XX-" usage="cmd"/> 1864 1865 <bitset name="a6xx_screen_scissor_cntl" inline="yes"> 1866 <bitfield name="SCISSOR_DISABLE" pos="0" type="boolean"/> 1867 </bitset> 1868 1869 <reg32 offset="0x80af" name="GRAS_SC_SCREEN_SCISSOR_CNTL" type="a6xx_screen_scissor_cntl" variants="A6XX-A7XX" pos="0" usage="cmd"/> 1870 <reg32 offset="0x8234" name="GRAS_SC_SCREEN_SCISSOR_CNTL" type="a6xx_screen_scissor_cntl" variants="A8XX-" pos="0" usage="cmd"/> 1871 1872 <bitset name="a6xx_scissor_xy" inline="yes"> 1873 <bitfield name="X" low="0" high="15" type="uint"/> 1874 <bitfield name="Y" low="16" high="31" type="uint"/> 1875 </bitset> 1876 1877 <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" variants="A6XX-A7XX" usage="draw"> 1878 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1879 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1880 </array> 1881 1882 <array offset="0x8240" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" variants="A8XX-" usage="draw"> 1883 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1884 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1885 </array> 1886 1887 <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" variants="A6XX-A7XX" usage="draw"> 1888 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1889 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1890 </array> 1891 <array offset="0x8270" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" variants="A8XX-" usage="draw"> 1892 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1893 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1894 </array> 1895 1896 <reg32 offset="0x829f" name="GRAS_SC_WINDOW_INV_SCISSOR_CNTL" variants="A8XX-"> 1897 <bitfield name="INCLUSION" pos="0" type="boolean"/> <!-- if not set, EXCLUSION --> 1898 <bitfield name="VP0_INV_SCISSOR_0_EN" pos="4" type="boolean"/> 1899 <bitfield name="VP0_INV_SCISSOR_1_EN" pos="5" type="boolean"/> 1900 <bitfield name="VP1_INV_SCISSOR_0_EN" pos="6" type="boolean"/> 1901 <bitfield name="VP1_INV_SCISSOR_1_EN" pos="7" type="boolean"/> 1902 <bitfield name="VP2_INV_SCISSOR_0_EN" pos="8" type="boolean"/> 1903 <bitfield name="VP2_INV_SCISSOR_1_EN" pos="9" type="boolean"/> 1904 <bitfield name="VP3_INV_SCISSOR_0_EN" pos="10" type="boolean"/> 1905 <bitfield name="VP3_INV_SCISSOR_1_EN" pos="11" type="boolean"/> 1906 <bitfield name="VP4_INV_SCISSOR_0_EN" pos="12" type="boolean"/> 1907 <bitfield name="VP4_INV_SCISSOR_1_EN" pos="13" type="boolean"/> 1908 <bitfield name="VP5_INV_SCISSOR_0_EN" pos="14" type="boolean"/> 1909 <bitfield name="VP5_INV_SCISSOR_1_EN" pos="15" type="boolean"/> 1910 </reg32> 1911 1912 <array offset="0x82a0" name="GRAS_SC_WINDOW_VP" stride="4" length="6" variants="A8XX-"> 1913 <reg32 offset="0" name="INV_SCISSOR_0_TL" type="a6xx_scissor_xy"/> 1914 <reg32 offset="1" name="INV_SCISSOR_0_BR" type="a6xx_scissor_xy"/> 1915 <reg32 offset="2" name="INV_SCISSOR_1_TL" type="a6xx_scissor_xy"/> 1916 <reg32 offset="3" name="INV_SCISSOR_1_BR" type="a6xx_scissor_xy"/> 1917 </array> 1918 1919 <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="draw"/> 1920 <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="draw"/> 1921 1922 <reg32 offset="0x8235" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" variants="A8XX-" usage="draw"/> 1923 <reg32 offset="0x8236" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" variants="A8XX-" usage="draw"/> 1924 1925 <enum name="a6xx_fsr_combiner"> 1926 <value value="0" name="FSR_COMBINER_OP_KEEP"/> 1927 <value value="1" name="FSR_COMBINER_OP_REPLACE"/> 1928 <value value="2" name="FSR_COMBINER_OP_MIN"/> 1929 <value value="3" name="FSR_COMBINER_OP_MAX"/> 1930 <value value="4" name="FSR_COMBINER_OP_MUL"/> 1931 </enum> 1932 1933 <enum name="a6xx_fsr_combiner_clamp_mode"> 1934 <value value="0" name="FSR_COMBINER_CLAMP_4x4"/> 1935 <value value="1" name="FSR_COMBINER_CLAMP_2x2"/> 1936 <!-- gen8 and later, reserved on earlier gens: --> 1937 <value value="2" name="FSR_COMBINER_CLAMP_16_SAMP"/> 1938 </enum> 1939 1940 <bitset name="a6xx_gras_vrs_config" inline="yes"> 1941 <bitfield name="PIPELINE_FSR_ENABLE" pos="0" type="boolean"/> 1942 <bitfield name="FRAG_SIZE_X" low="1" high="2" type="uint"/> 1943 <bitfield name="FRAG_SIZE_Y" low="3" high="4" type="uint"/> 1944 <bitfield name="COMBINER_OP_1" low="5" high="7" type="a6xx_fsr_combiner"/> 1945 <bitfield name="COMBINER_OP_2" low="8" high="10" type="a6xx_fsr_combiner"/> 1946 <bitfield name="COMBINER_CLAMP_MODE" low="11" high="12" type="a6xx_fsr_combiner_clamp_mode"/> 1947 <bitfield name="ATTACHMENT_FSR_ENABLE" pos="13" type="boolean"/> 1948 <bitfield name="PRIMITIVE_FSR_ENABLE" pos="20" type="boolean"/> 1949 </bitset> 1950 1951 <reg32 offset="0x80f4" name="GRAS_VRS_CONFIG" type="a6xx_gras_vrs_config" variants="A7XX" usage="draw"> 1952 <bitfield name="QUALITY_BUFFER_SHIFT_X" low="14" high="15" type="uint"/> 1953 <bitfield name="QUALITY_BUFFER_SHIFT_Y" low="16" high="17" type="uint"/> 1954 </reg32> 1955 <reg32 offset="0x8208" name="GRAS_VRS_CONFIG" type="a6xx_gras_vrs_config" variants="A8XX-" usage="draw"/> 1956 1957 <bitset name="a6xx_gras_quality_buffer_info" inline="yes"> 1958 <bitfield name="LAYERED" pos="0" type="boolean"/> 1959 <bitfield name="TILE_MODE" low="1" high="2" type="a6xx_tile_mode"/> 1960 </bitset> 1961 1962 <reg32 offset="0x80f5" name="GRAS_QUALITY_BUFFER_INFO" type="a6xx_gras_quality_buffer_info" variants="A7XX" usage="draw"/> 1963 <reg32 offset="0x808e" name="GRAS_QUALITY_BUFFER_INFO" type="a6xx_gras_quality_buffer_info" variants="A8XX-" usage="draw"> 1964 <bitfield name="QUALITY_BUFFER_SHIFT_X" low="4" high="5" type="uint"/> 1965 <bitfield name="QUALITY_BUFFER_SHIFT_Y" low="6" high="7" type="uint"/> 1966 </reg32> 1967 1968 <bitset name="a6xx_gras_quality_buffer_dimension" inline="yes"> 1969 <bitfield name="WIDTH" low="0" high="15" type="uint"/> 1970 <bitfield name="HEIGHT" low="16" high="31" type="uint"/> 1971 </bitset> 1972 1973 <reg32 offset="0x80f6" name="GRAS_QUALITY_BUFFER_DIMENSION" type="a6xx_gras_quality_buffer_dimension" variants="A7XX" usage="draw"/> 1974 <reg32 offset="0x808f" name="GRAS_QUALITY_BUFFER_DIMENSION" type="a6xx_gras_quality_buffer_dimension" variants="A8XX-" usage="draw"/> 1975 1976 <reg64 offset="0x80f8" name="GRAS_QUALITY_BUFFER_BASE" variants="A7XX" type="waddress" usage="draw"/> 1977 <reg64 offset="0x8090" name="GRAS_QUALITY_BUFFER_BASE" variants="A8XX-" type="waddress" usage="draw"/> 1978 1979 <bitset name="a6xx_gras_quality_buffer_pitch" inline="yes"> 1980 <bitfield name="PITCH" shr="6" low="0" high="7" type="uint"/> 1981 <bitfield name="ARRAY_PITCH" shr="6" low="10" high="28" type="uint"/> 1982 </bitset> 1983 1984 <reg32 offset="0x80fa" name="GRAS_QUALITY_BUFFER_PITCH" type="a6xx_gras_quality_buffer_pitch" variants="A7XX" usage="draw"/> 1985 <reg32 offset="0x8092" name="GRAS_QUALITY_BUFFER_PITCH" type="a6xx_gras_quality_buffer_pitch" variants="A8XX-" usage="draw"/> 1986 1987 <enum name="a6xx_lrz_dir_status"> 1988 <value value="0x1" name="LRZ_DIR_LE"/> 1989 <value value="0x2" name="LRZ_DIR_GE"/> 1990 <value value="0x3" name="LRZ_DIR_INVALID"/> 1991 </enum> 1992 1993 <bitset name="a6xx_gras_lrz_cntl" inline="yes"> 1994 <bitfield name="ENABLE" pos="0" type="boolean"/> 1995 <doc>LRZ write also disabled for blend/etc.</doc> 1996 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/> 1997 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc> 1998 <bitfield name="GREATER" pos="2" type="boolean"/> 1999 <doc> 2000 Clears the LRZ block being touched to: 2001 - 0.0 if GREATER 2002 - 1.0 if LESS 2003 </doc> 2004 <!-- set when depth-test + depth-write enabled --> 2005 <bitfield name="Z_WRITE_ENABLE" pos="4" type="boolean"/> 2006 <bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/> 2007 <bitfield name="DIR" low="6" high="7" type="a6xx_lrz_dir_status"/> 2008 <doc> 2009 If DISABLE_ON_WRONG_DIR enabled - write new LRZ direction into 2010 buffer, in case of mismatched direction writes 0 (disables LRZ). 2011 </doc> 2012 <bitfield name="DIR_WRITE" pos="8" type="boolean"/> 2013 <doc> 2014 Disable LRZ based on previous direction and the current one. 2015 If DIR_WRITE is not enabled - there is no write to direction buffer. 2016 </doc> 2017 <bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/> 2018 </bitset> 2019 2020 <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="draw" variants="A6XX"> 2021 <bitfield name="FC_ENABLE" pos="3" type="boolean" variants="A6XX"/> 2022 <bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean" variants="A6XX"/> 2023 </reg32> 2024 <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="draw" variants="A7XX"/> 2025 <reg32 offset="0x8212" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="draw" variants="A8XX-"/> 2026 2027 <bitset name="a7xx_gras_lrz_cb_cntl" inline="yes"> 2028 <doc> 2029 The total size of the LRZ image array (not including 2030 fast clear buffer), used as a stride for double 2031 buffering used with concurrent binning. 2032 </doc> 2033 <bitfield name="DOUBLE_BUFFER_PITCH" low="8" high="31" shr="8"/> 2034 </bitset> 2035 <reg32 offset="0x8007" name="GRAS_LRZ_CB_CNTL" type="a7xx_gras_lrz_cb_cntl" variants="A7XX" usage="draw"/> 2036 <reg32 offset="0x8101" name="GRAS_LRZ_CB_CNTL" type="a7xx_gras_lrz_cb_cntl" variants="A8XX-" usage="draw"/> 2037 2038 <enum name="a6xx_fragcoord_sample_mode"> 2039 <value value="0" name="FRAGCOORD_CENTER"/> 2040 <value value="3" name="FRAGCOORD_SAMPLE"/> 2041 </enum> 2042 2043 <bitset name="a6xx_gras_lrz_ps_input_cntl" inline="yes"> 2044 <bitfield name="SAMPLEID" pos="0" type="boolean"/> 2045 <bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/> 2046 </bitset> 2047 2048 <reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" type="a6xx_gras_lrz_ps_input_cntl" usage="draw" variants="A6XX-A7XX"/> 2049 <reg32 offset="0x8102" name="GRAS_LRZ_PS_INPUT_CNTL" type="a6xx_gras_lrz_ps_input_cntl" usage="draw" variants="A8XX-"/> 2050 2051 <bitset name="a6xx_gras_lrz_mrt_buffer_info_0" inline="yes"> 2052 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2053 </bitset> 2054 2055 <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUFFER_INFO_0" type="a6xx_gras_lrz_mrt_buffer_info_0" usage="draw" variants="A6XX-A7XX"/> 2056 <reg32 offset="0x8103" name="GRAS_LRZ_MRT_BUFFER_INFO_0" type="a6xx_gras_lrz_mrt_buffer_info_0" usage="draw" variants="A8XX-"/> 2057 2058 <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="draw" variants="A6XX-A7XX"/> 2059 <reg64 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="draw" variants="A8XX-"/> 2060 2061 <bitset name="a6xx_gras_lrz_buffer_pitch" inline="yes"> 2062 <bitfield name="PITCH" low="0" high="7" shr="6" type="uint"/> 2063 <bitfield name="ARRAY_PITCH" low="10" high="28" shr="8" type="uint"/> 2064 </bitset> 2065 2066 <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" type="a6xx_gras_lrz_buffer_pitch" usage="draw" variants="A6XX-A7XX"/> 2067 <reg32 offset="0x8108" name="GRAS_LRZ_BUFFER_PITCH" type="a6xx_gras_lrz_buffer_pitch" usage="draw" variants="A8XX-"/> 2068 2069 <reg32 offset="0x810e" name="GRAS_LRZ_BUFFER_STRIDE" usage="draw" low="0" high="16" shr="12" variants="A8XX-"/> 2070 2071 <!-- 2072 The LRZ "fast clear" buffer is initialized to zero's by blob, and 2073 read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set. It appears 2074 to store 1b/block. It appears that '0' means block has original 2075 depth clear value, and '1' means that the corresponding block in 2076 LRZ has been modified. Ignoring alignment/padding, the size is 2077 given by the formula: 2078 2079 // calculate LRZ size from depth size: 2080 if (nr_samples == 4) { 2081 width *= 2; 2082 height *= 2; 2083 } else if (nr_samples == 2) { 2084 height *= 2; 2085 } 2086 2087 lrz_width = div_round_up(width, 8); 2088 lrz_heigh = div_round_up(height, 8); 2089 2090 // calculate # of blocks: 2091 nblocksx = div_round_up(lrz_width, 16); 2092 nblocksy = div_round_up(lrz_height, 4); 2093 2094 // fast-clear buffer is 1bit/block: 2095 fc_sz = div_round_up(nblocksx * nblocksy, 8); 2096 2097 In practice the blob seems to switch off FC_ENABLE once the size 2098 increases beyond 1 page. Not sure if that is an actual limit or 2099 not. 2100 --> 2101 <reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress" usage="resolve"/> 2102 <reg32 offset="0x8109" name="GRAS_LRZ_PS_SAMPLEFREQ_CNTL" usage="draw"> 2103 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> 2104 </reg32> 2105 <!-- 2106 LRZ buffer represents a single array layer + mip level, and there is 2107 a single buffer per depth image. Thus to reuse LRZ between renderpasses 2108 it is necessary to track the depth view used in the past renderpass, which 2109 GRAS_LRZ_VIEW_INFO is for. 2110 GRAS_LRZ_CNTL checks if current value of GRAS_LRZ_VIEW_INFO is equal to 2111 the value stored in the LRZ buffer, if not - LRZ is disabled. 2112 --> 2113 <reg32 offset="0x810a" name="GRAS_LRZ_VIEW_INFO" usage="cmd"> 2114 <bitfield name="BASE_LAYER" low="0" high="10" type="uint"/> 2115 <bitfield name="LAYER_COUNT" low="16" high="26" type="uint"/> 2116 <bitfield name="BASE_MIP_LEVEL" low="28" high="31" type="uint"/> 2117 </reg32> 2118 2119 <reg32 offset="0x810b" name="GRAS_LRZ_CNTL2" variants="A7XX-" usage="draw"> 2120 <bitfield name="DISABLE_ON_WRONG_DIR" pos="0" type="boolean"/> 2121 <bitfield name="FC_ENABLE" pos="1" type="boolean"/> 2122 </reg32> 2123 2124 <!-- 0x810c-0x810f invalid --> 2125 2126 <reg32 offset="0x8110" name="GRAS_LRZ_BUFFER_SLICE_PITCH" low="8" high="31" shr="8" type="uint" variants="A8XX-"/> 2127 2128 <reg32 offset="0x8110" name="GRAS_MODE_CNTL" low="0" high="1" variants="A6XX-A7XX" usage="cmd"/> 2129 <reg32 offset="0x8213" name="GRAS_MODE_CNTL" low="0" high="1" variants="A8XX-" usage="cmd"/> 2130 2131 <!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR --> 2132 <reg32 offset="0x8111" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A7XX"/> 2133 <reg32 offset="0x810d" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A8XX-"/> 2134 2135 <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A7XX" usage="draw"/> 2136 <reg32 offset="0x810f" name="GRAS_LRZ_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A8XX" usage="draw"/> 2137 2138 <doc>LUT used to convert quality buffer values to HW shading rate values. An array of 4-bit values.</doc> 2139 <array offset="0x8120" name="GRAS_LRZ_QUALITY_LOOKUP_TABLE" variants="A7XX" stride="1" length="2"/> 2140 <array offset="0x8130" name="GRAS_LRZ_QUALITY_LOOKUP_TABLE" variants="A8XX-" stride="1" length="2"/> 2141 2142 <reg32 offset="0x810c" name="GRAS_LRZ_COLOR_COMP_MASK" variants="A8XX-"> 2143 <bitfield name="MRT0" low="0" high="3"/> 2144 <bitfield name="MRT1" low="4" high="7"/> 2145 <bitfield name="MRT2" low="8" high="11"/> 2146 <bitfield name="MRT3" low="12" high="15"/> 2147 <bitfield name="MRT4" low="16" high="19"/> 2148 <bitfield name="MRT5" low="20" high="23"/> 2149 <bitfield name="MRT6" low="24" high="27"/> 2150 <bitfield name="MRT7" low="28" high="31"/> 2151 </reg32> 2152 2153 <enum name="a6xx_rotation"> 2154 <value value="0x0" name="ROTATE_0"/> 2155 <value value="0x1" name="ROTATE_90"/> 2156 <value value="0x2" name="ROTATE_180"/> 2157 <value value="0x3" name="ROTATE_270"/> 2158 <value value="0x4" name="ROTATE_HFLIP"/> 2159 <value value="0x5" name="ROTATE_VFLIP"/> 2160 </enum> 2161 2162 <bitset name="a6xx_a2d_blt_cntl" inline="yes"> 2163 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/> 2164 <bitfield name="OVERWRITEEN" pos="3" type="boolean"/> 2165 <bitfield name="UNK4" low="4" high="6"/> 2166 <bitfield name="SOLID_COLOR" pos="7" type="boolean"/> 2167 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/> 2168 <bitfield name="SCISSOR" pos="16" type="boolean"/> 2169 <bitfield name="UNK17" low="17" high="18"/> 2170 <!-- required when blitting D24S8/D24X8 --> 2171 <bitfield name="D24S8" pos="19" type="boolean"/> 2172 <!-- some sort of channel mask, disabled channels are set to zero ? --> 2173 <bitfield name="MASK" low="20" high="23"/> 2174 <bitfield name="IFMT" low="24" high="26" type="a6xx_2d_ifmt"/> 2175 <bitfield name="UNK27" pos="27" type="boolean"/> 2176 <bitfield name="UNK28" pos="28" type="boolean"/> 2177 <bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/> 2178 <bitfield name="COPY" pos="30" type="boolean" variants="A7XX-"/> 2179 </bitset> 2180 2181 <reg32 offset="0x8400" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_blt_cntl" variants="A6XX-A7XX" usage="blit"/> 2182 <!-- note: the low 8 bits for src coords are valid, probably fixed point 2183 it would be a bit weird though, since we subtract 1 from BR coords 2184 apparently signed, gallium driver uses negative coords and it works? 2185 --> 2186 <reg32 offset="0x8401" name="GRAS_A2D_SRC_XMIN" low="8" high="24" type="int" variants="A6XX-A7XX" usage="blit"/> 2187 <reg32 offset="0x8402" name="GRAS_A2D_SRC_XMAX" low="8" high="24" type="int" variants="A6XX-A7XX" usage="blit"/> 2188 <reg32 offset="0x8403" name="GRAS_A2D_SRC_YMIN" low="8" high="24" type="int" variants="A6XX-A7XX" usage="blit"/> 2189 <reg32 offset="0x8404" name="GRAS_A2D_SRC_YMAX" low="8" high="24" type="int" variants="A6XX-A7XX" usage="blit"/> 2190 <reg32 offset="0x8405" name="GRAS_A2D_DEST_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="blit"/> 2191 <reg32 offset="0x8406" name="GRAS_A2D_DEST_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="blit"/> 2192 <reg32 offset="0x8407" name="GRAS_A2D_UNKNOWN_8407" low="0" high="31" variants="A6XX" usage="blit"/> 2193 <reg32 offset="0x8408" name="GRAS_A2D_UNKNOWN_8408" low="0" high="31" variants="A6XX" usage="blit"/> 2194 <reg32 offset="0x8409" name="GRAS_A2D_UNKNOWN_8409" low="0" high="31" variants="A6XX" usage="blit"/> 2195 <reg32 offset="0x840a" name="GRAS_A2D_SCISSOR_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="blit"/> 2196 <reg32 offset="0x840b" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="blit"/> 2197 2198 <reg32 offset="0x8500" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_blt_cntl" variants="A8XX-" usage="blit"/> 2199 <reg32 offset="0x8501" name="GRAS_A2D_SRC_XMIN" low="8" high="24" type="int" variants="A8XX-" usage="blit"/> 2200 <reg32 offset="0x8502" name="GRAS_A2D_SRC_XMAX" low="8" high="24" type="int" variants="A8XX-" usage="blit"/> 2201 <reg32 offset="0x8503" name="GRAS_A2D_SRC_YMIN" low="8" high="24" type="int" variants="A8XX-" usage="blit"/> 2202 <reg32 offset="0x8504" name="GRAS_A2D_SRC_YMAX" low="8" high="24" type="int" variants="A8XX-" usage="blit"/> 2203 <reg32 offset="0x8505" name="GRAS_A2D_DEST_TL" type="a6xx_reg_xy" variants="A8XX-" usage="blit"/> 2204 <reg32 offset="0x8506" name="GRAS_A2D_DEST_BR" type="a6xx_reg_xy" variants="A8XX-" usage="blit"/> 2205 <reg32 offset="0x8507" name="GRAS_A2D_SCISSOR_TL" type="a6xx_reg_xy" variants="A8XX-" usage="blit"/> 2206 <reg32 offset="0x8508" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" variants="A8XX-" usage="blit"/> 2207 2208 <!-- always 0x880 ? (and 0 in a640/a650 traces?) --> 2209 <reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="init" variants="A6XX-A7XX"> 2210 <bitfield name="UNK7" pos="7" type="boolean"/> 2211 <bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/> 2212 </reg32> 2213 <reg32 offset="0x8600" name="GRAS_TSEFE_DBG_ECO_CNTL" variants="A8XX-"/> 2214 <reg32 offset="0x8702" name="GRAS_DBG_ECO_CNTL" variants="A8XX"/> 2215 <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" variants="A6XX"/> 2216 <reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX"/> 2217 <reg32 offset="0x8700" name="GRAS_NC_MODE_CNTL" variants="A8XX-"/> 2218 <array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4" variants="A6XX-A7XX"/> 2219 <array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4" variants="A6XX-A7XX"/> 2220 <array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4" variants="A6XX-A7XX"/> 2221 2222 <array offset="0x8610" name="GRAS_PERFCTR_TSEFE_SEL" stride="1" length="6" variants="A8XX-"/> 2223 <array offset="0x8710" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="6" variants="A8XX-"/> 2224 <array offset="0x8720" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4" variants="A8XX-"/> 2225 <array offset="0x8730" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="6" variants="A8XX-"/> 2226 2227 2228 <!-- note 0x8620-0x87ff are not all invalid 2229 (in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords) 2230 --> 2231 2232 <!-- same as GRAS_BIN_CONTROL, but without bit 27: --> 2233 <reg32 offset="0x8800" name="RB_CNTL" variants="A6XX-A7XX" type="a6xx_bin_cntl" usage="cmd"/> 2234 <reg32 offset="0x8800" name="RB_CNTL" variants="A8XX-" type="a8xx_bin_cntl" usage="cmd"/> 2235 2236 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="draw"> 2237 <bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/> 2238 <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/> 2239 <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 2240 <bitfield name="UNK8" low="8" high="10"/> 2241 <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/> 2242 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/> 2243 <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/> 2244 <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/> 2245 <!-- bit seems to be set whenever depth buffer enabled: --> 2246 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/> 2247 <!-- bitmask of MRTs using UBWC flag buffer: --> 2248 <bitfield name="FLAG_MRTS" low="16" high="23"/> 2249 </reg32> 2250 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A7XX-" usage="draw"> 2251 <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/> 2252 <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 2253 <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/> 2254 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/> 2255 <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/> 2256 <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/> 2257 </reg32> 2258 2259 <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL" usage="draw"> 2260 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 2261 <bitfield name="UNK2" pos="2"/> 2262 <bitfield name="UNK3" pos="3"/> 2263 </reg32> 2264 <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL" usage="draw"> 2265 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 2266 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 2267 </reg32> 2268 2269 <reg32 offset="0x8804" name="RB_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="draw"/> 2270 <reg32 offset="0x8805" name="RB_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="draw"/> 2271 <reg32 offset="0x8806" name="RB_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="draw"/> 2272 <reg32 offset="0x8807" name="RB_PROGRAMMABLE_MSAA_POS_2" type="a6xx_programmable_msaa_pos" usage="draw" variants="A8XX-"/> 2273 <reg32 offset="0x8808" name="RB_PROGRAMMABLE_MSAA_POS_3" type="a6xx_programmable_msaa_pos" usage="draw" variants="A8XX-"/> 2274 <!-- 2275 note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL 2276 name comes from kernel and is probably right) 2277 --> 2278 <reg32 offset="0x8809" name="RB_INTERP_CNTL" usage="draw"> 2279 <!-- see also GRAS_CL_INTERP_CNTL --> 2280 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> 2281 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> 2282 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/> 2283 <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/> 2284 <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/> 2285 <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/> 2286 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> 2287 <bitfield name="INTERP_EN" pos="10" type="boolean"/> 2288 </reg32> 2289 <reg32 offset="0x880a" name="RB_PS_INPUT_CNTL" usage="draw"> 2290 <!-- enable bits for various FS sysvalue regs: --> 2291 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/> 2292 <bitfield name="POSTDEPTHCOVERAGE" pos="1" type="boolean"/> 2293 <bitfield name="FACENESS" pos="2" type="boolean"/> 2294 <bitfield name="SAMPLEID" pos="3" type="boolean"/> 2295 <bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/> 2296 <bitfield name="CENTERRHW" pos="6" type="boolean"/> 2297 <bitfield name="LINELENGTHEN" pos="7" type="boolean"/> 2298 <bitfield name="FOVEATION" pos="8" type="boolean"/> 2299 </reg32> 2300 2301 <reg32 offset="0x880b" name="RB_PS_OUTPUT_CNTL" usage="draw"> 2302 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> 2303 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/> 2304 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/> 2305 <bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/> 2306 </reg32> 2307 <reg32 offset="0x880c" name="RB_PS_MRT_CNTL" usage="draw"> 2308 <bitfield name="MRT" low="0" high="3" type="uint"/> 2309 </reg32> 2310 <reg32 offset="0x880d" name="RB_PS_OUTPUT_MASK" usage="draw"> 2311 <bitfield name="RT0" low="0" high="3"/> 2312 <bitfield name="RT1" low="4" high="7"/> 2313 <bitfield name="RT2" low="8" high="11"/> 2314 <bitfield name="RT3" low="12" high="15"/> 2315 <bitfield name="RT4" low="16" high="19"/> 2316 <bitfield name="RT5" low="20" high="23"/> 2317 <bitfield name="RT6" low="24" high="27"/> 2318 <bitfield name="RT7" low="28" high="31"/> 2319 </reg32> 2320 <reg32 offset="0x880e" name="RB_DITHER_CNTL" usage="cmd"> 2321 <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/> 2322 <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/> 2323 <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/> 2324 <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/> 2325 <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/> 2326 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/> 2327 <bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/> 2328 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/> 2329 </reg32> 2330 <reg32 offset="0x880f" name="RB_SRGB_CNTL" usage="draw"> 2331 <!-- Same as SP_SRGB_CNTL --> 2332 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/> 2333 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/> 2334 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/> 2335 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/> 2336 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/> 2337 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/> 2338 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/> 2339 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> 2340 </reg32> 2341 2342 <reg32 offset="0x8810" name="RB_PS_SAMPLEFREQ_CNTL" usage="draw"> 2343 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> 2344 </reg32> 2345 <reg32 offset="0x8811" name="RB_MODE_CNTL" low="4" high="6" usage="cmd"/> 2346 <reg32 offset="0x8812" name="RB_BUFFER_CNTL" variants="A7XX-" usage="draw"> 2347 <bitfield name="Z_SYSMEM" pos="0" type="boolean"/> 2348 <bitfield name="S_SYSMEM" pos="1" type="boolean"/> 2349 <bitfield name="RT0_SYSMEM" pos="2" type="boolean"/> 2350 <bitfield name="RT1_SYSMEM" pos="3" type="boolean"/> 2351 <bitfield name="RT2_SYSMEM" pos="4" type="boolean"/> 2352 <bitfield name="RT3_SYSMEM" pos="5" type="boolean"/> 2353 <bitfield name="RT4_SYSMEM" pos="6" type="boolean"/> 2354 <bitfield name="RT5_SYSMEM" pos="7" type="boolean"/> 2355 <bitfield name="RT6_SYSMEM" pos="8" type="boolean"/> 2356 <bitfield name="RT7_SYSMEM" pos="9" type="boolean"/> 2357 <bitfield name="Z_FULL_IN_GMEM" pos="10" type="boolean" variants="A8XX-"/> 2358 <bitfield name="S_FULL_IN_GMEM" pos="11" type="boolean" variants="A8XX-"/> 2359 <bitfield name="RT0_FULL_IN_GMEM" pos="12" type="boolean" variants="A8XX-"/> 2360 <bitfield name="RT1_FULL_IN_GMEM" pos="13" type="boolean" variants="A8XX-"/> 2361 <bitfield name="RT2_FULL_IN_GMEM" pos="14" type="boolean" variants="A8XX-"/> 2362 <bitfield name="RT3_FULL_IN_GMEM" pos="15" type="boolean" variants="A8XX-"/> 2363 <bitfield name="RT4_FULL_IN_GMEM" pos="16" type="boolean" variants="A8XX-"/> 2364 <bitfield name="RT5_FULL_IN_GMEM" pos="17" type="boolean" variants="A8XX-"/> 2365 <bitfield name="RT6_FULL_IN_GMEM" pos="18" type="boolean" variants="A8XX-"/> 2366 <bitfield name="RT7_FULL_IN_GMEM" pos="19" type="boolean" variants="A8XX-"/> 2367 </reg32> 2368 2369 <reg32 offset="0x8816" name="RB_RESOLVE_CR_CNTL" variants="A8XX-" usage="resolve"/> 2370 2371 <!-- 0x8813-0x8817 invalid --> 2372 <!-- always 0x0 ? --> 2373 <reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6" usage="cmd"/> 2374 <!-- 0x8819-0x881e all 32 bits --> 2375 <reg32 offset="0x8819" name="RB_UNKNOWN_8819" usage="cmd"/> 2376 <reg32 offset="0x881a" name="RB_UNKNOWN_881A" usage="cmd"/> 2377 <reg32 offset="0x881b" name="RB_UNKNOWN_881B" usage="cmd"/> 2378 <reg32 offset="0x881c" name="RB_UNKNOWN_881C" usage="cmd"/> 2379 <reg32 offset="0x881d" name="RB_UNKNOWN_881D" usage="cmd"/> 2380 <reg32 offset="0x881e" name="RB_UNKNOWN_881E" usage="cmd"/> 2381 2382 <!-- Duplicates fields from SP_PS_CNTL_0 --> 2383 <reg32 offset="0x881f" name="RB_PS_CNTL" variants="A8XX-" usage="draw"> 2384 <bitfield name="PIXLODENABLE" pos="0" type="boolean"/> 2385 <bitfield name="LODPIXMASK" pos="1" type="boolean"/> 2386 </reg32> 2387 2388 <array offset="0x8820" name="RB_MRT" stride="8" length="8" usage="draw"> 2389 <reg32 offset="0x0" name="CONTROL"> 2390 <bitfield name="COLOR_BLEND_EN" pos="0" type="boolean"/> 2391 <bitfield name="ALPHA_BLEND_EN" pos="1" type="boolean"/> 2392 <bitfield name="ROP_ENABLE" pos="2" type="boolean"/> 2393 <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/> 2394 <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/> 2395 </reg32> 2396 <reg32 offset="0x1" name="BLEND_CONTROL"> 2397 <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/> 2398 <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/> 2399 <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/> 2400 <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/> 2401 <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/> 2402 <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/> 2403 </reg32> 2404 <reg32 offset="0x2" name="BUF_INFO" variants="A6XX"> 2405 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2406 <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 2407 <bitfield name="UNK10" pos="10"/> 2408 <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/> 2409 </reg32> 2410 <reg32 offset="0x2" name="BUF_INFO" variants="A7XX-"> 2411 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2412 <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 2413 <bitfield name="UNK10" pos="10"/> 2414 <bitfield name="LOSSLESSCOMPEN" pos="11" type="boolean"/> 2415 <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/> 2416 <bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/> 2417 </reg32> 2418 <!-- 2419 at least in gmem, things seem to be aligned to pitch of 64.. 2420 maybe an artifact of tiled format used in gmem? 2421 --> 2422 <reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/> 2423 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/> 2424 <!-- 2425 Compared to a5xx and before, we configure both a GMEM base and 2426 external base. Not sure if this is to facilitate GMEM save/ 2427 restore for context switch, or just to simplify state setup to 2428 not have to care about GMEM vs BYPASS mode. 2429 --> 2430 <!-- maybe something in low bits since alignment of 1 doesn't make sense? --> 2431 <reg64 offset="0x5" name="BASE" type="waddress" align="1"/> 2432 2433 <reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/> 2434 </array> 2435 2436 <reg32 offset="0x8860" name="RB_BLEND_CONSTANT_RED_FP32" type="float" usage="draw"/> 2437 <reg32 offset="0x8861" name="RB_BLEND_CONSTANT_GREEN_FP32" type="float" usage="draw"/> 2438 <reg32 offset="0x8862" name="RB_BLEND_CONSTANT_BLUE_FP32" type="float" usage="draw"/> 2439 <reg32 offset="0x8863" name="RB_BLEND_CONSTANT_ALPHA_FP32" type="float" usage="draw"/> 2440 <reg32 offset="0x8864" name="RB_ALPHA_TEST_CNTL" usage="cmd"> 2441 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/> 2442 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/> 2443 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/> 2444 </reg32> 2445 <reg32 offset="0x8865" name="RB_BLEND_CNTL" usage="draw"> 2446 <!-- per-mrt enable bit --> 2447 <bitfield name="BLEND_READS_DEST" low="0" high="7"/> 2448 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/> 2449 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> 2450 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> 2451 <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/> 2452 <bitfield name="SAMPLE_MASK" low="16" high="31"/> 2453 </reg32> 2454 <reg32 offset="0x8866" name="RB_LB_PARAM_LIMIT" variants="A8XX-" usage="draw"> 2455 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> 2456 </reg32> 2457 <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" usage="draw"/> 2458 2459 <reg32 offset="0x8871" name="RB_DEPTH_CNTL" usage="draw"> 2460 <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> 2461 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/> 2462 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/> 2463 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/> 2464 <doc> 2465 Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER 2466 also set when Z_BOUNDS_ENABLE is set 2467 </doc> 2468 <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/> 2469 <bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/> 2470 <!-- clamp shader depth out to [0, 1] (instead of RB_VIEWPORT_ZCLAMP_MIN/MAX)--> 2471 <bitfield name="O_DEPTH_01_CLAMP_EN" pos="8" type="boolean" variants="A8XX-"/> 2472 </reg32> 2473 2474 <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: --> 2475 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A6XX" type="a6xx_depth_buffer_info" usage="draw"/> 2476 <!-- first 4 bits duplicates GRAS_SU_DEPTH_BUFFER_INFO --> 2477 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A7XX-" usage="draw"> 2478 <bitfield name="PRT" low="3" high="4"/> 2479 <bitfield name="TILEMODE" low="5" high="6" type="a6xx_tile_mode"/> 2480 <bitfield name="LOSSLESSCOMPEN" pos="7" type="boolean"/> 2481 </reg32> 2482 2483 <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint" usage="draw"/> 2484 <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint" usage="draw"/> 2485 <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64" usage="draw"/> 2486 <reg32 offset="0x8877" name="RB_DEPTH_GMEM_BASE" low="12" high="31" shr="12" usage="draw"/> 2487 2488 <reg32 offset="0x8878" name="RB_DEPTH_BOUND_MIN" type="float" usage="draw"/> 2489 <reg32 offset="0x8879" name="RB_DEPTH_BOUND_MAX" type="float" usage="draw"/> 2490 <!-- 0x887a-0x887f invalid --> 2491 <reg32 offset="0x8880" name="RB_STENCIL_CNTL" usage="draw"> 2492 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 2493 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/> 2494 <!-- 2495 set for stencil operations that require read from stencil 2496 buffer, but not for example for stencil clear (which does 2497 not require read).. so guessing this is analogous to 2498 READ_DEST_ENABLE for color buffer.. 2499 --> 2500 <bitfield name="STENCIL_READ" pos="2" type="boolean"/> 2501 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/> 2502 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/> 2503 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/> 2504 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/> 2505 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/> 2506 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/> 2507 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/> 2508 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/> 2509 </reg32> 2510 2511 <reg32 offset="0x8881" name="RB_STENCIL_BUFFER_INFO" variants="A6XX" usage="draw"> 2512 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> 2513 <bitfield name="UNK1" pos="1" type="boolean"/> 2514 </reg32> 2515 <reg32 offset="0x8881" name="RB_STENCIL_BUFFER_INFO" variants="A7XX-" usage="draw"> 2516 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> 2517 <bitfield name="UNK1" pos="1" type="boolean"/> 2518 <bitfield name="TILEMODE" low="2" high="3" type="a6xx_tile_mode"/> 2519 </reg32> 2520 <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint" usage="draw"/> 2521 <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint" usage="draw"/> 2522 <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64" usage="draw"/> 2523 <reg32 offset="0x8886" name="RB_STENCIL_GMEM_BASE" low="12" high="31" shr="12" usage="draw"/> 2524 <reg32 offset="0x8887" name="RB_STENCIL_REF_CNTL" usage="draw"> 2525 <bitfield name="REF" low="0" high="7"/> 2526 <bitfield name="BFREF" low="8" high="15"/> 2527 </reg32> 2528 <reg32 offset="0x8888" name="RB_STENCIL_MASK" usage="draw"> 2529 <bitfield name="MASK" low="0" high="7"/> 2530 <bitfield name="BFMASK" low="8" high="15"/> 2531 </reg32> 2532 <reg32 offset="0x8889" name="RB_STENCIL_WRITE_MASK" usage="draw"> 2533 <bitfield name="WRMASK" low="0" high="7"/> 2534 <bitfield name="BFWRMASK" low="8" high="15"/> 2535 </reg32> 2536 <!-- 0x888a-0x888f invalid --> 2537 <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy" usage="cmd"/> 2538 <reg32 offset="0x8891" name="RB_SAMPLE_COUNTER_CNTL" usage="cmd"> 2539 <bitfield name="DISABLE" pos="0" type="boolean"/> 2540 <bitfield name="COPY" pos="1" type="boolean"/> 2541 </reg32> 2542 <!-- 0x8892-0x8897 invalid --> 2543 <reg32 offset="0x8898" name="RB_LRZ_CNTL" usage="draw"> 2544 <bitfield name="ENABLE" pos="0" type="boolean"/> 2545 </reg32> 2546 <reg32 offset="0x8899" name="RB_LRZ_CNTL2" variants="A7XX-" usage="cmd"> 2547 <bitfield name="ENABLE_BIDIRECTIONAL_LRZ" pos="0" type="boolean"/> 2548 </reg32> 2549 <!-- 0x8899-0x88bf invalid --> 2550 <!-- clamps depth value for depth test/write --> 2551 <reg32 offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MIN" type="float" usage="draw" variants="A6XX-A7XX"/> 2552 <reg32 offset="0x88c1" name="RB_VIEWPORT_ZCLAMP_MAX" type="float" usage="draw" variants="A6XX-A7XX"/> 2553 2554<!-- todo allow type="float" on an <array/> --> 2555 <array offset="0x88b0" name="RB_VIEWPORT_ZCLAMP_MIN" stride="1" length="16" usage="draw" variants="A8XX-"> 2556 <reg32 offset="0" name="REG" type="float"/> 2557 </array> 2558 <array offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MAX" stride="1" length="16" usage="draw" variants="A8XX-"> 2559 <reg32 offset="0" name="REG" type="float"/> 2560 </array> 2561 2562 <!-- 0x88c2-0x88cf invalid--> 2563 <reg32 offset="0x88d0" name="RB_RESOLVE_CNTL_0" usage="resolve"> 2564 <bitfield name="UNK0" low="0" high="12"/> 2565 <bitfield name="UNK16" low="16" high="26"/> 2566 </reg32> 2567 <reg32 offset="0x88d1" name="RB_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="resolve"/> 2568 <reg32 offset="0x88d2" name="RB_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="resolve"/> 2569 <!-- weird to duplicate other regs from same block?? --> 2570 <reg32 offset="0x88d3" name="RB_RESOLVE_CNTL_3" variants="A6XX-A7XX" usage="resolve"> 2571 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 2572 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 2573 </reg32> 2574 2575 <reg32 offset="0x88d3" name="RB_RESOLVE_CNTL_3" type="a8xx_bin_size" variants="A8XX-" usage="resolve"/> 2576 <reg32 offset="0x88f0" name="RB_RESOLVE_CNTL_4" variants="A8XX-" usage="resolve"/> 2577 <reg32 offset="0x88f1" name="RB_RESOLVE_CNTL_5" variants="A8XX-" usage="resolve"/> 2578 2579 <reg32 offset="0x88d4" name="RB_RESOLVE_WINDOW_OFFSET" type="a6xx_reg_xy" usage="resolve"/> 2580 <reg32 offset="0x88d5" name="RB_RESOLVE_GMEM_BUFFER_INFO" usage="resolve"> 2581 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> 2582 </reg32> 2583 <reg32 offset="0x88d6" name="RB_RESOLVE_GMEM_BUFFER_BASE" low="12" high="31" shr="12" usage="resolve"/> 2584 <!-- s/DST_FORMAT/DST_INFO/ probably: --> 2585 <reg32 offset="0x88d7" name="RB_RESOLVE_SYSTEM_BUFFER_INFO" usage="resolve"> 2586 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> 2587 <bitfield name="FLAGS" pos="2" type="boolean"/> 2588 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> 2589 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/> 2590 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/> 2591 <bitfield name="UNK15" pos="15" type="boolean"/> 2592 <bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/> 2593 </reg32> 2594 <reg64 offset="0x88d8" name="RB_RESOLVE_SYSTEM_BUFFER_BASE" type="waddress" align="64" usage="resolve"/> 2595 <reg32 offset="0x88da" name="RB_RESOLVE_SYSTEM_BUFFER_PITCH" low="0" high="15" shr="6" type="uint" usage="resolve"/> 2596 <!-- array-pitch is size of layer --> 2597 <reg32 offset="0x88db" name="RB_RESOLVE_SYSTEM_BUFFER_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage="resolve"/> 2598 <reg64 offset="0x88dc" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_BASE" type="waddress" align="64" usage="resolve"/> 2599 2600 <bitset name="a6xx_flag_buffer_pitch" inline="yes"> 2601 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 2602 <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/> 2603 </bitset> 2604 2605 <reg32 offset="0x88de" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch" usage="resolve"/> 2606 2607 <reg32 offset="0x88df" name="RB_RESOLVE_CLEAR_COLOR_DW0" usage="resolve"/> 2608 <reg32 offset="0x88e0" name="RB_RESOLVE_CLEAR_COLOR_DW1" usage="resolve"/> 2609 <reg32 offset="0x88e1" name="RB_RESOLVE_CLEAR_COLOR_DW2" usage="resolve"/> 2610 <reg32 offset="0x88e2" name="RB_RESOLVE_CLEAR_COLOR_DW3" usage="resolve"/> 2611 2612 <enum name="a6xx_blit_event_type"> 2613 <value value="0x0" name="BLIT_EVENT_STORE"/> 2614 <value value="0x1" name="BLIT_EVENT_STORE_AND_CLEAR"/> 2615 <value value="0x2" name="BLIT_EVENT_CLEAR"/> 2616 <value value="0x3" name="BLIT_EVENT_LOAD"/> 2617 </enum> 2618 2619 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: --> 2620 <reg32 offset="0x88e3" name="RB_RESOLVE_OPERATION" usage="resolve"> 2621 <bitfield name="TYPE" low="0" high="1" type="a6xx_blit_event_type"/> 2622 <bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging --> 2623 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? --> 2624 <doc> 2625 For clearing depth/stencil 2626 1 - depth 2627 2 - stencil 2628 3 - depth+stencil 2629 For clearing color buffer: 2630 then probably a component mask, I always see 0xf 2631 </doc> 2632 <bitfield name="CLEAR_MASK" low="4" high="7"/> 2633 <!-- set when this is the last resolve on a650+ --> 2634 <bitfield name="LAST" low="8" high="9"/> 2635 <!-- 2636 a618 GLES: color render target number being resolved for CCU_RESOLVE, 0x8 for depth, 0x9 for separate stencil. 2637 a618 VK: 0x8 for depth CCU_RESOLVE, 0x9 for separate stencil, 0 otherwise. 2638 a7xx VK: 0x8 for depth, 0x9 for separate stencil, 0x0 to 0x7 used for concurrent resolves of color render 2639 targets inside a given resolve group. 2640 --> 2641 <bitfield name="BUFFER_ID" low="12" high="15"/> 2642 </reg32> 2643 2644 <enum name="a7xx_blit_clear_mode"> 2645 <value value="0x0" name="CLEAR_MODE_SYSMEM"/> 2646 <value value="0x1" name="CLEAR_MODE_GMEM"/> 2647 </enum> 2648 <reg32 offset="0x88e4" name="RB_CLEAR_TARGET" variants="A7XX-" usage="resolve"> 2649 <bitfield name="CLEAR_MODE" pos="0" type="a7xx_blit_clear_mode"/> 2650 </reg32> 2651 2652 <enum name="a6xx_ccu_cache_size"> 2653 <value value="0x0" name="CCU_CACHE_SIZE_FULL"/> 2654 <value value="0x1" name="CCU_CACHE_SIZE_HALF"/> 2655 <value value="0x2" name="CCU_CACHE_SIZE_QUARTER"/> 2656 <value value="0x3" name="CCU_CACHE_SIZE_EIGHTH"/> 2657 <!-- for DEPTH_CACHE_SIZE 3 == THREE_QUARTER from KNP --> 2658 <value value="0x3" name="CCU_CACHE_SIZE_THREE_QUARTER"/> 2659 </enum> 2660 <reg32 offset="0x88e5" name="RB_CCU_CACHE_CNTL" variants="A7XX" usage="cmd"> 2661 <bitfield name="DEPTH_OFFSET_HI" pos="0" type="hex"/> 2662 <bitfield name="COLOR_OFFSET_HI" pos="2" type="hex"/> 2663 <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/> 2664 <!-- GMEM offset of CCU depth cache --> 2665 <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/> 2666 <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/> 2667 <!-- GMEM offset of CCU color cache 2668 for GMEM rendering, we set it to GMEM size minus the minimum 2669 CCU color cache size. CCU color cache will be needed in some 2670 resolve cases, and in those cases we need to reserve the end 2671 of GMEM for color cache. 2672 --> 2673 <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/> 2674 </reg32> 2675 2676 <reg32 offset="0x88e5" name="RB_CCU_CACHE_CNTL" variants="A8XX-" usage="cmd"> 2677 <!-- 2678 For color cache, full is 128KB per CCU. For depth cache, 2679 full is 256KB per CCU. 2680 2681 For attr/pos caches (see VPC_{ATTR,POS,BV_POS}_BUF_GMEM_SIZE), 2682 the sizes are per CCU 2683 --> 2684 <bitfield name="COLOR_OFFSET" low="0" high="13" shr="12" type="hex"/> 2685 <bitfield name="COLOR_CACHE_SIZE" low="14" high="15" type="a6xx_ccu_cache_size"/> 2686 <bitfield name="DEPTH_OFFSET" low="16" high="29" shr="12" type="hex"/> 2687 <bitfield name="DEPTH_CACHE_SIZE" low="30" high="31" type="a6xx_ccu_cache_size"/> 2688 </reg32> 2689 2690 <reg32 offset="0x88e6" name="RB_RESOLVE_GMEM_BUFFER_CNTL" variants="A8XX-" usage="resolve"> 2691 <bitfield name="FULL_IN_GMEM" pos="0" type="boolean"/> 2692 </reg32> 2693 2694 <!-- always 0x0 ? --> 2695 <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" variants="A6XX" usage="resolve"/> 2696 <!-- could be for separate stencil? (or may not be a flag buffer at all) --> 2697 <reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64" variants="A6XX"/> 2698 <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch" variants="A6XX"/> 2699 2700 <reg32 offset="0x88f4" name="RB_VRS_CONFIG" usage="draw"> 2701 <bitfield name="UNK2" pos="2" type="boolean"/> 2702 <bitfield name="PIPELINE_FSR_ENABLE" pos="4" type="boolean"/> 2703 <bitfield name="ATTACHMENT_FSR_ENABLE" pos="5" type="boolean"/> 2704 <bitfield name="PRIMITIVE_FSR_ENABLE" pos="18" type="boolean"/> 2705 </reg32> 2706 <reg32 offset="0x88f5" name="RB_BIN_FOVEAT" variants="A7XX-" usage="cmd"> 2707 <bitfield name="BINSCALEEN" pos="6" type="boolean"/> 2708 </reg32> 2709 2710 <array offset="0x8950" name="RB_BIN_FOVEAT_XY" stride="1" length="6" variants="A8XX-" usage="cmd"> 2711 <reg32 offset="0" name="OFFSET" type="a8xx_bin_foveat_xy"/> 2712 </array> 2713 2714 <array offset="0x8960" name="RB_BIN_FOVEAT_XY_FDM" stride="1" length="6" variants="A8XX-" usage="cmd"> 2715 <reg32 offset="0" name="OFFSET" type="a8xx_bin_foveat_xy"/> 2716 </array> 2717 2718 <!-- 0x88f6-0x88ff invalid --> 2719 <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64" usage="draw"/> 2720 <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH" usage="draw"> 2721 <bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/> 2722 <!-- TODO: actually part of array pitch --> 2723 <bitfield name="UNK8" low="8" high="10"/> 2724 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> 2725 </reg32> 2726 2727 <array offset="0x8903" name="RB_COLOR_FLAG_BUFFER" stride="3" length="8" usage="draw"> 2728 <reg64 offset="0" name="ADDR" type="waddress" align="64"/> 2729 <reg32 offset="2" name="PITCH" type="a6xx_flag_buffer_pitch"/> 2730 </array> 2731 <!-- 0x891b-0x8926 invalid --> 2732 <doc> 2733 RB_SAMPLE_COUNTER_BASE register is used up to (and including) a730. After that 2734 the address is specified through CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT. 2735 </doc> 2736 <reg64 offset="0x8927" name="RB_SAMPLE_COUNTER_BASE" type="waddress" align="16" usage="cmd"/> 2737 2738 <bitset name="a8xx_gmem_dimension" inline="yes"> 2739 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 2740 <bitfield name="HEIGHT" low="16" high="30" type="uint"/> 2741 </bitset> 2742 2743 <reg32 offset="0x8813" name="RB_DEPTH_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-"/> 2744 <reg32 offset="0x8814" name="RB_STENCIL_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-"/> 2745 <reg32 offset="0x8815" name="RB_RESOLVE_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-" usage="resolve"/> 2746 <reg32 offset="0x88af" name="RB_RESOLVE_GMEM_PARTITION" variants="A8XX-" usage="resolve"/> 2747 2748 <array offset="0x8930" name="RB_MRT_GMEM_DIMENSION" variants="A8XX-" stride="1" length="8"> 2749 <reg32 offset="0" name="REG" type="a8xx_gmem_dimension"/> 2750 </array> 2751 2752 <!-- 2753 These show up in a6xx gen3+ but so far haven't found an example of 2754 blob writing non-zero: 2755 --> 2756 <reg32 offset="0x8a00" name="RB_UNKNOWN_8A00" variants="A6XX" usage="draw"/> 2757 <reg32 offset="0x8a10" name="RB_UNKNOWN_8A10" variants="A6XX" usage="draw"/> 2758 <reg32 offset="0x8a20" name="RB_UNKNOWN_8A20" variants="A6XX" usage="draw"/> 2759 <reg32 offset="0x8a30" name="RB_UNKNOWN_8A30" variants="A6XX" usage="draw"/> 2760 2761 <reg32 offset="0x8c00" name="RB_A2D_BLT_CNTL" type="a6xx_a2d_blt_cntl" usage="blit"/> 2762 <reg32 offset="0x8c01" name="RB_A2D_PIXEL_CNTL" low="0" high="31" usage="blit"/> 2763 2764 <bitset name="a6xx_a2d_src_texture_info" inline="yes"> 2765 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2766 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 2767 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> 2768 <bitfield name="FLAGS" pos="12" type="boolean"/> 2769 <bitfield name="SRGB" pos="13" type="boolean"/> 2770 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/> 2771 <bitfield name="FILTER" pos="16" type="boolean"/> 2772 <bitfield name="UNK17" pos="17" type="boolean"/> 2773 <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/> 2774 <bitfield name="UNK19" pos="19" type="boolean"/> 2775 <bitfield name="UNK20" pos="20" type="boolean"/> 2776 <bitfield name="UNK21" pos="21" type="boolean"/> 2777 <bitfield name="UNK22" pos="22" type="boolean"/> 2778 <bitfield name="UNK23" low="23" high="26"/> 2779 <bitfield name="UNK28" pos="28" type="boolean"/> 2780 <bitfield name="MUTABLEEN" pos="29" type="boolean" variants="A7XX-"/> 2781 </bitset> 2782 2783 <bitset name="a6xx_a2d_dest_buffer_info" inline="yes"> 2784 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2785 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 2786 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> 2787 <bitfield name="FLAGS" pos="12" type="boolean"/> 2788 <bitfield name="SRGB" pos="13" type="boolean"/> 2789 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/> 2790 <bitfield name="MUTABLEEN" pos="17" type="boolean" variants="A7XX-"/> 2791 </bitset> 2792 2793 <!-- 0x8c02-0x8c16 invalid --> 2794 <reg32 offset="0x8c17" name="RB_A2D_DEST_BUFFER_INFO" type="a6xx_a2d_dest_buffer_info" usage="blit"/> 2795 <reg64 offset="0x8c18" name="RB_A2D_DEST_BUFFER_BASE" type="waddress" align="64" usage="blit"/> 2796 <reg32 offset="0x8c1a" name="RB_A2D_DEST_BUFFER_PITCH" low="0" high="15" shr="6" type="uint" usage="blit"/> 2797 <!-- this is a guess but seems likely (for NV12/IYUV): --> 2798 <reg64 offset="0x8c1b" name="RB_A2D_DEST_BUFFER_BASE_1" type="waddress" align="64" usage="blit"/> 2799 <reg32 offset="0x8c1d" name="RB_A2D_DEST_BUFFER_PITCH_1" low="0" high="15" shr="6" type="uint" usage="blit"/> 2800 <reg64 offset="0x8c1e" name="RB_A2D_DEST_BUFFER_BASE_2" type="waddress" align="64" usage="blit"/> 2801 2802 <reg64 offset="0x8c20" name="RB_A2D_DEST_FLAG_BUFFER_BASE" type="waddress" align="64" usage="blit"/> 2803 <reg32 offset="0x8c22" name="RB_A2D_DEST_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch" usage="blit"/> 2804 <!-- this is a guess but seems likely (for NV12 with UBWC): --> 2805 <reg64 offset="0x8c23" name="RB_A2D_DEST_FLAG_BUFFER_BASE_1" type="waddress" align="64" usage="blit"/> 2806 <reg32 offset="0x8c25" name="RB_A2D_DEST_FLAG_BUFFER_PITCH_1" low="0" high="7" shr="6" type="uint" usage="blit"/> 2807 2808 <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers --> 2809 <!-- unlike a5xx, these are per channel values rather than packed --> 2810 <reg32 offset="0x8c2c" name="RB_A2D_CLEAR_COLOR_DW0" usage="blit"/> 2811 <reg32 offset="0x8c2d" name="RB_A2D_CLEAR_COLOR_DW1" usage="blit"/> 2812 <reg32 offset="0x8c2e" name="RB_A2D_CLEAR_COLOR_DW2" usage="blit"/> 2813 <reg32 offset="0x8c2f" name="RB_A2D_CLEAR_COLOR_DW3" usage="blit"/> 2814 2815 <reg32 offset="0x8c34" name="RB_A2D_UNKNOWN_8C34" variants="A7XX-" usage="blit"/> 2816 2817 <!-- 0x8c35-0x8dff invalid --> 2818 2819 <!-- always 0x1 ? either doesn't exist for a650 or write-only: --> 2820 <reg32 offset="0x8e01" name="RB_RBP_CNTL" usage="cmd"/> 2821 <!-- 0x8e00-0x8e03 invalid --> 2822 <reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff --> 2823 <reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" variants="A6XX"/> 2824 <!-- 0x02080000 in GMEM, zero otherwise? --> 2825 <reg32 offset="0x8e06" name="RB_CCU_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> 2826 2827 <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A6XX"> 2828 <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/> 2829 <!-- concurrent resolves are apparently a 2-bit enum on a650+ --> 2830 <bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/> 2831 <bitfield name="DEPTH_OFFSET_HI" pos="7" type="hex"/> 2832 <bitfield name="COLOR_OFFSET_HI" pos="9" type="hex"/> 2833 <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/> 2834 <!-- GMEM offset of CCU depth cache --> 2835 <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/> 2836 <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/> 2837 <!-- GMEM offset of CCU color cache 2838 for GMEM rendering, we set it to GMEM size minus the minimum 2839 CCU color cache size. CCU color cache will be needed in some 2840 resolve cases, and in those cases we need to reserve the end 2841 of GMEM for color cache. 2842 --> 2843 <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/> 2844 <!--TODO: valid mask 0xfffffc1f --> 2845 </reg32> 2846 <enum name="a7xx_concurrent_resolve_mode"> 2847 <value value="0x0" name="CONCURRENT_RESOLVE_MODE_DISABLED"/> 2848 <value value="0x1" name="CONCURRENT_RESOLVE_MODE_1"/> 2849 <value value="0x2" name="CONCURRENT_RESOLVE_MODE_2"/> 2850 </enum> 2851 <enum name="a7xx_concurrent_unresolve_mode"> 2852 <value value="0x0" name="CONCURRENT_UNRESOLVE_MODE_DISABLED"/> 2853 <value value="0x1" name="CONCURRENT_UNRESOLVE_MODE_PARTIAL"/> 2854 <value value="0x3" name="CONCURRENT_UNRESOLVE_MODE_FULL"/> 2855 </enum> 2856 <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A7XX-"> 2857 <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/> 2858 <bitfield name="CONCURRENT_RESOLVE_MODE" low="2" high="3" type="a7xx_concurrent_resolve_mode"/> 2859 <bitfield name="CONCURRENT_UNRESOLVE_MODE" low="5" high="6" type="a7xx_concurrent_unresolve_mode"/> 2860 <!-- rest of the bits were moved to RB_CCU_CACHE_CNTL --> 2861 </reg32> 2862 <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL" variants="A6XX-A7XX"> 2863 <bitfield name="MODE" pos="0" type="boolean"/> 2864 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/> 2865 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b --> 2866 <bitfield name="AMSBC" pos="4" type="boolean"/> 2867 <bitfield name="UPPER_BIT" pos="10" type="uint"/> 2868 <bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/> 2869 <bitfield name="UNK12" low="12" high="13"/> 2870 </reg32> 2871 <reg32 offset="0x8e08" name="RB_CCU_NC_MODE_CNTL" variants="A8XX-"/> 2872 2873 <reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX" usage="cmd"/> 2874 <reg32 offset="0x8e09" name="RB_GC_GMEM_PROTECT" variants="A8XX-"/> 2875 <reg32 offset="0x8e0a" name="RB_LPAC_GMEM_PROTECT" variants="A8XX-"/> 2876 <!-- 0x8e09-0x8e0f invalid --> 2877 <array offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/> 2878 <array offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/> 2879 <!-- 0x8e1d-0x8e1f invalid --> 2880 <!-- 0x8e20-0x8e25 more perfcntr sel? --> 2881 <!-- 0x8e26-0x8e27 invalid --> 2882 2883 <reg32 offset="0x8f00" name="RB_CMP_NC_MODE_CNTL" variants="A8XX-"/> 2884 <reg32 offset="0x8f01" name="RB_RESOLVE_PREFETCH_CNTL" variants="A8XX-" usage="resolve"/> 2885 <reg32 offset="0x8f02" name="RB_CMP_DBG_ECO_CNTL" variants="A8XX-"/> 2886 2887 <reg32 offset="0x8f03" name="RB_UNSLICE_STATUS" variants="A8XX-"/> 2888 <reg32 offset="0x8e28" name="RB_CMP_DBG_ECO_CNTL" variants="A6XX-A7XX"/> 2889 <!-- 0x8e29-0x8e2b invalid --> 2890 <array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4" variants="A6XX-A7XX"/> 2891 <array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX"/> 2892 <array offset="0x8f04" name="RB_PERFCTR_CMP_SEL" stride="1" length="4" variants="A8XX-"/> 2893 <array offset="0x8f10" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A8XX-"/> 2894 <reg32 offset="0x8e3b" name="RB_SUB_BLOCK_SEL_CNTL_HOST"/> 2895 <reg32 offset="0x8e3d" name="RB_SUB_BLOCK_SEL_CNTL_CD"/> 2896 <reg32 offset="0x8f29" name="RB_UFC_DBG_CNTL" variants="A8XX-"/> 2897 <!-- 0x8e3e-0x8e4f invalid --> 2898 <!-- GMEM save/restore for preemption: --> 2899 <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE" pos="0" type="boolean"/> 2900 <!-- address for GMEM save/restore? --> 2901 <reg32 offset="0x8e51" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ADDR" type="waddress" align="1"/> 2902 <reg32 offset="0x8e77" name="RB_SLICE_UFC_PREFETCH_CNTL" variants="A8XX-"/> 2903 <reg32 offset="0x8e78" name="RB_SLICE_UFC_DBG_CNTL" variants="A8XX-"/> 2904 <reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX" usage="init"/> 2905 <!-- 0x8e80-0x8e83 are valid --> 2906 <!-- 0x8e84-0x90ff invalid --> 2907 2908 <!-- 0x9000-0x90ff invalid --> 2909 2910 <reg32 offset="0x9100" name="VPC_GS_PARAM" variants="A6XX" usage="draw"> 2911 <bitfield name="LINELENGTHLOC" low="0" high="7" type="uint"/> 2912 </reg32> 2913 2914 <bitset name="a6xx_vpc_xs_clip_cntl" inline="yes"> 2915 <bitfield name="CLIP_MASK" low="0" high="7" type="uint"/> 2916 <!-- there can be up to 8 total clip/cull distance outputs, 2917 but apparenly VPC can only deal with vec4, so when there are 2918 more than 4 outputs a second location needs to be programmed 2919 --> 2920 <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/> 2921 <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/> 2922 </bitset> 2923 <reg32 offset="0x9101" name="VPC_VS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="draw"/> 2924 <reg32 offset="0x9102" name="VPC_GS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="draw"/> 2925 <reg32 offset="0x9103" name="VPC_DS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="draw"/> 2926 2927 <reg32 offset="0x9307" name="VPC_VS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A8XX" usage="draw"/> 2928 <reg32 offset="0x9308" name="VPC_GS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A8XX" usage="draw"/> 2929 <reg32 offset="0x9309" name="VPC_DS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A8XX" usage="draw"/> 2930 2931 <reg32 offset="0x9311" name="VPC_VS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="draw"/> 2932 <reg32 offset="0x9312" name="VPC_GS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="draw"/> 2933 <reg32 offset="0x9313" name="VPC_DS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="draw"/> 2934 2935 <bitset name="a6xx_vpc_xs_siv_cntl" inline="yes"> 2936 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/> 2937 <bitfield name="VIEWLOC" low="8" high="15" type="uint"/> 2938 <bitfield name="SHADINGRATELOC" low="16" high="23" type="uint" variants="A7XX-"/> 2939 </bitset> 2940 2941 <reg32 offset="0x9104" name="VPC_VS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="draw"/> 2942 <reg32 offset="0x9105" name="VPC_GS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="draw"/> 2943 <reg32 offset="0x9106" name="VPC_DS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="draw"/> 2944 2945 <reg32 offset="0x930a" name="VPC_VS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A8XX-" usage="draw"/> 2946 <reg32 offset="0x930b" name="VPC_GS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A8XX-" usage="draw"/> 2947 <reg32 offset="0x930c" name="VPC_DS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A8XX-" usage="draw"/> 2948 2949 <reg32 offset="0x9314" name="VPC_VS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="draw"/> 2950 <reg32 offset="0x9315" name="VPC_GS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="draw"/> 2951 <reg32 offset="0x9316" name="VPC_DS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="draw"/> 2952 2953 <bitset name="a6xx_vpc_rast_stream_cntl" inline="yes"> 2954 <!-- which stream to send to GRAS --> 2955 <bitfield name="STREAM" low="0" high="1" type="uint"/> 2956 <!-- discard primitives before rasterization --> 2957 <bitfield name="DISCARD" pos="2" type="boolean"/> 2958 </bitset> 2959 2960 <reg32 offset="0x9980" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A6XX" usage="draw"/> 2961 <reg32 offset="0x9107" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A7XX" usage="draw"/> 2962 <reg32 offset="0x930d" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A8XX-" usage="draw"/> 2963 <reg32 offset="0x9317" name="VPC_RAST_STREAM_CNTL_V2" type="a6xx_vpc_rast_stream_cntl" variants="A7XX" usage="draw"/> 2964 2965 <reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="draw"> 2966 <!-- this mirrors VPC_RAST_STREAM_CNTL::DISCARD, although it seems it's unused --> 2967 <bitfield name="RASTER_DISCARD" pos="0" type="boolean"/> 2968 <bitfield name="UNK2" pos="2" type="boolean"/> 2969 </reg32> 2970 2971 <reg32 offset="0x9108" name="VPC_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX-A7XX" usage="draw"/> 2972 <reg32 offset="0x930e" name="VPC_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX-" usage="draw"/> 2973 <bitset name="a6xx_pc_cntl" inline="yes"> 2974 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/> 2975 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/> 2976 <bitfield name="D3D_VERTEX_ORDERING" pos="2" type="boolean"> 2977 <doc> 2978 Swaps TESS_CW_TRIS/TESS_CCW_TRIS, and also makes 2979 triangle fans and triangle strips use the D3D 2980 order instead of the OpenGL order. 2981 </doc> 2982 </bitfield> 2983 <bitfield name="UNK3" pos="3" type="boolean"/> 2984 </bitset> 2985 2986 <bitset name="a6xx_gs_param_0" inline="yes"> 2987 <doc> 2988 geometry shader 2989 </doc> 2990 <!-- TODO: first 16 bits are valid so something is wrong or missing here --> 2991 <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/> 2992 <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/> 2993 <bitfield name="LINELENGTHEN" pos="15" type="boolean"/> 2994 <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/> 2995 <bitfield name="UNK18" pos="18"/> 2996 </bitset> 2997 2998 <bitset name="a6xx_stereo_rendering_cntl" inline="yes"> 2999 <bitfield name="ENABLE" pos="0" type="boolean"/> 3000 <bitfield name="DISABLEMULTIPOS" pos="1" type="boolean"> 3001 <doc> 3002 Multi-position output lets the last geometry 3003 stage shader write multiple copies of 3004 gl_Position. If disabled then the VS is run once 3005 for each view, and ViewID is passed as a 3006 register to the VS. 3007 </doc> 3008 </bitfield> 3009 <bitfield name="VIEWS" low="2" high="6" type="uint"/> 3010 </bitset> 3011 3012 <reg32 offset="0x9109" name="VPC_PC_CNTL" type="a6xx_pc_cntl" variants="A7XX" usage="draw"/> 3013 <reg32 offset="0x930f" name="VPC_PC_CNTL" type="a6xx_pc_cntl" variants="A8XX-" usage="draw"/> 3014 <reg32 offset="0x910a" name="VPC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A7XX" usage="draw"/> 3015 <reg32 offset="0x90c0" name="VPC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A8XX-" usage="draw"/> 3016 <reg32 offset="0x910b" name="VPC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A7XX" usage="draw"/> 3017 <reg32 offset="0x90c1" name="VPC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A8XX-" usage="draw"/> 3018 <reg32 offset="0x910c" name="VPC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A7XX" usage="draw"/> 3019 <reg32 offset="0x931a" name="VPC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A8XX-" usage="draw"/> 3020 3021 <enum name="a6xx_varying_interp_mode"> 3022 <value value="0" name="INTERP_SMOOTH"/> 3023 <value value="1" name="INTERP_FLAT"/> 3024 <value value="2" name="INTERP_ZERO"/> 3025 <value value="3" name="INTERP_ONE"/> 3026 </enum> 3027 3028 <enum name="a6xx_varying_ps_repl_mode"> 3029 <value value="0" name="PS_REPL_NONE"/> 3030 <value value="1" name="PS_REPL_S"/> 3031 <value value="2" name="PS_REPL_T"/> 3032 <value value="3" name="PS_REPL_ONE_MINUS_T"/> 3033 </enum> 3034 3035 <!-- 0x9109-0x91ff invalid --> 3036 <array offset="0x9200" name="VPC_VARYING_INTERP_MODE" stride="1" length="8" variants="A6XX-A7XX" usage="draw"> 3037 <doc>Packed array of a6xx_varying_interp_mode</doc> 3038 <reg32 offset="0x0" name="MODE"/> 3039 </array> 3040 <array offset="0x9208" name="VPC_VARYING_REPLACE_MODE" stride="1" length="8" variants="A6XX-A7XX" usage="draw"> 3041 <doc>Packed array of a6xx_varying_ps_repl_mode</doc> 3042 <reg32 offset="0x0" name="MODE"/> 3043 </array> 3044 3045 <array offset="0x9240" name="VPC_VARYING_INTERP_MODE" stride="1" length="8" variants="A8XX-" usage="draw"> 3046 <doc>Packed array of a6xx_varying_interp_mode</doc> 3047 <reg32 offset="0x0" name="MODE"/> 3048 </array> 3049 <array offset="0x9248" name="VPC_VARYING_REPLACE_MODE" stride="1" length="8" variants="A8XX-" usage="draw"> 3050 <doc>Packed array of a6xx_varying_ps_repl_mode</doc> 3051 <reg32 offset="0x0" name="MODE"/> 3052 </array> 3053 3054 <!-- always 0x0 --> 3055 <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/> 3056 <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/> 3057 3058 <array offset="0x9212" name="VPC_VARYING_LM_TRANSFER_CNTL" stride="1" length="4" variants="A6XX-A7XX" usage="draw"> 3059 <!-- one bit per varying component: --> 3060 <reg32 offset="0" name="DISABLE"/> 3061 </array> 3062 3063 <array offset="0x9252" name="VPC_VARYING_LM_TRANSFER_CNTL" stride="1" length="4" variants="A8XX-" usage="draw"> 3064 <!-- one bit per varying component: --> 3065 <reg32 offset="0" name="DISABLE"/> 3066 </array> 3067 3068 <bitset name="a6xx_vpc_so_mapping_wptr" inline="yes"> 3069 <!-- 3070 Choose which DWORD to write to. There is an array of 3071 (4 * 64) DWORD's, dumped in the devcoredump at 3072 HLSQ_INST_RAM dword 0x400. Each DWORD corresponds to a 3073 (VPC location, stream) pair like so: 3074 3075 location 0, stream 0 3076 location 2, stream 0 3077 ... 3078 location 126, stream 0 3079 location 0, stream 1 3080 location 2, stream 1 3081 ... 3082 location 126, stream 1 3083 location 0, stream 2 3084 ... 3085 3086 When EmitStreamVertex(N) happens, the HW goes to DWORD 3087 64 * N and then "executes" the next 64 DWORD's. 3088 3089 This field is auto-incremented when VPC_SO_MAPPING_PORT is 3090 written to. 3091 --> 3092 <bitfield name="ADDR" low="0" high="7" type="hex"/> 3093 <!-- clear all A_EN and B_EN bits for all DWORD's --> 3094 <bitfield name="RESET" pos="16" type="boolean"/> 3095 </bitset> 3096 3097 <reg32 offset="0x9216" name="VPC_SO_MAPPING_WPTR" type="a6xx_vpc_so_mapping_wptr" variants="A6XX-A7XX" usage="draw"/> 3098 <reg32 offset="0x9180" name="VPC_SO_MAPPING_WPTR" type="a6xx_vpc_so_mapping_wptr" variants="A8XX-" usage="draw"/> 3099 3100 <bitset name="a6xx_vpc_so_mapping_port" inline="yes"> 3101 <bitfield name="A_BUF" low="0" high="1" type="uint"/> 3102 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/> 3103 <bitfield name="A_EN" pos="11" type="boolean"/> 3104 <bitfield name="B_BUF" low="12" high="13" type="uint"/> 3105 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/> 3106 <bitfield name="B_EN" pos="23" type="boolean"/> 3107 </bitset> 3108 3109 <!-- special register, write multiple times to load SO program (not readable) --> 3110 <reg32 offset="0x9217" name="VPC_SO_MAPPING_PORT" type="a6xx_vpc_so_mapping_port" variants="A6XX-A7XX" usage="draw"/> 3111 <reg32 offset="0x9181" name="VPC_SO_MAPPING_PORT" type="a6xx_vpc_so_mapping_port" variants="A8XX-" usage="draw"/> 3112 3113 <reg64 offset="0x9218" name="VPC_SO_QUERY_BASE" type="waddress" align="32" variants="A6XX-A7XX" usage="cmd"/> 3114 <reg64 offset="0x9182" name="VPC_SO_QUERY_BASE" type="waddress" align="32" variants="A8XX-" usage="cmd"/> 3115 3116 <array offset="0x921a" name="VPC_SO" stride="7" length="4" variants="A6XX-A7XX" usage="cmd"> 3117 <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/> 3118 <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/> 3119 <reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/> 3120 <reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/> 3121 <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/> 3122 </array> 3123 3124 <array offset="0x9184" name="VPC_SO" stride="7" length="4" variants="A8XX-" usage="cmd"> 3125 <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/> 3126 <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/> 3127 <reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/> 3128 <reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/> 3129 <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/> 3130 </array> 3131 3132 <bitset name="a6xx_vpc_replace_mode_cntl" inline="yes"> 3133 <bitfield name="INVERT" pos="0" type="boolean"/> 3134 </bitset> 3135 3136 <reg32 offset="0x9236" name="VPC_REPLACE_MODE_CNTL" type="a6xx_vpc_replace_mode_cntl" variants="A6XX-A7XX" usage="cmd"/> 3137 <reg32 offset="0x9310" name="VPC_REPLACE_MODE_CNTL" type="a6xx_vpc_replace_mode_cntl" variants="A8XX-" usage="cmd"/> 3138 3139 <reg32 offset="0x9300" name="VPC_ROTATION_CNTL" low="0" high="2" variants="A6XX-A7XX" usage="cmd"/> 3140 <reg32 offset="0x9312" name="VPC_ROTATION_CNTL" low="0" high="2" variants="A8XX-" usage="cmd"/> 3141 3142 <bitset name="a6xx_vpc_xs_cntl" inline="yes"> 3143 <doc> 3144 num of varyings plus four for gl_Position (plus one if gl_PointSize) 3145 plus # of transform-feedback (streamout) varyings if using the 3146 hw streamout (rather than stg instructions in shader) 3147 </doc> 3148 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/> 3149 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/> 3150 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/> 3151 <bitfield name="EXTRAPOS" low="24" high="27" type="uint"> 3152 <doc> 3153 The number of extra copies of POSITION, i.e. 3154 number of views minus one when multi-position 3155 output is enabled, otherwise 0. 3156 </doc> 3157 </bitfield> 3158 </bitset> 3159 3160 <reg32 offset="0x9301" name="VPC_VS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="draw"/> 3161 <reg32 offset="0x9302" name="VPC_GS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="draw"/> 3162 <reg32 offset="0x9303" name="VPC_DS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="draw"/> 3163 3164 <reg32 offset="0x9300" name="VPC_VS_CNTL" type="a6xx_vpc_xs_cntl" variants="A8XX-" usage="draw"/> 3165 <reg32 offset="0x9301" name="VPC_GS_CNTL" type="a6xx_vpc_xs_cntl" variants="A8XX-" usage="draw"/> 3166 <reg32 offset="0x9302" name="VPC_DS_CNTL" type="a6xx_vpc_xs_cntl" variants="A8XX-" usage="draw"/> 3167 3168 <bitset name="a6xx_vpc_ps_cntl" inline="yes"> 3169 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/> 3170 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS --> 3171 <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/> 3172 <bitfield name="VARYING" pos="16" type="boolean"/> 3173 <bitfield name="VIEWIDLOC" low="24" high="31" type="uint"> 3174 <doc> 3175 This VPC location will be overwritten with 3176 ViewID when multiview is enabled. It's used when 3177 fragment shaders read ViewID. It's only 3178 strictly required for multi-position output, 3179 where the same VS invocation is used for all the 3180 views at once, but it can be used when multi-pos 3181 output is disabled too, to avoid having to pass 3182 ViewID through the VS. 3183 </doc> 3184 </bitfield> 3185 </bitset> 3186 3187 <reg32 offset="0x9304" name="VPC_PS_CNTL" type="a6xx_vpc_ps_cntl" variants="A6XX-A7XX" usage="draw"/> 3188 <reg32 offset="0x9303" name="VPC_PS_CNTL" type="a6xx_vpc_ps_cntl" variants="A8XX-" usage="draw"/> 3189 3190 <bitset name="a6xx_vpc_so_cntl" inline="yes"> 3191 <!-- 3192 It's offset by 1, and 0 means "disabled" 3193 --> 3194 <bitfield name="BUF0_STREAM" low="0" high="2" type="uint"/> 3195 <bitfield name="BUF1_STREAM" low="3" high="5" type="uint"/> 3196 <bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/> 3197 <bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/> 3198 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 3199 </bitset> 3200 3201 <reg32 offset="0x9305" name="VPC_SO_CNTL" type="a6xx_vpc_so_cntl" variants="A6XX-A7XX" usage="draw"/> 3202 <reg32 offset="0x9304" name="VPC_SO_CNTL" type="a6xx_vpc_so_cntl" variants="A8XX-" usage="draw"/> 3203 3204 <bitset name="a6xx_so_override" inline="yes"> 3205 <bitfield name="DISABLE" pos="0" type="boolean"/> 3206 </bitset> 3207 3208 <reg32 offset="0x9306" name="VPC_SO_OVERRIDE" type="a6xx_so_override" variants="A6XX-A7XX" usage="draw"/> 3209 <reg32 offset="0x9305" name="VPC_SO_OVERRIDE" type="a6xx_so_override" variants="A8XX-" usage="draw"/> 3210 3211 <reg32 offset="0x9807" name="PC_DGEN_SO_OVERRIDE" type="a6xx_so_override" variants="A7XX" usage="draw"/> 3212 <reg32 offset="0x9b0a" name="PC_DGEN_SO_OVERRIDE" type="a6xx_so_override" variants="A8XX-" usage="draw"/> 3213 3214 <reg32 offset="0x9307" name="VPC_PS_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX-A7XX" usage="draw"/> 3215 <reg32 offset="0x9306" name="VPC_PS_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX-" usage="draw"/> 3216 3217 <reg32 offset="0x9308" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="cmd"/> 3218 <reg32 offset="0x9309" name="VPC_ATTR_BUF_GMEM_BASE" variants="A7XX" type="hex" usage="cmd"/> 3219 3220 <reg32 offset="0x9314" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 3221 <reg32 offset="0x9315" name="VPC_ATTR_BUF_GMEM_BASE" variants="A8XX-" type="hex" usage="cmd"/> 3222 3223 <reg32 offset="0x9316" name="VPC_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 3224 <reg32 offset="0x9317" name="VPC_POS_BUF_GMEM_BASE" variants="A8XX-" type="hex" usage="cmd"/> 3225 3226 <reg32 offset="0x9318" name="VPC_BV_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 3227 <reg32 offset="0x9319" name="VPC_BV_POS_BUF_GMEM_BASE" variants="A8XX-" type="hex" usage="cmd"/> 3228 3229 <reg32 offset="0x9b09" name="PC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="cmd"/> 3230 <reg32 offset="0x9b16" name="PC_ATTR_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 3231 3232 <reg32 offset="0x9b17" name="PC_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 3233 <reg32 offset="0x9b18" name="PC_BV_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 3234 3235 <reg32 offset="0x930a" name="VPC_UNKNOWN_CNTL" variants="A7XX" usage="draw"/> 3236 <reg32 offset="0x9313" name="VPC_UNKNOWN_CNTL" variants="A8XX-" usage="draw"/> 3237 3238 <reg32 offset="0x9e17" name="PC_UNKNOWN_9E17" variants="A8XX-" usage="draw"/> 3239 3240 <reg32 offset="0x960a" name="VPC_FLATSHADE_MODE_CNTL" variants="A7XX"/> 3241 <reg32 offset="0x9741" name="VPC_FLATSHADE_MODE_CNTL" variants="A8XX-"/> 3242 3243 <!-- 0x9307-0x95ff invalid --> 3244 3245 <!-- TODO: 0x9600-0x97ff range --> 3246 <reg32 offset="0x9600" name="VPC_DBG_ECO_CNTL" variants="A6XX-A7XX" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask --> 3247 <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" usage="cmd" variants="A6XX"/> 3248 <reg32 offset="0x9680" name="VPC_DBG_ECO_CNTL" variants="A8XX-"/> 3249 <reg32 offset="0x9604" name="VPC_DBG_ECO_CNTL_2" variants="A8XX-"/> 3250 <reg32 offset="0x9742" name="VPC_DBG_ECO_CNTL_1" variants="A8XX-"/> 3251 <reg32 offset="0x9745" name="VPC_DBG_ECO_CNTL_3" variants="A8XX-"/> 3252 <reg32 offset="0x9602" name="VPC_LB_MODE_CNTL" pos="0" variants="A6XX-A7XX" usage="init"/> <!-- always 0x0 ? --> 3253 <reg32 offset="0x9740" name="VPC_LB_MODE_CNTL" pos="0" variants="A8XX-"/> 3254 <reg32 offset="0x9603" name="VPC_STATUS" low="0" high="26" variants="A6XX-A7XX"/> 3255 <reg32 offset="0x9600" name="VPC_STATUS" low="0" high="26" variants="A8XX-"/> 3256 <array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6" variants="A6XX"/> 3257 <array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX"/> 3258 <array offset="0x9670" name="VPC_PERFCTR_VPC_SEL_2" stride="1" length="12" variants="A8XX-"/> 3259 <array offset="0x9690" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A8XX-"/> 3260 <array offset="0x9750" name="VPC_PERFCTR_VPC_SEL_1" stride="1" length="12" variants="A8XX-"/> 3261 3262 <reg64 offset="0x9634" name="VPC_CONTEXT_SWITCH_SO_SAVE_ADDR" type="waddress" variants="A6XX-A7XX"/> 3263 <reg64 offset="0x9602" name="VPC_CONTEXT_SWITCH_SO_SAVE_ADDR" type="waddress" variants="A8XX-"/> 3264 3265 <reg32 offset="0x980b" name="PC_UNKNOWN_980B" variants="A8XX-"/> 3266 3267 <reg32 offset="0x9800" name="PC_HS_PARAM_0" low="0" high="5" type="uint" variants="A6XX-A7XX" usage="draw"/> 3268 <reg32 offset="0x9b10" name="PC_HS_PARAM_0" low="0" high="5" type="uint" variants="A8XX-" usage="draw"/> 3269 3270 <bitset name="a6xx_pc_hs_param_1" inline="yes"> 3271 <bitfield name="SIZE" low="0" high="10" type="uint"/> 3272 <bitfield name="UNK13" pos="13"/> 3273 </bitset> 3274 3275 <reg32 offset="0x9801" name="PC_HS_PARAM_1" type="a6xx_pc_hs_param_1" variants="A6XX-A7XX" usage="draw"/> 3276 <reg32 offset="0x9b11" name="PC_HS_PARAM_1" type="a6xx_pc_hs_param_1" variants="A8XX-" usage="draw"/> 3277 3278 <bitset name="a6xx_pc_ds_param" inline="yes"> 3279 <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/> 3280 <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/> 3281 </bitset> 3282 3283 <reg32 offset="0x9802" name="PC_DS_PARAM" type="a6xx_pc_ds_param" variants="A6XX-A7XX" usage="draw"/> 3284 <reg32 offset="0x9b12" name="PC_DS_PARAM" type="a6xx_pc_ds_param" variants="A8XX-" usage="draw"/> 3285 3286 <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" variants="A6XX-A7XX" usage="draw"/> 3287 <reg32 offset="0x9b15" name="PC_RESTART_INDEX" low="0" high="31" type="uint" variants="A8XX-" usage="draw"/> 3288 3289 <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" variants="A6XX-A7XX" usage="draw"/> 3290 <reg32 offset="0x9b00" name="PC_MODE_CNTL" low="0" high="14" variants="A8XX" usage="draw"/> 3291 3292 <reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" variants="A6XX" usage="draw"/> 3293 3294 <bitset name="a6xx_pc_ps_cntl" inline="yes"> 3295 <bitfield name="PRIMITIVEIDEN" pos="0" type="boolean"/> 3296 </bitset> 3297 3298 <reg32 offset="0x9806" name="PC_PS_CNTL" type="a6xx_pc_ps_cntl" variants="A6XX-A7XX" usage="draw"/> 3299 <reg32 offset="0x9b06" name="PC_PS_CNTL" type="a6xx_pc_ps_cntl" variants="A8XX-" usage="draw"/> 3300 3301 <bitset name="a6xx_pc_dgen_so_cntl" inline="yes"> 3302 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 3303 </bitset> 3304 3305 <!-- New in a6xx gen3+ --> 3306 <reg32 offset="0x9808" name="PC_DGEN_SO_CNTL" type="a6xx_pc_dgen_so_cntl" variants="A6XX-A7XX" usage="draw"/> 3307 <reg32 offset="0x9b0b" name="PC_DGEN_SO_CNTL" type="a6xx_pc_dgen_so_cntl" variants="A8XX-" usage="draw"/> 3308 3309 <bitset name="a6xx_pc_dgen_su_conservative_ras_cntl" inline="yes"> 3310 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 3311 </bitset> 3312 3313 <reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_pc_dgen_su_conservative_ras_cntl" variants="A6XX-A7XX"/> 3314 <reg32 offset="0x9b08" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_pc_dgen_su_conservative_ras_cntl" variants="A8XX-"/> 3315 3316 <reg32 offset="0x9b0c" name="PC_VS_INPUT_CNTL" variants="A8XX-" usage="draw"> 3317 <bitfield name="INSTR_CNT" low="0" high="5" type="uint"/> 3318 <bitfield name="SIDEBAND_CNT" low="6" high="8" type="uint"/> 3319 </reg32> 3320 3321 <!-- 0x9840 - 0x9842 are not readable --> 3322 <bitset name="a6xx_draw_initiator" inline="yes"> 3323 <bitfield name="STATE_ID" low="0" high="7"/> 3324 </bitset> 3325 3326 <reg32 offset="0x9840" name="PC_DRAW_INITIATOR" type="a6xx_draw_initiator" variants="A6XX-A7XX"/> 3327 <reg32 offset="0x9841" name="PC_KERNEL_INITIATOR" type="a6xx_draw_initiator" variants="A6XX-A7XX"/> 3328 3329 <reg32 offset="0x9800" name="PC_DRAW_INITIATOR" type="a6xx_draw_initiator" variants="A8XX-"/> 3330 <reg32 offset="0x9801" name="PC_KERNEL_INITIATOR" type="a6xx_draw_initiator" variants="A8XX-"/> 3331 3332 <bitset name="a6xx_event_initiator" inline="yes"> 3333 <!-- I think only the low bit is actually used? --> 3334 <bitfield name="STATE_ID" low="16" high="23"/> 3335 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 3336 </bitset> 3337 3338 <reg32 offset="0x9842" name="PC_EVENT_INITIATOR" type="a6xx_event_initiator" variants="A6XX-A7XX"/> 3339 <reg32 offset="0x9802" name="PC_EVENT_INITIATOR" type="a6xx_event_initiator" variants="A8XX-"/> 3340 3341 <!-- 3342 0x9880 written in a lot of places by SQE, same value gets written 3343 to control reg 0x12a. Set by CP_SET_MARKER, so lets name it after 3344 that 3345 --> 3346 <reg32 offset="0x9880" name="PC_MARKER"/> 3347 3348 <!-- 0x9843-0x997f invalid --> 3349 3350 <reg32 offset="0x9981" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX" usage="draw"/> 3351 <reg32 offset="0x9809" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A7XX" usage="draw"/> 3352 <reg32 offset="0x9812" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX" usage="draw"/> 3353 3354 <reg32 offset="0x9884" name="PC_HS_PATCH_SIZE" variants="A7XX" usage="cmd"/> 3355 <reg32 offset="0x9813" name="PC_HS_PATCH_SIZE" variants="A8XX-" usage="cmd"/> 3356 3357 <!-- Both are a750+. 3358 Probably needed to correctly overlap execution of several draws. 3359 --> 3360 <reg32 offset="0x9885" name="PC_HS_BUFFER_SIZE" variants="A7XX" usage="cmd"/> 3361 <reg32 offset="0x9814" name="PC_HS_BUFFER_SIZE" variants="A8XX-" usage="cmd"/> 3362 <!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of 3363 this additional space is not known. 3364 --> 3365 <reg32 offset="0x9886" name="PC_TF_BUFFER_SIZE" variants="A7XX" usage="cmd"/> 3366 <reg32 offset="0x9815" name="PC_TF_BUFFER_SIZE" variants="A8XX-" usage="cmd"/> 3367 3368 <!-- 0x9982-0x9aff invalid --> 3369 3370 <reg32 offset="0x9b00" name="PC_CNTL" type="a6xx_pc_cntl" variants="A6XX-A7XX" usage="draw"/> 3371 <reg32 offset="0x9b01" name="PC_CNTL" type="a6xx_pc_cntl" variants="A8XX-" usage="draw"/> 3372 3373 <bitset name="a6xx_pc_xs_cntl" inline="yes"> 3374 <doc> 3375 num of varyings plus four for gl_Position (plus one if gl_PointSize) 3376 plus # of transform-feedback (streamout) varyings if using the 3377 hw streamout (rather than stg instructions in shader) 3378 </doc> 3379 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/> 3380 <bitfield name="PSIZE" pos="8" type="boolean"/> 3381 <bitfield name="LAYER" pos="9" type="boolean"/> 3382 <bitfield name="VIEW" pos="10" type="boolean"/> 3383 <!-- note: PC_VS_CNTL doesn't have the PRIMITIVE_ID bit --> 3384 <!-- since HS can't output anything, only PRIMITIVE_ID is valid --> 3385 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/> 3386 <bitfield name="CLIP_MASK" low="16" high="23" type="uint"/> 3387 <bitfield name="SHADINGRATE" pos="24" type="boolean" variants="A7XX-"/> 3388 </bitset> 3389 3390 <reg32 offset="0x9b01" name="PC_VS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="draw"/> 3391 <reg32 offset="0x9b02" name="PC_GS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="draw"/> 3392 <reg32 offset="0x9b03" name="PC_HS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="draw"/> 3393 <reg32 offset="0x9b04" name="PC_DS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="draw"/> 3394 3395 <reg32 offset="0x9b02" name="PC_VS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="draw"/> 3396 <reg32 offset="0x9b03" name="PC_GS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="draw"/> 3397 <reg32 offset="0x9b04" name="PC_HS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="draw"/> 3398 <reg32 offset="0x9b05" name="PC_DS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="draw"/> 3399 3400 <reg32 offset="0x9b05" name="PC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A6XX-A7XX" usage="draw"/> 3401 <reg32 offset="0x9b13" name="PC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A8XX-" usage="draw"/> 3402 3403 <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6" variants="A6XX" usage="draw"> 3404 <doc> 3405 size in vec4s of per-primitive storage for gs. TODO: not actually in VPC 3406 </doc> 3407 <bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/> 3408 </reg32> 3409 3410 <reg32 offset="0x9b07" name="PC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A6XX-A7XX" usage="draw"/> 3411 <reg32 offset="0x9b09" name="PC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A8XX-" usage="draw"/> 3412 <!-- mask of enabled views, doesn't exist on A630 --> 3413 <reg32 offset="0x9b08" name="PC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A6XX-A7XX" usage="draw"/> 3414 <reg32 offset="0x9b0d" name="PC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A8XX-" usage="draw"/> 3415 <!-- 0x9b09-0x9bff invalid --> 3416 <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD"> 3417 <!-- special register (but note first 8 bits can be written/read) --> 3418 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 3419 <bitfield name="STATE_ID" low="8" high="15"/> 3420 </reg32> 3421 3422 <reg32 offset="0x9e50" name="PC_CHICKEN_BITS_1" variants="A8XX-"/> 3423 <reg32 offset="0x9f20" name="PC_CHICKEN_BITS_2" variants="A8XX-"/> 3424 <reg32 offset="0x9e22" name="PC_CHICKEN_BITS_3" variants="A8XX-"/> 3425 <reg32 offset="0x9e23" name="PC_CHICKEN_BITS_4" variants="A8XX-"/> 3426 <reg32 offset="0x9f23" name="PC_CHICKEN_BITS_5" variants="A8XX-"/> 3427 3428 <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL" variants="A6XX-A7XX"/> 3429 <reg32 offset="0x9e53" name="PC_DBG_ECO_CNTL" variants="A8XX-"/> 3430 <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 3431 <reg64 offset="0x9e04" name="PC_DMA_BASE" type="address" variants="A6XX-A7XX"/> 3432 <reg32 offset="0x9e06" name="PC_DMA_OFFSET" type="uint" variants="A6XX-A7XX"/> 3433 <reg32 offset="0x9e07" name="PC_DMA_SIZE" type="uint" variants="A6XX-A7XX"/> 3434 3435 <reg64 offset="0x9e06" name="PC_DMA_BASE" type="address" variants="A8XX-"/> 3436 <reg32 offset="0x9e08" name="PC_DMA_OFFSET" type="uint" variants="A8XX-"/> 3437 <reg32 offset="0x9e09" name="PC_DMA_SIZE" type="uint" variants="A8XX-"/> 3438 3439 <reg64 offset="0x9e08" name="PC_TESS_BASE" variants="A6XX" type="waddress" align="32" usage="cmd"/> 3440 <reg64 offset="0x9810" name="PC_TESS_BASE" variants="A7XX" type="waddress" align="32" usage="cmd"/> 3441 <reg64 offset="0x9816" name="PC_TESS_BASE" variants="A8XX-" type="waddress" align="32" usage="cmd"/> 3442 3443 <reg32 offset="0x9e0b" name="PC_DRAWCALL_CNTL" type="vgt_draw_initiator_a4xx" variants="A6XX-A7XX"> 3444 <doc> 3445 Possibly not really "initiating" the draw but the layout is similar 3446 to VGT_DRAW_INITIATOR on older gens 3447 </doc> 3448 </reg32> 3449 <reg32 offset="0x9e0c" name="PC_DRAWCALL_INSTANCE_NUM" type="uint" variants="A6XX-A7XX"/> 3450 <reg32 offset="0x9e0d" name="PC_DRAWCALL_SIZE" type="uint" variants="A6XX-A7XX"/> 3451 3452 <reg32 offset="0x9e00" name="PC_DRAWCALL_CNTL" type="vgt_draw_initiator_a4xx" variants="A8XX-"/> 3453 <reg32 offset="0x9e01" name="PC_DRAWCALL_INSTANCE_NUM" type="uint" variants="A8XX-"/> 3454 <reg32 offset="0x9e02" name="PC_DRAWCALL_SIZE" type="uint" variants="A8XX-"/> 3455 3456 <!-- These match the contents of CP_SET_BIN_DATA (not written directly) --> 3457 <bitset name="a6xx_pc_vis_stream_cntl" inline="yes"> 3458 <bitfield name="UNK0" low="0" high="15"/> 3459 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 3460 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 3461 </bitset> 3462 3463 <reg32 offset="0x9e11" name="PC_VIS_STREAM_CNTL" type="a6xx_pc_vis_stream_cntl" variants="A6XX-A7XX"/> 3464 <reg64 offset="0x9e12" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/> 3465 <reg64 offset="0x9e14" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/> 3466 3467 <reg32 offset="0x9e0a" name="PC_AUTO_VERTEX_STRIDE"/> 3468 <reg32 offset="0x9e0d" name="PC_VIS_STREAM_CNTL" type="a6xx_pc_vis_stream_cntl" variants="A8XX-"/> 3469 <reg64 offset="0x9e0e" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A8XX-"/> 3470 <reg64 offset="0x9e10" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A8XX-"/> 3471 3472 <bitset name="a6xx_pc_drawcall_cntl_override" inline="yes"> 3473 <doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc> 3474 <bitfield name="OVERRIDE" pos="0" type="boolean"/> 3475 </bitset> 3476 3477 <reg32 offset="0x9e1c" name="PC_DRAWCALL_CNTL_OVERRIDE" type="a6xx_pc_drawcall_cntl_override" variants="A6XX-A7XX"/> 3478 <reg32 offset="0x9e04" name="PC_DRAWCALL_CNTL_OVERRIDE" type="a6xx_pc_drawcall_cntl_override" variants="A8XX-"/> 3479 3480 <reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="init"/> 3481 3482 <array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8" variants="A6XX"/> 3483 <array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX"/> 3484 <array offset="0x9e30" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A8XX-"/> 3485 <array offset="0x9f00" name="PC_SLICE_PERFCTR_PC_SEL" stride="1" length="16" variants="A8XX-"/> 3486 3487 <!-- always 0x0 --> 3488 <reg32 offset="0x9e72" name="PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE" variants="A6XX-A7XX" usage="init"/> 3489 <reg32 offset="0x9e63" name="PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE" variants="A8XX-"/> 3490 <reg32 offset="0x9e64" name="PC_CONTEXT_SWITCH_STABILIZE_CNTL_1" variants="A8XX-"/> 3491 3492 <reg32 offset="0xa000" name="VFD_CNTL_0" usage="draw"> 3493 <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/> 3494 <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/> 3495 </reg32> 3496 <reg32 offset="0xa001" name="VFD_CNTL_1" usage="draw"> 3497 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/> 3498 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/> 3499 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/> 3500 <!-- only used for VS in non-multi-position-output case --> 3501 <bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/> 3502 </reg32> 3503 <reg32 offset="0xa002" name="VFD_CNTL_2" usage="draw"> 3504 <bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid"> 3505 <doc> 3506 This is the ID of the current patch within the 3507 subdraw, used to calculate the offset of the 3508 patch within the HS->DS buffers. When a draw is 3509 split into multiple subdraws then this differs 3510 from gl_PrimitiveID on the second, third, etc. 3511 subdraws. 3512 </doc> 3513 </bitfield> 3514 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/> 3515 </reg32> 3516 <reg32 offset="0xa003" name="VFD_CNTL_3" usage="draw"> 3517 <bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/> 3518 <bitfield name="REGID_DSRELPATCHID" low="8" high="15" type="a3xx_regid"/> 3519 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/> 3520 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/> 3521 </reg32> 3522 <reg32 offset="0xa004" name="VFD_CNTL_4" usage="draw"> 3523 <bitfield name="REGID_DSVIEWID" low="0" high="7" type="a3xx_regid"/> 3524 </reg32> 3525 <reg32 offset="0xa005" name="VFD_CNTL_5" usage="draw"> 3526 <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/> 3527 <bitfield name="REGID_GSVIEWID" low="8" high="15" type="a3xx_regid"/> 3528 </reg32> 3529 <reg32 offset="0xa006" name="VFD_CNTL_6" usage="draw"> 3530 <!-- 3531 True if gl_PrimitiveID is read via the FS 3532 --> 3533 <bitfield name="PRIMID4PSEN" pos="0" type="boolean"/> 3534 </reg32> 3535 3536 <reg32 offset="0xa007" name="VFD_RENDER_MODE" usage="cmd"> 3537 <bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/> 3538 </reg32> 3539 3540 <reg32 offset="0xa008" name="VFD_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" usage="draw"/> 3541 <reg32 offset="0xa009" name="VFD_MODE_CNTL" usage="cmd"> 3542 <!-- add VFD_INDEX_OFFSET to REGID4VTX --> 3543 <bitfield name="VERTEX" pos="0" type="boolean"/> 3544 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST --> 3545 <bitfield name="INSTANCE" pos="1" type="boolean"/> 3546 </reg32> 3547 3548 <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET" usage="draw"/> 3549 <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET" usage="draw"/> 3550 <array offset="0xa010" name="VFD_VERTEX_BUFFER" stride="4" length="32" usage="draw"> 3551 <reg64 offset="0x0" name="BASE" type="address" align="1"/> 3552 <reg32 offset="0x2" name="SIZE" type="uint"/> 3553 <reg32 offset="0x3" name="STRIDE" low="0" high="11" type="uint"/> 3554 </array> 3555 <array offset="0xa090" name="VFD_FETCH_INSTR" stride="2" length="32" usage="draw"> 3556 <reg32 offset="0x0" name="INSTR"> 3557 <!-- IDX and byte OFFSET into VFD_VERTEX_BUFFER --> 3558 <bitfield name="IDX" low="0" high="4" type="uint"/> 3559 <bitfield name="OFFSET" low="5" high="16"/> 3560 <bitfield name="INSTANCED" pos="17" type="boolean"/> 3561 <bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/> 3562 <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/> 3563 <bitfield name="UNK30" pos="30" type="boolean"/> 3564 <bitfield name="FLOAT" pos="31" type="boolean"/> 3565 </reg32> 3566 <reg32 offset="0x1" name="STEP_RATE" type="uint"/> 3567 </array> 3568 <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32" usage="draw"> 3569 <reg32 offset="0x0" name="INSTR"> 3570 <bitfield name="WRITEMASK" low="0" high="3" type="hex"/> 3571 <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/> 3572 </reg32> 3573 </array> 3574 3575 <reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" variants="A6XX" usage="draw"/> 3576 3577 <reg32 offset="0xa600" name="VFD_DBG_ECO_CNTL" variants="A7XX-" usage="init"/> 3578 3579 <reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 3580 <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8" variants="A6XX"/> 3581 <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16" variants="A7XX-"/> 3582 <reg32 offset="0xa639" name="VFD_CB_BV_THRESHOLD" variants="A8XX-"/> 3583 <reg32 offset="0xa63a" name="VFD_CB_BR_THRESHOLD" variants="A8XX-"/> 3584 <reg32 offset="0xa63b" name="VFD_CB_BUSY_REQ_CNT" variants="A8XX-"/> 3585 <reg32 offset="0xa63c" name="VFD_CB_LP_REQ_CNT" variants="A8XX-"/> 3586 3587 <!-- 3588 Note: this seems to always be paired with another bit in another 3589 block. 3590 --> 3591 <enum name="a6xx_threadsize"> 3592 <value value="0" name="THREAD64"/> 3593 <value value="1" name="THREAD128"/> 3594 </enum> 3595 3596 <bitset name="a6xx_sp_xs_cntl_0" inline="yes"> 3597 <!-- if set to SINGLE, only use 1 concurrent wave on each SP --> 3598 <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/> 3599 <!-- 3600 When b31 set we just see FULLREGFOOTPRINT set. The pattern of 3601 used registers is a bit odd too: 3602 - used (half): 0-15 68-179 (cnt=128, max=179) 3603 - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127> 3604 whereas we usually see a (mostly) contiguous range of regs used. But if 3605 I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)), 3606 then: 3607 - used (merged): 0-191 (cnt=192, max=191) 3608 So I think if b31 is set, then the half precision registers overlap 3609 the full precision registers. (Which seems like a pretty sensible 3610 feature, actually I'm not sure when you *wouldn't* want to use that, 3611 since it gives register allocation more flexibility) 3612 --> 3613 <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/> 3614 <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/> 3615 <!-- seems to be nesting level for flow control:.. --> 3616 <bitfield name="BRANCHSTACK" low="13" high="19" type="uint"/> 3617 3618 <!-- gen8: --> 3619 <bitfield name="FULLREGFOOTPRINT_LSB" pos="27" type="uint" variants="A8XX-"/> 3620 <bitfield name="HALFREGFOOTPRINT_LSB" pos="30" type="uint" variants="A8XX-"/> 3621 </bitset> 3622 3623 <bitset name="a6xx_sp_xs_config" inline="yes"> 3624 <!-- 3625 Each of these are set if the given resource type is used 3626 with the Vulkan/bindless binding model. 3627 --> 3628 <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/> 3629 <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/> 3630 <bitfield name="BINDLESS_UAV" pos="2" type="boolean"/> 3631 <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/> 3632 3633 <bitfield name="ENABLED" pos="8" type="boolean"/> 3634 <!-- 3635 number of textures and samplers.. these might be swapped, with GL I 3636 always see the same value for both. 3637 --> 3638 <bitfield name="NTEX" low="9" high="16" type="uint"/> 3639 <bitfield name="NSAMP" low="17" high="21" type="uint"/> 3640 <bitfield name="NUAV" low="22" high="28" type="uint"/> 3641 </bitset> 3642 3643 <bitset name="a6xx_sp_xs_output_cntl" inline="yes"> 3644 <!-- # of VS outputs including pos/psize --> 3645 <bitfield name="OUT" low="0" high="5" type="uint"/> 3646 </bitset> 3647 3648 <reg32 offset="0xa800" name="SP_VS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="draw"> 3649 <!-- 3650 This field actually controls all geometry stages. TCS, TES, and 3651 GS must have the same mergedregs setting as VS. 3652 --> 3653 <bitfield name="MERGEDREGS" pos="20" type="boolean"/> 3654 <!-- 3655 Creates a separate preamble-only thread? 3656 3657 Early preamble has the following limitations: 3658 - Only shared, a1, and consts regs could be used 3659 (accessing other regs would result in GPU fault); 3660 - No cat5/cat6, only stc/ldc variants are working; 3661 - Values writen to shared regs are not accessible by the rest 3662 of the shader; 3663 - Instructions before shps are also considered to be a part of 3664 early preamble; 3665 3666 Note, for all shaders from d3d11 games blob produced preambles 3667 compatible with early preamble mode. 3668 --> 3669 <bitfield name="EARLYPREAMBLE" pos="21" type="boolean"/> 3670 </reg32> 3671 <!-- bitmask of true/false conditions for VS brac.N instructions, 3672 bit N corresponds to brac.N --> 3673 <reg32 offset="0xa801" name="SP_VS_BOOLEAN_CF_MASK" type="hex"/> 3674 <!-- # of VS outputs including pos/psize --> 3675 <reg32 offset="0xa802" name="SP_VS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="draw"/> 3676 <array offset="0xa803" name="SP_VS_OUTPUT" stride="1" length="16" usage="draw"> 3677 <reg32 offset="0x0" name="REG"> 3678 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 3679 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> 3680 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> 3681 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 3682 </reg32> 3683 </array> 3684 <!-- 3685 Starting with a5xx, position/psize outputs from shader end up in the 3686 SP_VS_OUTPUT map, with highest OUTLOCn position. (Generally they are 3687 the last entries too, except when gl_PointCoord is used, blob inserts 3688 an extra varying after, but with a lower OUTLOC position. If present, 3689 psize is last, preceded by position. 3690 --> 3691 <array offset="0xa813" name="SP_VS_VPC_DEST" stride="1" length="8" usage="draw"> 3692 <reg32 offset="0x0" name="REG"> 3693 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 3694 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> 3695 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> 3696 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> 3697 </reg32> 3698 </array> 3699 3700 <bitset name="a6xx_sp_xs_pvt_mem_param" inline="yes"> 3701 <bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9"> 3702 <doc>The size of memory that ldp/stp can address.</doc> 3703 </bitfield> 3704 <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31"> 3705 <doc> 3706 Seems to be the same as a3xx. The maximum stack 3707 size in units of 4 calls, so a call depth of 7 3708 would result in a value of 2. 3709 TODO: What's the actual size per call, i.e. the 3710 size of the PC? a3xx docs say it's 16 bits 3711 there, but the length register now takes 28 bits 3712 so it's probably been bumped to 32 bits. 3713 </doc> 3714 </bitfield> 3715 </bitset> 3716 3717 <bitset name="a6xx_sp_xs_pvt_mem_size" inline="yes"> 3718 <bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/> 3719 <bitfield name="PERWAVEMEMLAYOUT" pos="31" type="boolean"> 3720 <doc> 3721 There are four indices used to compute the 3722 private memory location for an access: 3723 3724 - stp/ldp offset 3725 - fiber id 3726 - wavefront id (a swizzled version of what "getwid" returns) 3727 - SP ID (the same as what "getspid" returns) 3728 3729 The stride for the SP ID is always set by 3730 TOTALPVTMEMSIZE. In the per-wave layout, the 3731 indices are used in this order: 3732 3733 - offset % 4 (offset within dword) 3734 - fiber id 3735 - offset / 4 3736 - wavefront id 3737 - SP ID 3738 3739 and the stride for the wavefront ID is 3740 MEMSIZEPERITEM, multiplied by 128 (fibers per 3741 wavefront). In the per-fiber layout, the indices 3742 are used in this order: 3743 3744 - offset 3745 - fiber id % 4 3746 - wavefront id 3747 - fiber id / 4 3748 - SP ID 3749 3750 and the stride for the fiber id/wavefront id 3751 combo is MEMSIZEPERITEM. 3752 3753 Note: Accesses of more than 1 dword do not work 3754 with per-fiber layout. The blob will fall back 3755 to per-wave instead. 3756 </doc> 3757 </bitfield> 3758 </bitset> 3759 3760 <bitset name="a6xx_sp_xs_pvt_mem_stack_offset" inline="yes"> 3761 <doc> 3762 This seems to be be the equivalent of HWSTACKOFFSET in 3763 a3xx. The ldp/stp offset formula above isn't affected by 3764 HWSTACKSIZEPERTHREAD at all, so the HW return address 3765 stack seems to be after all the normal per-SP private 3766 memory. 3767 </doc> 3768 <bitfield name="OFFSET" low="0" high="18" shr="11"/> 3769 </bitset> 3770 3771 <bitset name="a6xx_sp_xs_hysteresis" inline="yes"> 3772 <doc>Same on a6xx/a7xx, UMD should not need to write this</doc> 3773 </bitset> 3774 3775 <bitset name="a8xx_sp_xs_hysteresis" inline="yes"> 3776 <doc>UMD needs to write in some cases</doc> 3777 <!-- seen 0x400, 0xc00, 0x1000, 0x1c00, 0x1000, 0x2000, 0x3000 --> 3778 </bitset> 3779 3780 <reg32 offset="0xa81b" name="SP_VS_PROGRAM_COUNTER_OFFSET" type="uint" usage="draw"/> 3781 <reg64 offset="0xa81c" name="SP_VS_BASE" type="address" align="32" usage="draw"/> 3782 <reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="draw"/> 3783 <reg64 offset="0xa81f" name="SP_VS_PVT_MEM_BASE" type="waddress" align="32" usage="draw"/> 3784 <reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="draw"/> 3785 <reg32 offset="0xa822" name="SP_VS_TSIZE" low="0" high="7" type="uint" usage="draw"/> 3786 <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config" usage="draw"/> 3787 <reg32 offset="0xa824" name="SP_VS_INSTR_SIZE" low="0" high="27" type="uint" usage="draw"/> 3788 <reg32 offset="0xa825" name="SP_VS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="draw"/> 3789 <reg32 offset="0xa826" name="SP_VS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 3790 <reg32 offset="0xa826" name="SP_VS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 3791 <reg32 offset="0xa82d" name="SP_VS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 3792 3793 <reg32 offset="0xa830" name="SP_HS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="draw"> 3794 <!-- There is no mergedregs bit, that comes from the VS. --> 3795 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 3796 </reg32> 3797 <!-- 3798 Total size of local storage in dwords divided by the wave size. 3799 The maximum value is 64. With the wave size being always 64 for HS, 3800 the maximum size of local storage should be: 3801 64 (wavesize) * 64 (SP_HS_CNTL_1) * 4 = 16k 3802 --> 3803 <reg32 offset="0xa831" name="SP_HS_CNTL_1" low="0" high="7" type="uint" usage="draw"/> 3804 <reg32 offset="0xa832" name="SP_HS_BOOLEAN_CF_MASK" type="hex" usage="draw"/> 3805 3806 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 3807 <reg32 offset="0xa833" name="SP_HS_PROGRAM_COUNTER_OFFSET" type="uint" usage="draw"/> 3808 <reg64 offset="0xa834" name="SP_HS_BASE" type="address" align="32" usage="draw"/> 3809 <reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="draw"/> 3810 <reg64 offset="0xa837" name="SP_HS_PVT_MEM_BASE" type="waddress" align="32" usage="draw"/> 3811 <reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="draw"/> 3812 <reg32 offset="0xa83a" name="SP_HS_TSIZE" low="0" high="7" type="uint" usage="draw"/> 3813 <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config" usage="draw"/> 3814 <reg32 offset="0xa83c" name="SP_HS_INSTR_SIZE" low="0" high="27" type="uint" usage="draw"/> 3815 <reg32 offset="0xa83d" name="SP_HS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="draw"/> 3816 <reg32 offset="0xa83e" name="SP_HS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 3817 <reg32 offset="0xa83e" name="SP_HS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 3818 <reg32 offset="0xa82f" name="SP_HS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 3819 3820 <reg32 offset="0xa840" name="SP_DS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="draw"> 3821 <!-- There is no mergedregs bit, that comes from the VS. --> 3822 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 3823 </reg32> 3824 <reg32 offset="0xa841" name="SP_DS_BOOLEAN_CF_MASK" type="hex"/> 3825 3826 <!-- TODO: exact same layout as 0xa802-0xa81a --> 3827 <reg32 offset="0xa842" name="SP_DS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="draw"/> 3828 <array offset="0xa843" name="SP_DS_OUTPUT" stride="1" length="16" usage="draw"> 3829 <reg32 offset="0x0" name="REG"> 3830 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 3831 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> 3832 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> 3833 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 3834 </reg32> 3835 </array> 3836 <array offset="0xa853" name="SP_DS_VPC_DEST" stride="1" length="8" usage="draw"> 3837 <reg32 offset="0x0" name="REG"> 3838 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 3839 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> 3840 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> 3841 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> 3842 </reg32> 3843 </array> 3844 3845 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 3846 <reg32 offset="0xa85b" name="SP_DS_PROGRAM_COUNTER_OFFSET" type="uint" usage="draw"/> 3847 <reg64 offset="0xa85c" name="SP_DS_BASE" type="address" align="32" usage="draw"/> 3848 <reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="draw"/> 3849 <reg64 offset="0xa85f" name="SP_DS_PVT_MEM_BASE" type="waddress" align="32" usage="draw"/> 3850 <reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="draw"/> 3851 <reg32 offset="0xa862" name="SP_DS_TSIZE" low="0" high="7" type="uint" usage="draw"/> 3852 <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config" usage="draw"/> 3853 <reg32 offset="0xa864" name="SP_DS_INSTR_SIZE" low="0" high="27" type="uint" usage="draw"/> 3854 <reg32 offset="0xa865" name="SP_DS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="draw"/> 3855 <reg32 offset="0xa866" name="SP_DS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 3856 <reg32 offset="0xa866" name="SP_DS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 3857 <reg32 offset="0xa868" name="SP_DS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 3858 3859 <reg32 offset="0xa870" name="SP_GS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="draw"> 3860 <!-- There is no mergedregs bit, that comes from the VS. --> 3861 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 3862 </reg32> 3863 <reg32 offset="0xa871" name="SP_GS_CNTL_1" low="0" high="7" type="uint" usage="draw"> 3864 <doc> 3865 Normally the size of the output of the last stage in 3866 dwords. It should be programmed as follows: 3867 3868 size less than 63 - size 3869 size of 63 (?) or 64 - 63 3870 size greater than 64 - 64 3871 3872 What to program when the size is 61-63 is a guess, but 3873 both the blob and ir3 align the size to 4 dword's so it 3874 doesn't matter in practice. 3875 </doc> 3876 </reg32> 3877 <reg32 offset="0xa872" name="SP_GS_BOOLEAN_CF_MASK" type="hex" usage="draw"/> 3878 3879 <!-- TODO: exact same layout as 0xa802-0xa81a --> 3880 <reg32 offset="0xa873" name="SP_GS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="draw"> 3881 <!-- FLAGS_REGID only for GS --> 3882 <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/> 3883 </reg32> 3884 <array offset="0xa874" name="SP_GS_OUTPUT" stride="1" length="16" usage="draw"> 3885 <reg32 offset="0x0" name="REG"> 3886 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 3887 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> 3888 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> 3889 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 3890 </reg32> 3891 </array> 3892 3893 <array offset="0xa884" name="SP_GS_VPC_DEST" stride="1" length="8" usage="draw"> 3894 <reg32 offset="0x0" name="REG"> 3895 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 3896 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> 3897 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> 3898 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> 3899 </reg32> 3900 </array> 3901 3902 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 3903 <reg32 offset="0xa88c" name="SP_GS_PROGRAM_COUNTER_OFFSET" type="uint" usage="draw"/> 3904 <reg64 offset="0xa88d" name="SP_GS_BASE" type="address" align="32" usage="draw"/> 3905 <reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="draw"/> 3906 <reg64 offset="0xa890" name="SP_GS_PVT_MEM_BASE" type="waddress" align="32" usage="draw"/> 3907 <reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="draw"/> 3908 <reg32 offset="0xa893" name="SP_GS_TSIZE" low="0" high="7" type="uint" usage="draw"/> 3909 <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config" usage="draw"/> 3910 <reg32 offset="0xa895" name="SP_GS_INSTR_SIZE" low="0" high="27" type="uint" usage="draw"/> 3911 <reg32 offset="0xa896" name="SP_GS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="draw"/> 3912 <reg32 offset="0xa897" name="SP_GS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 3913 <reg32 offset="0xa897" name="SP_GS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 3914 <reg32 offset="0xa899" name="SP_GS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 3915 3916 <reg64 offset="0xa8a0" name="SP_VS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 3917 <reg64 offset="0xa8a2" name="SP_HS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 3918 <reg64 offset="0xa8a4" name="SP_DS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 3919 <reg64 offset="0xa8a6" name="SP_GS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 3920 <reg64 offset="0xa8a8" name="SP_VS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 3921 <reg64 offset="0xa8aa" name="SP_HS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 3922 <reg64 offset="0xa8ac" name="SP_DS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 3923 <reg64 offset="0xa8ae" name="SP_GS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 3924 3925 <!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 --> 3926 3927 <reg32 offset="0xa980" name="SP_PS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="draw"> 3928 <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> 3929 <bitfield name="UNK21" pos="21" type="boolean"/> 3930 <bitfield name="VARYING" pos="22" type="boolean"/> 3931 <bitfield name="LODPIXMASK" pos="23" type="boolean"> 3932 <doc> 3933 Enable ALL helper invocations in a quad. Necessary for 3934 fine derivatives and quad subgroup ops. 3935 </doc> 3936 </bitfield> 3937 <bitfield name="INOUTREGOVERLAP" pos="24" type="boolean"/> 3938 <bitfield name="UNK25" pos="25" type="boolean"/> 3939 <bitfield name="PIXLODENABLE" pos="26" type="boolean"> 3940 <doc> 3941 Enable helper invocations. Enables 3 out of 4 fragments, 3942 because the coarse derivatives only use half of the quad 3943 and so one pixel's value is always unused. 3944 </doc> 3945 </bitfield> 3946 <bitfield name="EARLYPREAMBLE" pos="28" type="boolean"/> 3947 <bitfield name="MERGEDREGS" pos="31" type="boolean"/> 3948 </reg32> 3949 <reg32 offset="0xa981" name="SP_PS_BOOLEAN_CF_MASK" type="hex"/> 3950 <reg32 offset="0xa982" name="SP_PS_PROGRAM_COUNTER_OFFSET" type="uint" usage="draw"/> 3951 <reg64 offset="0xa983" name="SP_PS_BASE" type="address" align="32" usage="draw"/> 3952 <reg32 offset="0xa985" name="SP_PS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="draw"/> 3953 <reg64 offset="0xa986" name="SP_PS_PVT_MEM_BASE" type="waddress" align="32" usage="draw"/> 3954 <reg32 offset="0xa988" name="SP_PS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="draw"/> 3955 3956 <bitset name="a6xx_sp_blend_cntl" inline="yes"> 3957 <!-- per-mrt enable bit --> 3958 <bitfield name="ENABLE_BLEND" low="0" high="7"/> 3959 <bitfield name="INDEPENDENT_BLEND_EN" pos="8" type="boolean"/> 3960 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> 3961 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> 3962 </bitset> 3963 3964 <reg32 offset="0xa989" name="SP_BLEND_CNTL" type="a6xx_sp_blend_cntl" variants="A6XX-A7XX" usage="draw"/> 3965 <reg32 offset="0xa989" name="SP_BLEND_CNTL" type="a6xx_sp_blend_cntl" variants="A8XX-" usage="draw"> 3966 <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean" variants="A8XX-"/> 3967 </reg32> 3968 3969 <reg32 offset="0xa98a" name="SP_SRGB_CNTL" usage="draw"> 3970 <!-- Same as RB_SRGB_CNTL --> 3971 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/> 3972 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/> 3973 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/> 3974 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/> 3975 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/> 3976 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/> 3977 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/> 3978 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> 3979 </reg32> 3980 <reg32 offset="0xa98b" name="SP_PS_OUTPUT_MASK" usage="draw"> 3981 <bitfield name="RT0" low="0" high="3"/> 3982 <bitfield name="RT1" low="4" high="7"/> 3983 <bitfield name="RT2" low="8" high="11"/> 3984 <bitfield name="RT3" low="12" high="15"/> 3985 <bitfield name="RT4" low="16" high="19"/> 3986 <bitfield name="RT5" low="20" high="23"/> 3987 <bitfield name="RT6" low="24" high="27"/> 3988 <bitfield name="RT7" low="28" high="31"/> 3989 </reg32> 3990 <reg32 offset="0xa98c" name="SP_PS_OUTPUT_CNTL" usage="draw"> 3991 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> 3992 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/> 3993 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/> 3994 <bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/> 3995 </reg32> 3996 <reg32 offset="0xa98d" name="SP_PS_MRT_CNTL" usage="draw"> 3997 <bitfield name="MRT" low="0" high="3" type="uint"/> 3998 </reg32> 3999 4000 <array offset="0xa98e" name="SP_PS_OUTPUT" stride="1" length="8" usage="draw"> 4001 <doc>per MRT</doc> 4002 <reg32 offset="0x0" name="REG"> 4003 <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/> 4004 <bitfield name="HALF_PRECISION" pos="8" type="boolean"/> 4005 </reg32> 4006 </array> 4007 4008 <array offset="0xa996" name="SP_PS_MRT" stride="1" length="8" usage="draw"> 4009 <reg32 offset="0" name="REG"> 4010 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 4011 <bitfield name="COLOR_SINT" pos="8" type="boolean"/> 4012 <bitfield name="COLOR_UINT" pos="9" type="boolean"/> 4013 <bitfield name="UNK10" pos="10" type="boolean"/> 4014 </reg32> 4015 </array> 4016 4017 <reg32 offset="0xa99e" name="SP_PS_INITIAL_TEX_LOAD_CNTL" usage="draw"> 4018 <bitfield name="COUNT" low="0" high="2" type="uint"/> 4019 <bitfield name="IJ_WRITE_DISABLE" pos="3" type="boolean"/> 4020 <doc> 4021 Similar to "(eq)" flag but disables helper invocations 4022 after the texture prefetch. 4023 </doc> 4024 <bitfield name="ENDOFQUAD" pos="4" type="boolean" /> 4025 <doc> 4026 Bypass writing to regs and overwrite output with color from 4027 CONSTSLOTID const regs. 4028 </doc> 4029 <bitfield name="WRITE_COLOR_TO_OUTPUT" pos="5" type="boolean"/> 4030 <bitfield name="CONSTSLOTID" low="6" high="14" type="uint"/> 4031 <!-- Blob never uses it --> 4032 <bitfield name="CONSTSLOTID4COORD" low="16" high="24" type="uint" variants="A7XX-"/> 4033 </reg32> 4034 <array offset="0xa99f" name="SP_PS_INITIAL_TEX_LOAD" stride="1" length="4" variants="A6XX" usage="draw"> 4035 <reg32 offset="0" name="CMD" variants="A6XX"> 4036 <bitfield name="SRC" low="0" high="6" type="uint"/> 4037 <bitfield name="SAMP_ID" low="7" high="10" type="uint"/> 4038 <bitfield name="TEX_ID" low="11" high="15" type="uint"/> 4039 <bitfield name="DST" low="16" high="21" type="a3xx_regid"/> 4040 <bitfield name="WRMASK" low="22" high="25" type="hex"/> 4041 <bitfield name="HALF" pos="26" type="boolean"/> 4042 <doc>Results in color being zero</doc> 4043 <bitfield name="UNK27" pos="27" type="boolean"/> 4044 <bitfield name="BINDLESS" pos="28" type="boolean"/> 4045 <bitfield name="CMD" low="29" high="31" type="a6xx_tex_prefetch_cmd"/> 4046 </reg32> 4047 </array> 4048 <array offset="0xa99f" name="SP_PS_INITIAL_TEX_LOAD" stride="1" length="4" variants="A7XX-" usage="draw"> 4049 <reg32 offset="0" name="CMD" variants="A7XX-"> 4050 <bitfield name="SRC" low="0" high="6" type="uint"/> 4051 <bitfield name="SAMP_ID" low="7" high="9" type="uint"/> 4052 <bitfield name="TEX_ID" low="10" high="12" type="uint"/> 4053 <bitfield name="DST" low="13" high="18" type="a3xx_regid"/> 4054 <bitfield name="WRMASK" low="19" high="22" type="hex"/> 4055 <bitfield name="HALF" pos="23" type="boolean"/> 4056 <bitfield name="BINDLESS" pos="25" type="boolean"/> 4057 <bitfield name="CMD" low="26" high="29" type="a6xx_tex_prefetch_cmd"/> 4058 </reg32> 4059 </array> 4060 <array offset="0xa9a3" name="SP_PS_INITIAL_TEX_INDEX" stride="1" length="4" usage="draw"> 4061 <reg32 offset="0" name="CMD"> 4062 <bitfield name="SAMP_ID" low="0" high="15" type="uint"/> 4063 <bitfield name="TEX_ID" low="16" high="31" type="uint"/> 4064 </reg32> 4065 </array> 4066 <reg32 offset="0xa9a7" name="SP_PS_TSIZE" low="0" high="7" type="uint" usage="draw"/> 4067 <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? --> 4068 <reg32 offset="0xa9a9" name="SP_PS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="draw"/> 4069 <reg32 offset="0xa9ab" name="SP_PS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 4070 <reg32 offset="0xa9ab" name="SP_PS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 4071 4072 <!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS --> 4073 4074 <reg32 offset="0xa9b0" name="SP_CS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="compute"> 4075 <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> 4076 <!-- seems to make SP use less concurrent threads when possible? --> 4077 <bitfield name="UNK21" pos="21" type="boolean"/> 4078 <!-- has a small impact on performance, not clear what it does --> 4079 <bitfield name="UNK22" pos="22" type="boolean"/> 4080 <bitfield name="EARLYPREAMBLE" pos="23" type="boolean"/> 4081 <bitfield name="MERGEDREGS" pos="31" type="boolean"/> 4082 </reg32> 4083 4084 <enum name="a6xx_const_ram_mode"> 4085 <value value="0x0" name="CONSTLEN_128"/> 4086 <value value="0x1" name="CONSTLEN_192"/> 4087 <value value="0x2" name="CONSTLEN_256"/> 4088 <value value="0x3" name="CONSTLEN_512"/> <!-- a7xx only --> 4089 </enum> 4090 4091 <!-- set for compute shaders --> 4092 <reg32 offset="0xa9b1" name="SP_CS_CNTL_1" usage="compute"> 4093 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"> 4094 <doc> 4095 If 0 - all 32k of shared storage is enabled, otherwise 4096 (SHARED_SIZE + 1) * 1k is enabled. 4097 The ldl/stl offset seems to be rewritten to 0 when it is beyond 4098 this limit. This is different from ldlw/stlw, which wraps at 4099 64k (and has 36k of storage on A640 - reads between 36k-64k 4100 always return 0) 4101 </doc> 4102 </bitfield> 4103 <bitfield name="CONSTANTRAMMODE" low="5" high="6" type="a6xx_const_ram_mode"> 4104 <doc> 4105 This defines the split between consts and local 4106 memory in the Local Buffer. The programmed value 4107 must be at least the actual CONSTLEN. 4108 </doc> 4109 </bitfield> 4110 <bitfield name="ALT_LM_ENCODE" pos="26" type="boolean"/> 4111 </reg32> 4112 <reg32 offset="0xa9b2" name="SP_CS_BOOLEAN_CF_MASK" type="hex" usage="compute"/> 4113 <reg32 offset="0xa9b3" name="SP_CS_PROGRAM_COUNTER_OFFSET" type="uint" usage="compute"/> 4114 <reg64 offset="0xa9b4" name="SP_CS_BASE" type="address" align="32" usage="compute"/> 4115 <reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="compute"/> 4116 <reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_BASE" type="waddress" align="32" usage="compute"/> 4117 <reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="compute"/> 4118 <reg32 offset="0xa9ba" name="SP_CS_TSIZE" low="0" high="7" type="uint" usage="compute"/> 4119 <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="compute"/> 4120 <reg32 offset="0xa9bc" name="SP_CS_INSTR_SIZE" low="0" high="27" type="uint" usage="compute"/> 4121 <reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="compute"/> 4122 <reg32 offset="0xa9be" name="SP_CS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX" usage="compute"/> 4123 <reg32 offset="0xa9be" name="SP_CS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-" usage="compute"/> 4124 <reg32 offset="0xa9c5" name="SP_CS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 4125 4126 <!-- new in a6xx gen4, matches SP_CS_CONST_CONFIG_0 --> 4127 <reg32 offset="0xa9c2" name="SP_CS_WIE_CNTL_0" usage="compute"> 4128 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> 4129 <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/> 4130 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/> 4131 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> 4132 </reg32> 4133 <!-- new in a6xx gen4, matches SP_CS_WGE_CNTL --> 4134 <reg32 offset="0xa9c3" name="SP_CS_WIE_CNTL_1" variants="A6XX" usage="compute"> 4135 <!-- gl_LocalInvocationIndex --> 4136 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 4137 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only 4138 one of those 6 "SP cores" --> 4139 <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/> 4140 <!-- Must match SP_CS_CTRL --> 4141 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> 4142 <!-- 1 thread per wave (ignored if bit9 set) --> 4143 <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/> 4144 </reg32> 4145 4146 <enum name="a7xx_workitem_rast_order"> 4147 <value value="0x0" name="WORKITEMRASTORDER_LINEAR"/> 4148 <doc> 4149 This is a fixed tiling, with 4x4 invocation outer tiles 4150 containing 2x2 invocation inner tiles. The intent is to 4151 improve cache locality with textures and images accessed 4152 using gl_LocalInvocationID. 4153 </doc> 4154 <value value="0x1" name="WORKITEMRASTORDER_TILED"/> 4155 </enum> 4156 4157 <reg32 offset="0xa9c3" name="SP_CS_WIE_CNTL_1" variants="A7XX-" usage="compute"> 4158 <!-- gl_LocalInvocationIndex --> 4159 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 4160 <!-- Must match SP_CS_CTRL --> 4161 <bitfield name="THREADSIZE" pos="8" type="a6xx_threadsize"/> 4162 <!-- 1 thread per wave (would hang if THREAD128 is also set) --> 4163 <bitfield name="THREADSIZE_SCALAR" pos="9" type="boolean"/> 4164 4165 <doc>How invocations/fibers within a workgroup are tiled.</doc> 4166 <bitfield name="WORKITEMRASTORDER" pos="15" type="a7xx_workitem_rast_order"/> 4167 </reg32> 4168 4169 <!-- TODO: two 64kb aligned addresses at a9d0/a9d2 --> 4170 4171 <reg64 offset="0xa9e0" name="SP_PS_SAMPLER_BASE" type="address" align="16" usage="draw"/> 4172 <reg64 offset="0xa9e2" name="SP_CS_SAMPLER_BASE" type="address" align="16" usage="compute"/> 4173 <reg64 offset="0xa9e4" name="SP_PS_TEXMEMOBJ_BASE" type="address" align="64" usage="draw"/> 4174 <reg64 offset="0xa9e6" name="SP_CS_TEXMEMOBJ_BASE" type="address" align="64" usage="compute"/> 4175 4176 <enum name="a6xx_bindless_descriptor_size"> 4177 <doc> 4178 This can alternatively be interpreted as a pitch shift, ie, the 4179 descriptor size is 2 << N dwords 4180 </doc> 4181 <value value="1" name="BINDLESS_DESCRIPTOR_16B"/> 4182 <value value="3" name="BINDLESS_DESCRIPTOR_64B"/> 4183 </enum> 4184 4185 <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="compute"> 4186 <reg64 offset="0" name="DESCRIPTOR" variants="A6XX"> 4187 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4188 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4189 </reg64> 4190 </array> 4191 <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="compute"> 4192 <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-"> 4193 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4194 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4195 </reg64> 4196 </array> 4197 4198 <!-- 4199 UAV state for compute shader: 4200 --> 4201 <reg64 offset="0xa9f2" name="SP_CS_UAV_BASE" type="address" align="16" variants="A6XX" usage="compute"/> 4202 <reg64 offset="0xa9f8" name="SP_CS_UAV_BASE" type="address" align="16" variants="A7XX-" usage="compute"/> 4203 <reg32 offset="0xaa00" name="SP_CS_USIZE" low="0" high="6" type="uint" usage="compute"/> 4204 4205 <!-- Correlated with avgs/uvgs usage in FS --> 4206 <reg32 offset="0xaa01" name="SP_PS_VGS_CNTL" type="uint" variants="A7XX-" usage="cmd"/> 4207 4208 <reg32 offset="0xaa02" name="SP_PS_OUTPUT_CONST_CNTL" variants="A7XX-" usage="cmd"> 4209 <bitfield name="ENABLED" pos="0" type="boolean"/> 4210 </reg32> 4211 <reg32 offset="0xaa03" name="SP_PS_OUTPUT_CONST_MASK" variants="A7XX-" usage="cmd"> 4212 <doc> 4213 Specify for which components the output color should be read 4214 from alias, e.g. for: 4215 4216 alias.1.b32.0 r3.x, c8.x 4217 alias.1.b32.0 r2.x, c4.x 4218 alias.1.b32.0 r1.x, c4.x 4219 alias.1.b32.0 r0.x, c0.x 4220 4221 the SP_PS_OUTPUT_CONST_MASK would be 0x00001111 4222 </doc> 4223 4224 <bitfield name="RT0" low="0" high="3"/> 4225 <bitfield name="RT1" low="4" high="7"/> 4226 <bitfield name="RT2" low="8" high="11"/> 4227 <bitfield name="RT3" low="12" high="15"/> 4228 <bitfield name="RT4" low="16" high="19"/> 4229 <bitfield name="RT5" low="20" high="23"/> 4230 <bitfield name="RT6" low="24" high="27"/> 4231 <bitfield name="RT7" low="28" high="31"/> 4232 </reg32> 4233 4234 <array offset="0xaa04" name="SP_MRT_BLEND_CNTL" stride="1" length="8" variants="A8XX-"> 4235 <reg32 offset="0" name="REG"> 4236 <bitfield name="COLOR_BLEND_EN" pos="0" type="boolean"/> 4237 <bitfield name="ALPHA_BLEND_EN" pos="1" type="boolean"/> 4238 <bitfield name="COMPONENT_WRITE_MASK" low="7" high="10"/> 4239 </reg32> 4240 </array> 4241 4242 <reg32 offset="0xaa0c" name="SP_ALPHA_TEST_CNTL" variants="A8XX-"> 4243 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/> 4244 </reg32> 4245 4246 <reg32 offset="0xaaf2" name="SP_UNKNOWN_AAF2" type="uint" usage="cmd"/> 4247 4248 <!-- 4249 This enum is probably similar in purpose to SNORMMODE on a3xx, 4250 minus the snorm stuff, i.e. it controls what happens with an 4251 out-of-bounds isam/isamm. GL and Vulkan robustness require us to 4252 return 0 on out-of-bound textureFetch(). 4253 --> 4254 <enum name="a6xx_isam_mode"> 4255 <value value="0x1" name="ISAMMODE_CL"/> 4256 <value value="0x2" name="ISAMMODE_GL"/> 4257 </enum> 4258 4259 <reg32 offset="0xab00" name="SP_MODE_CNTL" usage="draw"> 4260 <!-- 4261 When set, half register loads from the constant file will 4262 load a 32-bit value (so hc0.y loads the same value as c0.y) 4263 and implicitly convert it to 16b (f2f16, or u2u16, based on 4264 operand type). When unset, half register loads from the 4265 constant file will load 16 bits from the packed constant 4266 file (so hc0.y loads the top 16 bits of the value of c0.x) 4267 --> 4268 <bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/> 4269 <bitfield name="ISAMMODE" low="1" high="2" type="a6xx_isam_mode"/> 4270 <bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS --> 4271 </reg32> 4272 4273 <reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/> 4274 <reg32 offset="0xab02" name="SP_HLSQ_MODE_CNTL" variants="A7XX-" usage="cmd"> 4275 <bitfield name="SHARED_CONSTS_ENABLE" pos="0" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS --> 4276 </reg32> 4277 4278 <reg32 offset="0xab04" name="SP_PS_CONFIG" type="a6xx_sp_xs_config" usage="draw"/> 4279 <reg32 offset="0xab05" name="SP_PS_INSTR_SIZE" low="0" high="27" type="uint" usage="draw"/> 4280 4281 <reg32 offset="0xab06" name="SP_BIN_SIZE" type="a8xx_bin_size" variants="A8XX-" usage="cmd"/> 4282 4283 <array offset="0xab10" name="SP_GFX_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="draw"> 4284 <reg64 offset="0" name="DESCRIPTOR" variants="A6XX"> 4285 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4286 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4287 </reg64> 4288 </array> 4289 <array offset="0xab0a" name="SP_GFX_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="draw"> 4290 <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-"> 4291 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4292 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4293 </reg64> 4294 </array> 4295 4296 <!-- 4297 Combined UAV state for 3d pipe, used for Image and SSBO write/atomic 4298 instructions VS/HS/DS/GS/FS. See SP_CS_UAV_BASE_* for compute shaders. 4299 --> 4300 <reg64 offset="0xab1a" name="SP_GFX_UAV_BASE" type="address" align="16" usage="cmd"/> 4301 <reg32 offset="0xab20" name="SP_GFX_USIZE" low="0" high="6" type="uint" variants="A6XX-A7XX" usage="cmd"/> 4302 <reg32 offset="0xab09" name="SP_GFX_USIZE" low="0" high="6" type="uint" variants="A8XX-" usage="cmd"/> 4303 4304 <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX" usage="cmd"/> 4305 4306 <reg32 offset="0xab23" name="SP_UNKNOWN_AB23" variants="A8XX-"/> 4307 4308 <enum name="a6xx_sp_a2d_output_ifmt_type"> 4309 <value name="OUTPUT_IFMT_2D_FLOAT" value="0"/> 4310 <value name="OUTPUT_IFMT_2D_SINT" value="1"/> 4311 <value name="OUTPUT_IFMT_2D_UINT" value="2"/> 4312 </enum> 4313 4314 <bitset name="a6xx_sp_a2d_output_info" inline="yes"> 4315 <bitfield name="HALF_PRECISION" pos="0" type="boolean"/> 4316 <bitfield name="IFMT_TYPE" low="1" high="2" type="a6xx_sp_a2d_output_ifmt_type"/> 4317 <!-- looks like HW only cares about the base type of this format, 4318 which matches the ifmt? --> 4319 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/> 4320 <!-- set when ifmt is R2D_UNORM8_SRGB --> 4321 <bitfield name="SRGB" pos="11" type="boolean"/> 4322 <!-- some sort of channel mask, not sure what it is for --> 4323 <bitfield name="MASK" low="12" high="15"/> 4324 </bitset> 4325 4326 <reg32 offset="0xacc0" name="SP_A2D_OUTPUT_INFO" type="a6xx_sp_a2d_output_info" variants="A6XX" usage="blit"/> 4327 <reg32 offset="0xa9bf" name="SP_A2D_OUTPUT_INFO" type="a6xx_sp_a2d_output_info" variants="A7XX-" usage="blit"/> 4328 4329 <reg32 offset="0xae00" name="SP_DBG_ECO_CNTL" usage="init"/> 4330 <reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" variants="A6XX"/> 4331 <reg32 offset="0xae01" name="SP_SHADER_PROFILING" variants="A8XX-"/> 4332 <reg32 offset="0xae02" name="SP_NC_MODE_CNTL"> 4333 <!-- TODO: valid bits 0x3c3f, see kernel --> 4334 </reg32> 4335 <reg32 offset="0xae03" name="SP_CHICKEN_BITS" usage="init"> 4336 <doc> 4337 When this bit is enabled, new waves may be unlocked once 4338 all invocations have signaled they don't need local 4339 memory anymore using (eolm)nop. 4340 </doc> 4341 <bitfield name="EOLM_ENABLE" pos="1" type="boolean"/> 4342 </reg32> 4343 <reg32 offset="0xae04" name="SP_NC_MODE_CNTL_2" usage="init"> 4344 <bitfield name="F16_NO_INF" pos="3" type="boolean"/> 4345 </reg32> 4346 4347 <reg32 offset="0xae05" name="SP_SS_CHICKEN_BITS_0" variants="A8XX-"/> 4348 <reg32 offset="0xae06" name="SP_ISDB_CNTL" variants="A7XX-" usage="init"/> 4349 <reg32 offset="0xae07" name="SP_PERFCTR_CNTL"/> 4350 <reg32 offset="0xae08" name="SP_CHICKEN_BITS_1" variants="A7XX-" usage="init"/> 4351 <reg32 offset="0xae09" name="SP_CHICKEN_BITS_2" variants="A7XX-" usage="init"/> 4352 <reg32 offset="0xae0a" name="SP_CHICKEN_BITS_3" variants="A7XX-" usage="init"/> 4353 <reg32 offset="0xae0b" name="SP_CHICKEN_BITS_4" variants="A8XX-"/> 4354 <reg32 offset="0xae0c" name="SP_STATUS"/> 4355 4356 <reg32 offset="0xae0f" name="SP_PERFCTR_SHADER_MASK" usage="init"> 4357 <!-- some perfcntrs are affected by a per-stage enable bit 4358 (PERF_SP_ALU_WORKING_CYCLES for example) 4359 TODO: verify position of HS/DS/GS bits --> 4360 <bitfield name="VS" pos="0" type="boolean"/> 4361 <bitfield name="HS" pos="1" type="boolean"/> 4362 <bitfield name="DS" pos="2" type="boolean"/> 4363 <bitfield name="GS" pos="3" type="boolean"/> 4364 <bitfield name="FS" pos="4" type="boolean"/> 4365 <bitfield name="CS" pos="5" type="boolean"/> 4366 </reg32> 4367 <array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24" variants="A6XX"/> 4368 <array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/> 4369 <reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="init"/> 4370 <reg32 offset="0xae6b" name="SP_HLSQ_TIMEOUT_THRESHOLD_DP" variants="A7XX-" usage="init"/> 4371 <reg32 offset="0xae6c" name="SP_HLSQ_DBG_ECO_CNTL" variants="A7XX-" usage="init"/> 4372 <reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-"> 4373 <bitfield name="CONTEXT" low="26" high="30"/> 4374 <bitfield name="SLICE" low="21" high="25"/> 4375 <bitfield name="LOCATION" low="18" high="20" type="a7xx_state_location"/> 4376 <bitfield name="PIPE" low="16" high="17" type="adreno_pipe"/> 4377 <bitfield name="STATETYPE" low="8" high="15" type="a7xx_statetype_id"/> 4378 <bitfield name="USPTP" low="4" high="7"/> 4379 <bitfield name="SPTP" low="0" high="3"/> 4380 </reg32> 4381 <reg32 offset="0xae71" name="SP_DBG_CNTL" variants="A7XX-"/> 4382 <reg32 offset="0xae73" name="SP_HLSQ_DBG_ECO_CNTL_1" variants="A7XX-"/> 4383 <reg32 offset="0xae74" name="SP_HLSQ_DBG_ECO_CNTL_2" variants="A7XX-"/> 4384 <reg32 offset="0xae76" name="SP_HLSQ_DBG_ECO_CNTL_3" variants="A8XX-"/> 4385 <array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/> 4386 <!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) --> 4387 <!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range --> 4388 <reg32 offset="0xae52" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/> 4389 4390 <reg64 offset="0xae10" name="SP_HLSQ_GC_GMEM_RANGE_MIN" variants="A8XX-"/> 4391 <reg64 offset="0xae12" name="SP_HLSQ_LPAC_GMEM_RANGE_MIN" variants="A8XX-"/> 4392 <reg32 offset="0xae15" name="SP_LPAC_CPI_STATUS" variants="A8XX-"/> 4393 <reg32 offset="0xae16" name="SP_LPAC_DBG_STATUS" variants="A8XX-"/> 4394 <reg32 offset="0xae17" name="SP_LPAC_ISDB_BATCH_COUNT" variants="A8XX-"/> 4395 <reg32 offset="0xae18" name="SP_LPAC_ISDB_BATCH_COUNT_INCR_EN" variants="A8XX-"/> 4396 <reg32 offset="0xae19" name="SP_LPAC_ISDB_BATCH_COUNT_SHADERS" variants="A8XX-"/> 4397 <reg32 offset="0xae30" name="SP_ISDB_BATCH_COUNT" variants="A7XX-"/> 4398 <reg32 offset="0xae31" name="SP_ISDB_BATCH_COUNT_INCR_EN" variants="A7XX-"/> 4399 <reg32 offset="0xae32" name="SP_ISDB_BATCH_COUNT_SHADERS" variants="A7XX-"/> 4400 <reg32 offset="0xae35" name="SP_ISDB_DEBUG_CONFIG" variants="A7XX-"/> 4401 4402 <reg32 offset="0xae3a" name="SP_SELF_THROTTLE_CONTROL" variants="A7XX-"/> 4403 <reg32 offset="0xae3b" name="SP_DISPATCH_CNTL" variants="A7XX-"/> 4404 <reg64 offset="0xae3c" name="SP_SW_DEBUG_ADDR" variants="A7XX-"/> 4405 <reg64 offset="0xae3e" name="SP_ISDB_DEBUG_ADDR" variants="A7XX-"/> 4406 4407 <array offset="0xaec0" name="SP_PERFCTR_HLSQ_SEL_2" stride="1" length="6" variants="A7XX-"/> 4408 4409 <!-- 4410 The downstream kernel calls the debug cluster of registers 4411 "a6xx_sp_ps_tp_cluster" but this actually specifies the border 4412 color base for compute shaders. 4413 --> 4414 <reg64 offset="0xb180" name="TPL1_CS_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/> 4415 <reg32 offset="0xb182" name="TPL1_PS_ROTATION_CNTL" low="0" high="2" usage="cmd"/> 4416 <reg32 offset="0xb183" name="TPL1_PS_SWIZZLE_CNTL" low="0" high="23" usage="cmd"/> 4417 4418 <reg32 offset="0xb190" name="SP_UNKNOWN_B190"/> 4419 <reg32 offset="0xb191" name="SP_UNKNOWN_B191"/> 4420 4421 <reg32 offset="0xb2d6" name="TPL1_A2D_BIN_SIZE" type="a8xx_bin_size" variants="A8XX-" usage="cmd"/> 4422 <reg32 offset="0xb2d7" name="TPL1_A2D_FILTER_CNTL" variants="A8XX-" usage="blit"/> 4423 4424 <reg32 offset="0xb300" name="TPL1_RAS_MSAA_CNTL" usage="draw"> 4425 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 4426 <bitfield name="UNK2" low="2" high="3"/> 4427 </reg32> 4428 <reg32 offset="0xb301" name="TPL1_DEST_MSAA_CNTL" usage="draw"> 4429 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 4430 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 4431 </reg32> 4432 4433 <!-- looks to work in the same way as a5xx: --> 4434 <reg64 offset="0xb302" name="TPL1_GFX_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/> 4435 <reg32 offset="0xb304" name="TPL1_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" variants="A6XX-A7XX" usage="draw"/> 4436 <reg32 offset="0xb305" name="TPL1_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="draw" variants="A6XX-A7XX" /> 4437 <reg32 offset="0xb306" name="TPL1_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="draw" variants="A6XX-A7XX" /> 4438 <reg32 offset="0xb307" name="TPL1_WINDOW_OFFSET" type="a6xx_reg_xy" usage="cmd"/> 4439 4440 <reg32 offset="0xb304" name="TPL1_BIN_SIZE" type="a8xx_bin_size" variants="A8XX-" usage="cmd"/> 4441 4442 <enum name="a6xx_coord_round"> 4443 <value value="0" name="COORD_TRUNCATE"/> 4444 <value value="1" name="COORD_ROUND_NEAREST_EVEN"/> 4445 <value value="2" name="ROUND_FLOAT_TO_INT"/> <!-- only ARRAYCOORDROUNDMODE --> 4446 </enum> 4447 4448 <enum name="a6xx_nearest_mode"> 4449 <value value="0" name="ROUND_CLAMP_TRUNCATE"/> 4450 <value value="1" name="CLAMP_ROUND_TRUNCATE"/> 4451 </enum> 4452 4453 <bitset name="a6xx_tpl1_mode_cntl" inline="yes"> 4454 <bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/> 4455 <bitfield name="TEXCOORDROUNDMODE" pos="2" type="a6xx_coord_round"/> 4456 <bitfield name="ARRAYCOORDROUNDMODE" low="3" high="4" type="a6xx_coord_round"/> 4457 <bitfield name="NEARESTMIPSNAP" pos="5" type="a6xx_nearest_mode"/> 4458 <bitfield name="SAMPLEREPLICATE" pos="6" type="boolean"/> 4459 <bitfield name="DESTDATATYPEOVERRIDE" pos="7" type="boolean"/> 4460 <bitfield name="PACK_SAMP_REDUCED_PRECISION" pos="8" type="boolean"/> 4461 </bitset> 4462 4463 <reg32 offset="0xb309" name="TPL1_MODE_CNTL" usage="cmd" type="a6xx_tpl1_mode_cntl" variants="A6XX-A7XX"/> 4464 <reg32 offset="0xb309" name="TPL1_MODE_CNTL" usage="cmd" type="a6xx_tpl1_mode_cntl" variants="A8XX-"> 4465 <bitfield name="CLAMP_DISABLE" pos="12" type="boolean"/> 4466 </reg32> 4467 <reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/> 4468 4469 <!-- 4470 Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either 4471 badly named or the functionality moved in a6xx. But downstream kernel 4472 calls this "a6xx_sp_ps_tp_2d_cluster" 4473 --> 4474 <reg32 offset="0xb4c0" name="TPL1_A2D_SRC_TEXTURE_INFO" type="a6xx_a2d_src_texture_info" variants="A6XX" usage="blit"/> 4475 <reg32 offset="0xb4c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A6XX" usage="blit"> 4476 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 4477 <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 4478 </reg32> 4479 <reg64 offset="0xb4c2" name="TPL1_A2D_SRC_TEXTURE_BASE" type="address" align="16" variants="A6XX" usage="blit"/> 4480 <reg32 offset="0xb4c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A6XX" usage="blit"> 4481 <bitfield name="UNK0" low="0" high="8"/> 4482 <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/> 4483 </reg32> 4484 4485 <reg32 offset="0xb2c0" name="TPL1_A2D_SRC_TEXTURE_INFO" type="a6xx_a2d_src_texture_info" variants="A7XX-" usage="blit"/> 4486 <reg32 offset="0xb2c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A7XX-" usage="blit"> 4487 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 4488 <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 4489 </reg32> 4490 <reg64 offset="0xb2c2" name="TPL1_A2D_SRC_TEXTURE_BASE" type="address" align="16" variants="A7XX" usage="blit"/> 4491 <!-- gen8 can use an unaligned base for IMG_BUFFER: --> 4492 <reg64 offset="0xb2c2" name="TPL1_A2D_SRC_TEXTURE_BASE" type="address" variants="A8XX-" usage="blit"/> 4493 <reg32 offset="0xb2c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A7XX-" usage="blit"> 4494 <!-- 4495 Bits from 3..9 must be zero unless 'TPL1_A2D_BLT_CNTL::TYPE' 4496 is A6XX_TEX_IMG_BUFFER, which allows for lower alignment. 4497 --> 4498 <bitfield name="PITCH" low="3" high="23" type="uint"/> 4499 </reg32> 4500 4501 <!-- planes for NV12, etc. (TODO: not tested) --> 4502 <reg64 offset="0xb4c5" name="TPL1_A2D_SRC_TEXTURE_BASE_1" type="address" align="16" variants="A6XX" usage="blit"/> 4503 <reg32 offset="0xb4c7" name="TPL1_A2D_SRC_TEXTURE_PITCH_1" low="0" high="11" shr="6" type="uint" variants="A6XX" usage="blit"/> 4504 <reg64 offset="0xb4c8" name="TPL1_A2D_SRC_TEXTURE_BASE_2" type="address" align="16" variants="A6XX" usage="blit"/> 4505 4506 <reg64 offset="0xb2c5" name="TPL1_A2D_SRC_TEXTURE_BASE_1" type="address" align="16" variants="A7XX-" usage="blit"/> 4507 <reg32 offset="0xb2c7" name="TPL1_A2D_SRC_TEXTURE_PITCH_1" low="0" high="11" shr="6" type="uint" variants="A7XX-" usage="blit"/> 4508 <reg64 offset="0xb2c8" name="TPL1_A2D_SRC_TEXTURE_BASE_2" type="address" align="16" variants="A7XX-" usage="blit"/> 4509 4510 <reg64 offset="0xb4ca" name="TPL1_A2D_SRC_TEXTURE_FLAG_BASE" type="address" align="16" variants="A6XX" usage="blit"/> 4511 <reg32 offset="0xb4cc" name="TPL1_A2D_SRC_TEXTURE_FLAG_PITCH" low="0" high="7" shr="6" type="uint" variants="A6XX" usage="blit"/> 4512 4513 <reg64 offset="0xb2ca" name="TPL1_A2D_SRC_TEXTURE_FLAG_BASE" type="address" align="16" variants="A7XX-" usage="blit"/> 4514 <reg32 offset="0xb2cc" name="TPL1_A2D_SRC_TEXTURE_FLAG_PITCH" low="0" high="7" shr="6" type="uint" variants="A7XX-" usage="blit"/> 4515 4516 <reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A6XX" usage="blit"/> 4517 <reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A6XX" usage="blit"/> 4518 <reg32 offset="0xb4cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A6XX" usage="blit"/> 4519 <reg32 offset="0xb4d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A6XX" usage="blit"/> 4520 <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A6XX" usage="cmd"/> 4521 4522 <reg32 offset="0xb2cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A7XX" usage="blit"/> 4523 <reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX" usage="blit"/> 4524 <reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX" usage="blit"/> 4525 <reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX" usage="blit"/> 4526 <reg32 offset="0xb2d1" name="TPL1_A2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="cmd"/> 4527 <bitset name="a7xx_tpl1_a2d_blt_cntl" inline="yes"> 4528 <bitfield name="RAW_COPY" pos="0" type="boolean"/> 4529 <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/> 4530 </bitset> 4531 <reg32 offset="0xb2d2" name="TPL1_A2D_BLT_CNTL" type="a7xx_tpl1_a2d_blt_cntl" variants="A7XX" usage="blit"> 4532 <bitfield name="START_OFFSET_TEXELS" low="16" high="21"/> 4533 </reg32> 4534 <reg32 offset="0xb2d2" name="TPL1_A2D_BLT_CNTL" type="a7xx_tpl1_a2d_blt_cntl" variants="A8XX-" usage="blit"/> 4535 <reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX" usage="cmd"/> 4536 <reg32 offset="0xab07" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A8XX-" usage="cmd"/> 4537 4538 <reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" usage="init"> 4539 <bitfield name="LINEAR_MIPMAP_FALLBACK_IN_BLOCKS" pos="25" type="boolean" variants="A6XX-A7XX"/> 4540 </reg32> 4541 <reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 4542 <reg32 offset="0xb602" name="TPL1_DBG_ECO_CNTL1" usage="init"> 4543 <!-- Affects UBWC in some way, if BLIT_OP_SCALE is done with this bit set 4544 and if other blit is done without it - UBWC image may be copied incorrectly. 4545 --> 4546 <bitfield name="TP_UBWC_FLAG_HINT" pos="18" type="boolean"/> 4547 </reg32> 4548 <reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL"> 4549 <bitfield name="MODE" pos="0" type="boolean"/> 4550 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/> 4551 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b --> 4552 <bitfield name="UPPER_BIT" pos="4" type="uint"/> 4553 <bitfield name="UNK6" low="6" high="7"/> 4554 </reg32> 4555 <reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="init"/> <!-- always 0x0 or 0x44 ? --> 4556 4557 <array offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="5" variants="A6XX"> 4558 <reg32 offset="0" name="REG" low="0" high="29"/> 4559 </array> 4560 4561 <array offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="5" variants="A7XX"> 4562 <reg32 offset="0" name="REG" low="0" high="29" usage="cmd"/> 4563 </array> 4564 4565 <array offset="0xb606" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="25" variants="A8XX"> 4566 <reg32 offset="0" name="REG" low="0" high="29"/> 4567 </array> 4568 4569 <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12" variants="A6XX"/> 4570 <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="18" variants="A7XX"/> 4571 <array offset="0xb620" name="TPL1_PERFCTR_TP_SEL" stride="1" length="20" variants="A8XX"/> 4572 4573 <!-- TODO: 4 more perfcntr sel at 0xb620 ? --> 4574 4575 <bitset name="a6xx_xs_const_config" inline="yes"> 4576 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/> 4577 <bitfield name="ENABLED" pos="8" type="boolean"/> 4578 <bitfield name="READ_IMM_SHARED_CONSTS" pos="9" type="boolean" variants="A7XX-"/> 4579 </bitset> 4580 4581 <reg32 offset="0xb800" name="SP_VS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="draw"/> 4582 <reg32 offset="0xb801" name="SP_HS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="draw"/> 4583 <reg32 offset="0xb802" name="SP_DS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="draw"/> 4584 <reg32 offset="0xb803" name="SP_GS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="draw"/> 4585 4586 <reg32 offset="0xa827" name="SP_VS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="draw"/> 4587 <reg32 offset="0xa83f" name="SP_HS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="draw"/> 4588 <reg32 offset="0xa867" name="SP_DS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="draw"/> 4589 <reg32 offset="0xa898" name="SP_GS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="draw"/> 4590 4591 <reg32 offset="0xa9aa" name="SP_RENDER_CNTL" variants="A7XX-" usage="draw"> 4592 <bitfield name="FS_DISABLE" pos="0" type="boolean"/> 4593 </reg32> 4594 4595 <reg32 offset="0xa9ac" name="SP_DITHER_CNTL" variants="A7XX-" usage="cmd"> 4596 <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/> 4597 <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/> 4598 <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/> 4599 <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/> 4600 <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/> 4601 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/> 4602 <bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/> 4603 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/> 4604 </reg32> 4605 4606 <reg32 offset="0xa9ad" name="SP_VRS_CONFIG" variants="A7XX-" usage="draw"> 4607 <bitfield name="PIPELINE_FSR_ENABLE" pos="0" type="boolean"/> 4608 <bitfield name="ATTACHMENT_FSR_ENABLE" pos="1" type="boolean"/> 4609 <bitfield name="PRIMITIVE_FSR_ENABLE" pos="3" type="boolean"/> 4610 </reg32> 4611 4612 <reg32 offset="0xa9ae" name="SP_PS_CNTL_1" variants="A7XX-" usage="draw"> 4613 <bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/> 4614 <bitfield name="DEFER_WAVE_ALLOC_DIS" pos="8" type="boolean"/> 4615 <bitfield name="EVICT_BUF_MODE" low="9" high="10"/> 4616 <bitfield name="WAVE_PAIR_MODE" low="11" high="12"/> 4617 <bitfield name="NUM_TOTAL_VAR" low="13" high="20"/> 4618 </reg32> 4619 4620 <reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/> 4621 <reg64 offset="0xb821" name="HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR" align="16" type="address"/> 4622 <reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/> 4623 4624 4625 <bitset name="a6xx_sp_ps_wave_cntl" inline="yes"> 4626 <!-- must match SP_FS_CTRL --> 4627 <bitfield name="THREADSIZE" pos="0" type="a6xx_threadsize"/> 4628 <bitfield name="VARYINGS" pos="1" type="boolean"/> 4629 <bitfield name="UNK2" low="2" high="11"/> 4630 </bitset> 4631 <bitset name="a6xx_sp_reg_prog_id_1" inline="yes"> 4632 <!-- register loaded with position (bary.f) --> 4633 <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/> 4634 <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/> 4635 <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/> 4636 <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/> 4637 </bitset> 4638 <bitset name="a6xx_sp_reg_prog_id_2" inline="yes"> 4639 <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/> 4640 <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/> 4641 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/> 4642 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/> 4643 </bitset> 4644 <bitset name="a6xx_sp_reg_prog_id_3" inline="yes"> 4645 <bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/> 4646 <bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/> 4647 </bitset> 4648 4649 <reg32 offset="0xb980" type="a6xx_sp_ps_wave_cntl" name="SP_PS_WAVE_CNTL" variants="A6XX" usage="draw"/> 4650 <reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX" usage="draw"/> <!-- never used by blob --> 4651 <reg32 offset="0xb982" name="SP_LB_PARAM_LIMIT" low="0" high="2" variants="A6XX" usage="draw"> 4652 <!-- Sets the maximum number of primitives allowed in one FS wave minus one, similarly to the 4653 A3xx field, except that it's not necessary to set it to anything but the maximum, since 4654 the hardware will simply emit smaller waves when it runs out of space. --> 4655 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> 4656 </reg32> 4657 <reg32 offset="0xb983" name="SP_REG_PROG_ID_0" variants="A6XX" usage="draw"> 4658 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> 4659 <!-- SAMPLEID is loaded into a half-precision register: --> 4660 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> 4661 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> 4662 <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/> 4663 </reg32> 4664 <reg32 offset="0xb984" type="a6xx_sp_reg_prog_id_1" name="SP_REG_PROG_ID_1" variants="A6XX" usage="draw"/> 4665 <reg32 offset="0xb985" type="a6xx_sp_reg_prog_id_2" name="SP_REG_PROG_ID_2" variants="A6XX" usage="draw"/> 4666 <reg32 offset="0xb986" type="a6xx_sp_reg_prog_id_3" name="SP_REG_PROG_ID_3" variants="A6XX" usage="draw"/> 4667 <reg32 offset="0xb987" name="SP_CS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="compute"/> 4668 <reg32 offset="0xa9c6" type="a6xx_sp_ps_wave_cntl" name="SP_PS_WAVE_CNTL" variants="A7XX" usage="draw"/> 4669 <reg32 offset="0xa9c6" name="SP_PS_WAVE_CNTL" variants="A8XX-" usage="draw"> 4670 <bitfield name="VARYINGS" pos="1" type="boolean"/> 4671 </reg32> 4672 <reg32 offset="0xa9c7" name="SP_LB_PARAM_LIMIT" low="0" high="2" variants="A7XX-" usage="draw"> 4673 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> 4674 </reg32> 4675 <reg32 offset="0xa9c8" name="SP_REG_PROG_ID_0" variants="A7XX-" usage="draw"> 4676 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> 4677 <!-- SAMPLEID is loaded into a half-precision register: --> 4678 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> 4679 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> 4680 <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/> 4681 </reg32> 4682 <reg32 offset="0xa9c9" type="a6xx_sp_reg_prog_id_1" name="SP_REG_PROG_ID_1" variants="A7XX-" usage="draw"/> 4683 <reg32 offset="0xa9ca" type="a6xx_sp_reg_prog_id_2" name="SP_REG_PROG_ID_2" variants="A7XX-" usage="draw"/> 4684 <reg32 offset="0xa9cb" type="a6xx_sp_reg_prog_id_3" name="SP_REG_PROG_ID_3" variants="A7XX-" usage="draw"/> 4685 <reg32 offset="0xa9cd" name="SP_CS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="compute"/> 4686 4687 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) --> 4688 <reg32 offset="0xb990" name="SP_CS_NDRANGE_0" variants="A6XX" usage="compute"> 4689 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> 4690 <!-- localsize is value minus one: --> 4691 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 4692 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 4693 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 4694 </reg32> 4695 <reg32 offset="0xb991" name="SP_CS_NDRANGE_1" variants="A6XX" usage="compute"> 4696 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/> 4697 </reg32> 4698 <reg32 offset="0xb992" name="SP_CS_NDRANGE_2" variants="A6XX" usage="compute"> 4699 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/> 4700 </reg32> 4701 <reg32 offset="0xb993" name="SP_CS_NDRANGE_3" variants="A6XX" usage="compute"> 4702 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/> 4703 </reg32> 4704 <reg32 offset="0xb994" name="SP_CS_NDRANGE_4" variants="A6XX" usage="compute"> 4705 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/> 4706 </reg32> 4707 <reg32 offset="0xb995" name="SP_CS_NDRANGE_5" variants="A6XX" usage="compute"> 4708 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/> 4709 </reg32> 4710 <reg32 offset="0xb996" name="SP_CS_NDRANGE_6" variants="A6XX" usage="compute"> 4711 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/> 4712 </reg32> 4713 <reg32 offset="0xb997" name="SP_CS_CONST_CONFIG_0" variants="A6XX" usage="compute"> 4714 <!-- these are all vec3. first 3 need to be high regs 4715 WGSIZECONSTID is the local size (from SP_CS_NDRANGE_0) 4716 WGOFFSETCONSTID is WGIDCONSTID*WGSIZECONSTID 4717 --> 4718 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> 4719 <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/> 4720 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/> 4721 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> 4722 </reg32> 4723 <reg32 offset="0xb998" name="SP_CS_WGE_CNTL" variants="A6XX" usage="compute"> 4724 <!-- gl_LocalInvocationIndex --> 4725 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 4726 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only 4727 one of those 6 "SP cores" --> 4728 <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/> 4729 <!-- Must match SP_CS_CTRL --> 4730 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> 4731 <!-- 1 thread per wave (ignored if bit9 set) --> 4732 <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/> 4733 </reg32> 4734 <!--note: vulkan blob doesn't use these --> 4735 <reg32 offset="0xb999" name="SP_CS_KERNEL_GROUP_X" variants="A6XX" usage="compute"/> 4736 <reg32 offset="0xb99a" name="SP_CS_KERNEL_GROUP_Y" variants="A6XX" usage="compute"/> 4737 <reg32 offset="0xb99b" name="SP_CS_KERNEL_GROUP_Z" variants="A6XX" usage="compute"/> 4738 4739 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) --> 4740 <reg32 offset="0xa9d4" name="SP_CS_NDRANGE_0" variants="A7XX-" usage="compute"> 4741 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> 4742 <!-- localsize is value minus one: --> 4743 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 4744 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 4745 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 4746 </reg32> 4747 <reg32 offset="0xa9d5" name="SP_CS_NDRANGE_1" variants="A7XX-" usage="compute"> 4748 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/> 4749 </reg32> 4750 <reg32 offset="0xa9d6" name="SP_CS_NDRANGE_2" variants="A7XX-" usage="compute"> 4751 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/> 4752 </reg32> 4753 <reg32 offset="0xa9d7" name="SP_CS_NDRANGE_3" variants="A7XX-" usage="compute"> 4754 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/> 4755 </reg32> 4756 <reg32 offset="0xa9d8" name="SP_CS_NDRANGE_4" variants="A7XX-" usage="compute"> 4757 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/> 4758 </reg32> 4759 <reg32 offset="0xa9d9" name="SP_CS_NDRANGE_5" variants="A7XX-" usage="compute"> 4760 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/> 4761 </reg32> 4762 <reg32 offset="0xa9da" name="SP_CS_NDRANGE_6" variants="A7XX-" usage="compute"> 4763 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/> 4764 </reg32> 4765 <!--note: vulkan blob doesn't use these --> 4766 <reg32 offset="0xa9dc" name="SP_CS_KERNEL_GROUP_X" variants="A7XX-" usage="compute"/> 4767 <reg32 offset="0xa9dd" name="SP_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="compute"/> 4768 <reg32 offset="0xa9de" name="SP_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="compute"/> 4769 4770 <enum name="a7xx_cs_yalign"> 4771 <value name="CS_YALIGN_1" value="8"/> 4772 <value name="CS_YALIGN_2" value="4"/> 4773 <value name="CS_YALIGN_4" value="2"/> 4774 <value name="CS_YALIGN_8" value="1"/> 4775 </enum> 4776 4777 <reg32 offset="0xa9db" name="SP_CS_WGE_CNTL" variants="A7XX-" usage="compute"> 4778 <!-- gl_LocalInvocationIndex --> 4779 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 4780 <!-- Must match SP_CS_CTRL --> 4781 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> 4782 <doc> 4783 When this bit is enabled, the dispatch order interleaves 4784 the z coordinate instead of launching all workgroups 4785 with z=0, then all with z=1 and so on. 4786 </doc> 4787 <bitfield name="WORKGROUPRASTORDERZFIRSTEN" pos="11" type="boolean"/> 4788 <doc> 4789 When both fields are non-0 then the dispatcher uses 4790 these tile sizes to launch workgroups in a tiled manner 4791 when the x and y workgroup counts are 4792 both more than 1. 4793 </doc> 4794 <bitfield name="WGTILEWIDTH" low="20" high="25"/> 4795 <bitfield name="WGTILEHEIGHT" low="26" high="31"/> 4796 </reg32> 4797 4798 <reg32 offset="0xa9df" name="SP_CS_NDRANGE_7" variants="A7XX-" usage="compute"> 4799 <!-- The size of the last workgroup. localsize is value minus one: --> 4800 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 4801 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 4802 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 4803 </reg32> 4804 4805 <reg32 offset="0xb9a0" name="HLSQ_LOAD_STATE_FRAG_CMD"/> 4806 <reg64 offset="0xb9a1" name="HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR" align="16" type="address"/> 4807 <reg32 offset="0xb9a3" name="HLSQ_LOAD_STATE_FRAG_DATA"/> 4808 4809 <!-- mirror of SP_CS_BINDLESS_BASE --> 4810 <array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="compute"> 4811 <reg64 offset="0" name="DESCRIPTOR"> 4812 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4813 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4814 </reg64> 4815 </array> 4816 4817 <!-- new in a6xx gen4, mirror of SP_CS_CNTL_1? --> 4818 <reg32 offset="0xb9d0" name="HLSQ_CS_CTRL_REG1" variants="A6XX" usage="compute"> 4819 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"/> 4820 <bitfield name="CONSTANTRAMMODE" low="5" high="6" type="a6xx_const_ram_mode"/> 4821 </reg32> 4822 4823 <reg32 offset="0xbb00" name="SP_DRAW_INITIATOR" variants="A6XX"> 4824 <bitfield name="STATE_ID" low="0" high="7"/> 4825 </reg32> 4826 4827 <reg32 offset="0xbb01" name="SP_KERNEL_INITIATOR" variants="A6XX"> 4828 <bitfield name="STATE_ID" low="0" high="7"/> 4829 </reg32> 4830 4831 <reg32 offset="0xbb02" name="SP_EVENT_INITIATOR" variants="A6XX"> 4832 <!-- I think only the low bit is actually used? --> 4833 <bitfield name="STATE_ID" low="16" high="23"/> 4834 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 4835 </reg32> 4836 4837 <reg32 offset="0xbb08" name="SP_UPDATE_CNTL" variants="A6XX" usage="cmd,compute"> 4838 <doc> 4839 This register clears pending loads queued up by 4840 CP_LOAD_STATE6. Each bit resets a particular kind(s) of 4841 CP_LOAD_STATE6. 4842 </doc> 4843 4844 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers --> 4845 <bitfield name="VS_STATE" pos="0" type="boolean"/> 4846 <bitfield name="HS_STATE" pos="1" type="boolean"/> 4847 <bitfield name="DS_STATE" pos="2" type="boolean"/> 4848 <bitfield name="GS_STATE" pos="3" type="boolean"/> 4849 <bitfield name="FS_STATE" pos="4" type="boolean"/> 4850 <bitfield name="CS_STATE" pos="5" type="boolean"/> 4851 4852 <bitfield name="CS_UAV" pos="6" type="boolean"/> 4853 <bitfield name="GFX_UAV" pos="7" type="boolean"/> 4854 4855 <!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 --> 4856 <bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/> 4857 <bitfield name="GFX_SHARED_CONST" pos="8" type="boolean"/> 4858 4859 <!-- SS6_BINDLESS: one bit per bindless base --> 4860 <bitfield name="CS_BINDLESS" low="9" high="13" type="hex"/> 4861 <bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/> 4862 </reg32> 4863 4864 <reg32 offset="0xab1c" name="SP_DRAW_INITIATOR" variants="A7XX-"> 4865 <bitfield name="STATE_ID" low="0" high="7"/> 4866 </reg32> 4867 4868 <reg32 offset="0xab1d" name="SP_KERNEL_INITIATOR" variants="A7XX-"> 4869 <bitfield name="STATE_ID" low="0" high="7"/> 4870 </reg32> 4871 4872 <reg32 offset="0xab1e" name="SP_EVENT_INITIATOR" variants="A7XX-"> 4873 <bitfield name="STATE_ID" low="16" high="23"/> 4874 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 4875 </reg32> 4876 4877 <reg32 offset="0xab1f" name="SP_UPDATE_CNTL" variants="A7XX" usage="cmd,compute"> 4878 <doc> 4879 This register clears pending loads queued up by 4880 CP_LOAD_STATE6. Each bit resets a particular kind(s) of 4881 CP_LOAD_STATE6. 4882 </doc> 4883 4884 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers --> 4885 <bitfield name="VS_STATE" pos="0" type="boolean"/> 4886 <bitfield name="HS_STATE" pos="1" type="boolean"/> 4887 <bitfield name="DS_STATE" pos="2" type="boolean"/> 4888 <bitfield name="GS_STATE" pos="3" type="boolean"/> 4889 <bitfield name="FS_STATE" pos="4" type="boolean"/> 4890 <bitfield name="CS_STATE" pos="5" type="boolean"/> 4891 4892 <bitfield name="CS_UAV" pos="6" type="boolean"/> 4893 <bitfield name="GFX_UAV" pos="7" type="boolean"/> 4894 4895 <!-- SS6_BINDLESS: one bit per bindless base --> 4896 <bitfield name="CS_BINDLESS" low="9" high="16" type="hex"/> 4897 <bitfield name="GFX_BINDLESS" low="17" high="24" type="hex"/> 4898 </reg32> 4899 4900 <reg32 offset="0xab1f" name="SP_UPDATE_CNTL" variants="A8XX" usage="cmd,compute"> 4901 <doc> 4902 This register clears pending loads queued up by 4903 CP_LOAD_STATE6. Each bit resets a particular kind(s) of 4904 CP_LOAD_STATE6. 4905 </doc> 4906 4907 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers --> 4908 <bitfield name="VS_STATE" pos="0" type="boolean"/> 4909 <bitfield name="HS_STATE" pos="1" type="boolean"/> 4910 <bitfield name="DS_STATE" pos="2" type="boolean"/> 4911 <bitfield name="GS_STATE" pos="3" type="boolean"/> 4912 <bitfield name="FS_STATE" pos="4" type="boolean"/> 4913 <bitfield name="CS_STATE" pos="5" type="boolean"/> 4914 </reg32> 4915 4916 <reg32 offset="0xa9c0" name="SP_CS_BINDLESS_INVALIDATE" usage="compute"/> 4917 <reg32 offset="0xab08" name="SP_GFX_BINDLESS_INVALIDATE" usage="draw"/> 4918 4919 <reg32 offset="0xbb10" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="draw"/> 4920 <reg32 offset="0xab03" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="draw"/> 4921 4922 <array offset="0xab40" name="SP_SHARED_CONSTANT_GFX" stride="1" length="64" variants="A7XX" usage="draw"/> 4923 <array offset="0xab30" name="SP_SHARED_CONSTANT_GFX" stride="1" length="128" variants="A8XX-" usage="draw"/> 4924 4925 <reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd,compute"> 4926 <doc> 4927 Shared constants are intended to be used for Vulkan push 4928 constants. When enabled, 8 vec4's are reserved in the FS 4929 const pool and 16 in the geometry const pool although 4930 only 8 are actually used (why?) and they are mapped to 4931 c504-c511 in each stage. Both VS and FS shared consts 4932 are written using ST6_CONSTANTS/SB6_UAV, so that both 4933 the geometry and FS shared consts can be written at once 4934 by using CP_LOAD_STATE6 rather than 4935 CP_LOAD_STATE6_FRAG/CP_LOAD_STATE6_GEOM. In addition 4936 DST_OFF and NUM_UNIT are in units of dwords instead of 4937 vec4's. 4938 4939 There is also a separate shared constant pool for CS, 4940 which is loaded through CP_LOAD_STATE6_FRAG with 4941 ST6_UBO/ST6_UAV. However the only real difference for CS 4942 is the dword units. 4943 </doc> 4944 <bitfield name="ENABLE" pos="0" type="boolean"/> 4945 </reg32> 4946 4947 <!-- mirror of SP_GFX_BINDLESS_BASE --> 4948 <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd"> 4949 <reg64 offset="0" name="DESCRIPTOR"> 4950 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4951 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4952 </reg64> 4953 </array> 4954 4955 <reg32 offset="0xbd80" name="HLSQ_2D_EVENT_CMD"> 4956 <bitfield name="STATE_ID" low="8" high="15"/> 4957 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 4958 </reg32> 4959 4960 <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="init"/> <!-- all bits valid except bit 29 --> 4961 <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6" variants="A6XX" usage="init"/> 4962 <reg32 offset="0xbe04" name="HLSQ_DBG_ECO_CNTL" variants="A6XX" usage="init"/> 4963 <reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 4964 <reg32 offset="0xbe08" name="HLSQ_UNKNOWN_BE08" low="0" high="15"/> 4965 <array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/> 4966 4967 <!-- TODO: some valid registers between 0xbe20 and 0xbe33 --> 4968 <reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE" variants="A6XX"/> 4969 4970 <reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX-"/> 4971 4972 <!-- Don't know if these are SP, always 0 --> 4973 <reg64 offset="0x0ce2" name="SP_UNKNOWN_0CE2" variants="A7XX-" usage="cmd"/> 4974 <reg64 offset="0x0ce4" name="SP_UNKNOWN_0CE4" variants="A7XX-" usage="cmd"/> 4975 <reg64 offset="0x0ce6" name="SP_UNKNOWN_0CE6" variants="A7XX-" usage="cmd"/> 4976 4977 <!-- 4978 These special registers signal the beginning/end of an event 4979 sequence. The sequence used internally for an event looks like: 4980 - write EVENT_CMD pipe register 4981 - write CP_EVENT_START 4982 - write SP_EVENT_INITIATOR with event or SP_DRAW_INITIATOR 4983 - write PC_EVENT_INITIATOR with event or PC_DRAW_INITIATOR 4984 - write SP_EVENT_INITIATOR(CONTEXT_DONE) 4985 - write PC_EVENT_INITIATOR(CONTEXT_DONE) 4986 - write CP_EVENT_END 4987 Writing to CP_EVENT_END seems to actually trigger the context roll 4988 --> 4989 <reg32 offset="0xd600" name="CP_EVENT_START"> 4990 <bitfield name="STATE_ID" low="0" high="7"/> 4991 </reg32> 4992 <reg32 offset="0xd601" name="CP_EVENT_END"> 4993 <bitfield name="STATE_ID" low="0" high="7"/> 4994 </reg32> 4995 <reg32 offset="0xd700" name="CP_2D_EVENT_START"> 4996 <bitfield name="STATE_ID" low="0" high="7"/> 4997 </reg32> 4998 <reg32 offset="0xd701" name="CP_2D_EVENT_END"> 4999 <bitfield name="STATE_ID" low="0" high="7"/> 5000 </reg32> 5001</domain> 5002 5003<domain name="A6XX_PDC" width="32"> 5004 <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/> 5005 <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/> 5006 <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/> 5007 <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/> 5008 <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/> 5009 <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/> 5010 <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/> 5011 <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/> 5012 <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/> 5013 <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/> 5014 <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/> 5015 <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/> 5016 <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/> 5017 <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/> 5018 <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/> 5019 <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/> 5020 <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/> 5021 <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/> 5022 <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/> 5023 <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/> 5024 <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/> 5025 <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/> 5026 <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/> 5027 <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/> 5028 <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/> 5029 <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/> 5030</domain> 5031 5032<domain name="A6XX_PDC_GPU_SEQ" width="32"> 5033 <reg32 offset="0x0" name="MEM_0"/> 5034</domain> 5035 5036<domain name="A6XX_CX_DBGC" width="32"> 5037 <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A"> 5038 <bitfield high="7" low="0" name="PING_INDEX"/> 5039 <bitfield high="15" low="8" name="PING_BLK_SEL"/> 5040 </reg32> 5041 <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/> 5042 <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/> 5043 <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/> 5044 <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT"> 5045 <bitfield high="5" low="0" name="TRACEEN"/> 5046 <bitfield high="14" low="12" name="GRANU"/> 5047 <bitfield high="31" low="28" name="SEGT"/> 5048 </reg32> 5049 <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM"> 5050 <bitfield high="27" low="24" name="ENABLE"/> 5051 </reg32> 5052 <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/> 5053 <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/> 5054 <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/> 5055 <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/> 5056 <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/> 5057 <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/> 5058 <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/> 5059 <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/> 5060 <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0"> 5061 <bitfield high="3" low="0" name="BYTEL0"/> 5062 <bitfield high="7" low="4" name="BYTEL1"/> 5063 <bitfield high="11" low="8" name="BYTEL2"/> 5064 <bitfield high="15" low="12" name="BYTEL3"/> 5065 <bitfield high="19" low="16" name="BYTEL4"/> 5066 <bitfield high="23" low="20" name="BYTEL5"/> 5067 <bitfield high="27" low="24" name="BYTEL6"/> 5068 <bitfield high="31" low="28" name="BYTEL7"/> 5069 </reg32> 5070 <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1"> 5071 <bitfield high="3" low="0" name="BYTEL8"/> 5072 <bitfield high="7" low="4" name="BYTEL9"/> 5073 <bitfield high="11" low="8" name="BYTEL10"/> 5074 <bitfield high="15" low="12" name="BYTEL11"/> 5075 <bitfield high="19" low="16" name="BYTEL12"/> 5076 <bitfield high="23" low="20" name="BYTEL13"/> 5077 <bitfield high="27" low="24" name="BYTEL14"/> 5078 <bitfield high="31" low="28" name="BYTEL15"/> 5079 </reg32> 5080 5081 <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/> 5082 <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/> 5083</domain> 5084 5085<domain name="A7XX_CX_DBGC" width="32" varset="chip"> 5086 <!-- Bitfields shifted, but otherwise the same: --> 5087 <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A" variants="A7XX-"> 5088 <bitfield high="7" low="0" name="PING_INDEX"/> 5089 <bitfield high="24" low="16" name="PING_BLK_SEL"/> 5090 </reg32> 5091</domain> 5092 5093<domain name="A6XX_CX_MISC" width="32" prefix="variant" varset="chip"> 5094 <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/> 5095 <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/> 5096 <reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/> 5097 <reg32 offset="0x0087" name="CX_MISC_SLICE_ENABLE_FINAL" variants="A8XX"/> 5098 <reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-"> 5099 <bitfield pos="0" name="FASTBLEND" type="boolean"/> 5100 <bitfield pos="1" name="LPAC" type="boolean"/> 5101 <bitfield pos="2" name="RAYTRACING" type="boolean"/> 5102 </reg32> 5103 <reg32 offset="0x0405" name="CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS" variants="A8XX-"> 5104 <bitfield high="8" low="0" name="FINALFREQLIMIT"/> 5105 <bitfield pos="24" name="SOFTSKUDISABLED" type="boolean"/> 5106 </reg32> 5107</domain> 5108 5109</database> 5110