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Searched +full:coresight +full:- +full:dynamic +full:- +full:funnel (Results 1 – 13 of 13) sorted by relevance

/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3660-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * dtsi for Hisilicon Hi3660 Coresight
6 * Copyright (C) 2016-2018 HiSilicon Ltd.
15 compatible = "arm,coresight-etm4x", "arm,primecell";
18 clock-names = "apb_pclk";
20 arm,coresight-loses-context-with-cpu;
22 out-ports {
25 remote-endpoint =
33 compatible = "arm,coresight-etm4x", "arm,primecell";
36 clock-names = "apb_pclk";
[all …]
H A Dhi6220-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * dtsi file for Hisilicon Hi6220 coresight
13 funnel@f6401000 {
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
17 clock-names = "apb_pclk";
19 out-ports {
22 remote-endpoint =
28 in-ports {
31 remote-endpoint =
39 compatible = "arm,coresight-tmc", "arm,primecell";
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/linux/arch/arm64/boot/dts/sprd/
H A Dsc9860.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
52 compatible = "arm,cortex-a53";
54 enable-method = "psci";
55 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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H A Dums512.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
20 cpu-map {
51 compatible = "arm,cortex-a55";
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H A Dsc9836.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #address-cells = <2>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
22 enable-method = "psci";
27 compatible = "arm,cortex-a53";
29 enable-method = "psci";
34 compatible = "arm,cortex-a53";
36 enable-method = "psci";
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/linux/arch/arm/boot/dts/hisilicon/
H A Dhip04.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 HiSilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
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/linux/arch/arm64/boot/dts/arm/
H A Djuno-cs-r1r2.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 funnel@20130000 { /* cssys1 */
4 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
8 clock-names = "apb_pclk";
9 power-domains = <&scpi_devpd 0>;
10 out-ports {
13 remote-endpoint = <&etf1_in_port>;
17 in-ports {
27 compatible = "arm,coresight-tmc", "arm,primecell";
31 clock-names = "apb_pclk";
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H A Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 #address-cells = <1>;
14 #size-cells = <1>;
18 frame-number = <1>;
30 #mbox-cells = <1>;
32 clock-names = "apb_pclk";
36 compatible = "arm,mmu-400", "arm,smmu-v1";
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/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
8 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
11 #include <dt-bindings/gpio/gpio.h>
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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/linux/arch/arm/boot/dts/st/
H A Dste-dbx5x0.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/ste-db8500-clkout.h>
9 #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
10 #include <dt-bindings/mfd/dbx500-prcmu.h>
11 #include <dt-bindings/arm/ux500_pm_domains.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/thermal/thermal.h>
16 #address-cells = <1>;
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