| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | intel,ce4100-lapic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Local Advanced Programmable Interrupt Controller (LAPIC)
10 - Rahul Tanwar <rtanwar@maxlinear.com>
13 Intel's Advanced Programmable Interrupt Controller (APIC) is a
15 architecture design, with a local component (LAPIC) integrated
16 into the processor itself and an external I/O APIC. Local APIC
26 This schema defines bindings for local APIC interrupt controller.
[all …]
|
| H A D | mti,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPS Global Interrupt Controller
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
[all …]
|
| H A D | intel,ce4100-ioapic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
10 - Rahul Tanwar <rtanwar@maxlinear.com>
13 Intel's Advanced Programmable Interrupt Controller (APIC) is a
15 architecture design, with a local component (LAPIC) integrated
16 into the processor itself and an external I/O APIC. Local APIC
26 This schema defines bindings for I/O APIC interrupt controller.
[all …]
|
| H A D | riscv,cpu-intc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
12 software. Some of these CSRs are used to control local interrupts connected
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
[all …]
|
| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | samsung,exynos4210-mct.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
17 down-counters and generate an interrupt when the counter expires. There is
18 one CPU local timer instantiated in MCT for every CPU in the system.
[all …]
|
| /linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | thead,th1520-mbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/thead,th1520-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-head TH1520 Mailbox Controller
10 The T-head mailbox controller enables communication and coordination between
13 using interrupts via the Interrupt Controller Unit (ICU).
16 - Michal Wilczynski <m.wilczynski@samsung.com>
20 const: thead,th1520-mbox
24 - description: Clock for the local mailbox
[all …]
|
| /linux/Documentation/devicetree/bindings/clock/ti/davinci/ |
| H A D | psc.txt | 1 Binding for TI DaVinci Power Sleep Controller (PSC)
7 - compatible: shall be one of:
8 - "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
9 - "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
10 - reg: physical base address and size of the controller's register area
11 - #clock-cells: from common clock binding; shall be set to 1
12 - #power-domain-cells: from generic power domain binding; shall be set to 1.
13 - clocks: phandles to clocks corresponding to the clock-names property
14 - clock-names: list of parent clock names - depends on compatible value
15 - for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | recommended.json | 4 "BriefDescription": "Execution-time branch misprediction ratio (non-speculative).",
150 "BriefDescription": "L1 demand data cache fills from local L2 cache.",
216 "BriefDescription": "Macro-ops dispatched.",
227 "BriefDescription": "Macro-ops retired.",
232 "BriefDescription": "DRAM read data for local processor.",
236 "ScaleUnit": "6.103515625e-5MiB"
240 "BriefDescription": "DRAM write data for local processor.",
244 "ScaleUnit": "6.103515625e-5MiB"
252 "ScaleUnit": "6.103515625e-5MiB"
260 "ScaleUnit": "6.103515625e-5MiB"
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | uncore-cache.json | 9 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
21 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
27 "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode",
33 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
45 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
57 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
69 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
81 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
93 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misse
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | uncore-cache.json | 9 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
21 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
27 "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode",
33 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
45 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
57 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
69 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
81 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
93 "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misse
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | uncore-cache.json | 23 "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
32 "PublicDescription": "Counts the number of cycles either the local distress or incoming distress signals are asserted. Incoming distress includes both up and dn.",
41 "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
51 "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
61 "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
71 "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standar
[all...] |
| /linux/Documentation/devicetree/bindings/net/ |
| H A D | mctp-i2c-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mctp-i2c-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matt Johnston <matt@codeconstruct.com.au>
13 An mctp-i2c-controller defines a local MCTP endpoint on an I2C controller.
16 An mctp-i2c-controller must be attached to an I2C adapter which supports
18 busses) are attached to the mctp-i2c-controller with a 'mctp-controller'
19 property on each used bus. Each mctp-controller I2C bus will be presented
24 const: mctp-i2c-controller
[all …]
|
| H A D | asix,ax88796c.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Łukasz Stelmach <l.stelmach@samsung.com>
13 ASIX AX88796C is an Ethernet controller with a built in PHY. This
16 The node for this driver must be a child node of an SPI controller,
18 ../spi/spi-controller.yaml must be specified.
21 - $ref: ethernet-controller.yaml#
22 - $ref: /schemas/spi/spi-peripheral-props.yaml
31 spi-max-frequency:
[all …]
|
| H A D | marvell-orion-net.txt | 1 Marvell Orion/Discovery ethernet controller
4 The Marvell Discovery ethernet controller can be found on Marvell Orion SoCs
6 Discovery system controller chips (mv64[345]60).
8 The Discovery ethernet controller is described with two levels of nodes. The
9 first level describes the ethernet controller itself and the second level
10 describes up to 3 ethernet port nodes within that controller. The reason for
12 set of controller registers. Each port node describes port-specific properties.
15 For Orion SoCs we stick to the separation, although there each controller has
16 only one port associated. Multiple ports are implemented as multiple single-port
20 * Ethernet controller node
[all …]
|
| H A D | davicom,dm9051.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Davicom DM9051 SPI Ethernet Controller
10 - Joseph CHANG <josright123@gmail.com>
13 The DM9051 is a fully integrated and cost-effective low pin count single
14 chip Fast Ethernet controller with a Serial Peripheral Interface (SPI).
17 - $ref: ethernet-controller.yaml#
26 spi-max-frequency:
32 local-mac-address: true
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | uncore-cache.json | 15 …ed in Counter 0. The filtering available is found in the control register - threshold, invert an…
24 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
34 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
44 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
54 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
64 …- this includes code, data, prefetches and hints coming from L2. This has numerous filters availa…
209 "BriefDescription": "LRU Queue; Non-0 Aged Victim",
214 "PublicDescription": "How often we picked a victim that had a non-zero age",
224 …T -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP directio…
234 …T -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP directio…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | memory.json | 172 …y accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) t…
188 …fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, o…
194 …fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, o…
210 … that were supplied by DRAM on a distant memory controller of this socket when the system is in SN…
216 … that were supplied by DRAM on a distant memory controller of this socket when the system is in SN…
232 …"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2,…
238 …"PublicDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2…
265 … that were supplied by DRAM on a distant memory controller of this socket when the system is in SN…
271 … that were supplied by DRAM on a distant memory controller of this socket when the system is in SN…
287 …fetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, o…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | memory.json | 172 …y accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) t…
188 …fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, o…
194 …fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, o…
210 … that were supplied by DRAM on a distant memory controller of this socket when the system is in SN…
216 … that were supplied by DRAM on a distant memory controller of this socket when the system is in SN…
232 …"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2,…
238 …"PublicDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2…
265 … that were supplied by DRAM on a distant memory controller of this socket when the system is in SN…
271 … that were supplied by DRAM on a distant memory controller of this socket when the system is in SN…
287 …fetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, o…
[all …]
|
| /linux/drivers/net/can/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
8 Controller Area Network (CAN) is serial communications protocol up to
10 to 8Mbit/s for the more recent CAN with Flexible Data-Rate
11 (CAN-FD). The CAN bus was originally mainly for automotive, but is now
16 This section contains all the CAN(-FD) device drivers including the
21 can-dev.
26 tristate "Virtual Local CA
[all...] |
| /linux/arch/alpha/kernel/ |
| H A D | smc37c669.c | 52 * Super I/O controller.
60 * er 28-Jan-1997 Initial Entry
69 ** The mask acts as a flag used in mapping actual ISA IRQs (0 - 15)
70 ** to device IRQs (A - H).
84 ** channels to device DMA channels (A - C).
218 ** CR00 - default value 0x28
221 ** 0x - 30ua pull-ups on nIDEEN, nHDCS0, NHDCS1
222 ** 11 - IRQ_H available as IRQ output,
224 ** 10 - nIDEEN, nHDCS0, nHDCS1 used to control IDE
247 ** CR01 - default value 0x9C
[all …]
|
| /linux/Documentation/devicetree/bindings/i2c/ |
| H A D | i2c-pxa-pci-ce4100.txt | 2 ----------
4 CE4100 has one PCI device which is described as the I2C-Controller. This
5 PCI device has three PCI-bars, each bar contains a complete I2C
6 controller. So we have a total of three independent I2C-Controllers
8 The driver is probed via the PCI-ID and is gathering the information of
10 Grant Likely recommended to use the ranges property to map the PCI-Bar
12 of the specific I2C controller. This were his exact words:
16 (middle group of 3) is translated to the local
19 the first cell of the local address is chosen to be
22 non-zero if you had 2 or more devices mapped off
[all …]
|
| /linux/kernel/ |
| H A D | cpu_pm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
53 * cpu_pm_register_notifier - register a driver with cpu_pm
74 * cpu_pm_unregister_notifier - unregister a driver with cpu_pm
94 * cpu_pm_enter - CPU low power entry notifier
102 * co-processor, interrupt controller and its PM extensions, local CPU
115 * cpu_pm_exit - CPU low power exit notifier
120 * Notified drivers can include VFP co-processor, interrupt controller
121 * and its PM extensions, local CPU timers context save/restore which
133 * cpu_cluster_pm_enter - CPU cluster low power entry notifier
140 * domain. Notified drivers can include VFP co-processor, interrupt controller
[all …]
|
| /linux/Documentation/core-api/ |
| H A D | debugging-via-ohci1394.rst | 2 Using physical DMA provided by OHCI-1394 FireWire controllers for debugging
6 ------------
9 to the OHCI-1394 specification which defines the controller to be a PCI
12 PCI-Bus master DMA after applying filters defined by the OHCI-1394 driver.
15 ask the OHCI-1394 controller to perform read and write requests on
28 hardware such as x86, x86-64 and PowerPC.
34 Together with a early initialization of the OHCI-1394 controller for debugging,
41 -------
43 The firewire-ohci driver in drivers/firewire uses filtered physical
47 Because the firewire-ohci driver depends on the PCI enumeration to be
[all …]
|
| /linux/Documentation/nvme/ |
| H A D | nvme-pci-endpoint-target.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 The NVMe PCI endpoint function target driver implements an NVMe PCIe controller
10 using an NVMe fabrics target controller configured with the PCI transport type.
16 controller over a PCIe link, thus implementing an NVMe PCIe device similar to a
17 regular M.2 SSD. The target controller is created in the same manner as when
18 using NVMe over fabrics: the controller represents the interface to an NVMe
22 existing physical NVMe device or an NVMe fabrics host controller (e.g. a NVMe
23 TCP host controller).
51 data buffer is transferred from the host into a local memory buffer before
52 executing the command using the target core code. For read commands, a local
[all …]
|
| /linux/arch/mips/boot/dts/cavium-octeon/ |
| H A D | octeon_68xx.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 * use. Because of this, it contains a super-set of the available
11 compatible = "cavium,octeon-6880";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&ciu2>;
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
[all …]
|