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/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn66xx_device.c174 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn66xx_setup_pkt_ctl_regs() local
179 if (CFG_GET_OQ_MAX_Q(cn6xxx->conf) <= 4) in lio_cn66xx_setup_pkt_ctl_regs()
185 if (CFG_GET_IS_SLI_BP_ON(cn6xxx->conf)) in lio_cn66xx_setup_pkt_ctl_regs()
196 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn6xxx_setup_global_output_regs() local
202 if (CFG_GET_IS_SLI_BP_ON(cn6xxx->conf)) { in lio_cn6xxx_setup_global_output_regs()
239 (u32)CFG_GET_OQ_INTR_PKT(cn6xxx->conf)); in lio_cn6xxx_setup_global_output_regs()
242 CFG_GET_OQ_INTR_TIME(cn6xxx->conf)); in lio_cn6xxx_setup_global_output_regs()
473 struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; in lio_cn6xxx_enable_interrupt() local
474 u64 mask = cn6xxx->intr_mask64 | CN6XXX_INTR_DMA0_FORCE; in lio_cn6xxx_enable_interrupt()
477 writeq(mask, cn6xxx->intr_enb_reg64); in lio_cn6xxx_enable_interrupt()
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H A Docteon_droq.c243 struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx); in octeon_init_droq()
828 struct octeon_cn6xxx *cn6xxx = in octeon_enable_irq() local
834 (&cn6xxx->lock_for_droq_int_enb_reg, flags); in octeon_enable_irq()
845 (&cn6xxx->lock_for_droq_int_enb_reg, flags); in octeon_enable_irq()
H A Dcn66xx_device.h25 /* Register address and configuration for a CN6XXX devices.
H A Docteon_device.c881 CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn6xxx)); in octeon_setup_instr_queues()
926 CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn6xxx)); in octeon_setup_output_queues()
928 CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn6xxx)); in octeon_setup_output_queues()
1209 CFG_GET_NUM_NIC_PORTS(CHIP_CONF(oct, cn6xxx)); in octeon_core_drv_init()
1313 (struct octeon_config *)(CHIP_CONF(oct, cn6xxx)); in octeon_get_conf()
H A Docteon_config.h42 /* CN6xxx IQ configuration macros */
49 /* CN6xxx OQ configuration macros */
H A Dcn68xx_device.c76 max_oqs = CFG_GET_OQ_MAX_Q(CHIP_CONF(oct, cn6xxx)); in lio_cn68xx_setup_pkt_ctl_regs()
H A Dlio_ethtool.c507 struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx); in lio_ethtool_get_channels()
965 struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx); in lio_ethtool_get_ringparam()
2145 struct octeon_cn6xxx *cn6xxx = in lio_get_intr_coalesce() local
2150 CFG_GET_OQ_INTR_TIME(cn6xxx->conf); in lio_get_intr_coalesce()
2152 CFG_GET_OQ_INTR_PKT(cn6xxx->conf); in lio_get_intr_coalesce()
2238 struct octeon_cn6xxx *cn6xxx = in oct_cfg_rx_intrcnt() local
2248 CFG_SET_OQ_INTR_PKT(cn6xxx->conf, rx_max_coalesced_frames); in oct_cfg_rx_intrcnt()
2311 struct octeon_cn6xxx *cn6xxx = in oct_cfg_rx_intrtime() local
2324 CFG_SET_OQ_INTR_TIME(cn6xxx->conf, rx_coalesce_usecs); in oct_cfg_rx_intrtime()
H A Drequest_manager.c59 conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn6xxx))); in octeon_init_instr_queue()
166 CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn6xxx)); in octeon_delete_instr_queue()
H A Dcn66xx_regs.h448 /* CN6XXX BAR1 Index registers. */
H A Dlio_main.c1112 * if it is a CN6XXX OR the LAST CN23XX device. in octeon_destroy_resources()
3481 cn6xxx)); in setup_nic_devices()
/linux/Documentation/devicetree/bindings/net/
H A Dcavium-pip.txt12 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
23 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
34 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
H A Dcavium-mix.txt6 Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX
H A Dcavium-mdio.txt7 and cn6XXX SOCs.
/linux/drivers/net/ethernet/cavium/
H A DKconfig85 tristate "Octeon Management port ethernet driver (CN5XXX, CN6XXX)"
93 CN54XX, CN52XX, and CN6XXX chips.
/linux/Documentation/devicetree/bindings/mips/cavium/
H A Ddma-engine.txt10 Compatibility with all cn52XX, cn56XX and cn6XXX SOCs.
H A Ductl.txt6 Compatibility with all cn6XXX SOCs.
H A Dbootbus.txt9 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-octeon.txt5 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
/linux/arch/mips/include/asm/octeon/
H A Docteon-model.h63 /* Match all cn6XXX Octeon models. */
123 * CN6XXX models with new revision encoding
/linux/arch/mips/pci/
H A Dpcie-octeon.c1349 mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */ in __cvmx_pcie_rc_initialize_gen2()