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/linux/drivers/clocksource/
H A Dmmio.c12 struct clocksource clksrc; member
17 return container_of(c, struct clocksource_mmio, clksrc); in to_mmio_clksrc()
63 cs->clksrc.name = name; in clocksource_mmio_init()
64 cs->clksrc.rating = rating; in clocksource_mmio_init()
65 cs->clksrc.read = read; in clocksource_mmio_init()
66 cs->clksrc.mask = CLOCKSOURCE_MASK(bits); in clocksource_mmio_init()
67 cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; in clocksource_mmio_init()
69 return clocksource_register_hz(&cs->clksrc, hz); in clocksource_mmio_init()
H A Dtimer-sun5i.c41 struct clocksource clksrc; member
48 container_of(x, struct sun5i_timer, clksrc)
141 static u64 sun5i_clksrc_read(struct clocksource *clksrc) in sun5i_clksrc_read() argument
143 struct sun5i_timer *cs = clksrc_to_sun5i_timer(clksrc); in sun5i_clksrc_read()
156 clocksource_unregister(&cs->clksrc); in sun5i_rate_cb()
160 clocksource_register_hz(&cs->clksrc, ndata->new_rate); in sun5i_rate_cb()
183 cs->clksrc.name = pdev->dev.of_node->name; in sun5i_setup_clocksource()
184 cs->clksrc.rating = 340; in sun5i_setup_clocksource()
185 cs->clksrc.read = sun5i_clksrc_read; in sun5i_setup_clocksource()
186 cs->clksrc.mask = CLOCKSOURCE_MASK(32); in sun5i_setup_clocksource()
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H A Dclksrc_st_lpc.c55 "clksrc-st-lpc", rate, 300, 32, in st_clksrc_init()
58 pr_err("clksrc-st-lpc: Failed to register clocksource\n"); in st_clksrc_init()
71 pr_err("clksrc-st-lpc: Failed to get LPC clock\n"); in st_clksrc_setup_clk()
76 pr_err("clksrc-st-lpc: Failed to enable LPC clock\n"); in st_clksrc_setup_clk()
81 pr_err("clksrc-st-lpc: Failed to get LPC clock rate\n"); in st_clksrc_setup_clk()
98 pr_err("clksrc-st-lpc: An LPC mode must be provided\n"); in st_clksrc_of_register()
108 pr_err("clksrc-st-lpc: Unable to map iomem\n"); in st_clksrc_of_register()
126 pr_info("clksrc-st-lpc: clocksource initialised - running @ %luHz\n", in st_clksrc_of_register()
H A Dtimer-atmel-pit.c40 struct clocksource clksrc; member
49 static inline struct pit_data *clksrc_to_pit_data(struct clocksource *clksrc) in clksrc_to_pit_data() argument
51 return container_of(clksrc, struct pit_data, clksrc); in clksrc_to_pit_data()
221 data->clksrc.mask = CLOCKSOURCE_MASK(bits); in at91sam926x_pit_dt_init()
222 data->clksrc.name = "pit"; in at91sam926x_pit_dt_init()
223 data->clksrc.rating = 175; in at91sam926x_pit_dt_init()
224 data->clksrc.read = read_pit_clk; in at91sam926x_pit_dt_init()
225 data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; in at91sam926x_pit_dt_init()
227 ret = clocksource_register_hz(&data->clksrc, pit_rate); in at91sam926x_pit_dt_init()
239 clocksource_unregister(&data->clksrc); in at91sam926x_pit_dt_init()
H A Dtimer-microchip-pit64b.c81 * @clksrc: clocksource
85 struct clocksource clksrc; member
90 struct mchp_pit64b_clksrc, clksrc))
366 cs->clksrc.name = MCHP_PIT64B_NAME; in mchp_pit64b_init_clksrc()
367 cs->clksrc.mask = CLOCKSOURCE_MASK(64); in mchp_pit64b_init_clksrc()
368 cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; in mchp_pit64b_init_clksrc()
369 cs->clksrc.rating = 210; in mchp_pit64b_init_clksrc()
370 cs->clksrc.read = mchp_pit64b_clksrc_read; in mchp_pit64b_init_clksrc()
371 cs->clksrc.suspend = mchp_pit64b_clksrc_suspend; in mchp_pit64b_init_clksrc()
372 cs->clksrc.resume = mchp_pit64b_clksrc_resume; in mchp_pit64b_init_clksrc()
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H A Dtimer-ti-dm-systimer.c714 struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs); in dmtimer_clocksource_read_cycles() local
715 struct dmtimer_systimer *t = &clksrc->t; in dmtimer_clocksource_read_cycles()
729 struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs); in dmtimer_clocksource_suspend() local
730 struct dmtimer_systimer *t = &clksrc->t; in dmtimer_clocksource_suspend()
732 clksrc->loadval = readl_relaxed(t->base + t->counter); in dmtimer_clocksource_suspend()
739 struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs); in dmtimer_clocksource_resume() local
740 struct dmtimer_systimer *t = &clksrc->t; in dmtimer_clocksource_resume()
748 writel_relaxed(clksrc->loadval, t->base + t->counter); in dmtimer_clocksource_resume()
755 struct dmtimer_clocksource *clksrc; in dmtimer_clocksource_init() local
760 clksrc = kzalloc_obj(*clksrc); in dmtimer_clocksource_init()
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H A Dtimer-atmel-tcb.c113 static struct clocksource clksrc = { variable
124 return tc_get_cycles(&clksrc); in tc_sched_clock_read()
129 return tc_get_cycles32(&clksrc); in tc_sched_clock_read32()
136 return tc_get_cycles(&clksrc); in tc_delay_timer_read()
141 return tc_get_cycles32(&clksrc); in tc_delay_timer_read32()
451 clksrc.name = kbasename(node->parent->full_name); in tcb_clksrc_init()
453 pr_debug("%s at %d.%03d MHz\n", clksrc.name, divided_rate / 1000000, in tcb_clksrc_init()
460 clksrc.read = tc_get_cycles32; in tcb_clksrc_init()
481 ret = clocksource_register_hz(&clksrc, divided_rate); in tcb_clksrc_init()
498 clocksource_unregister(&clksrc); in tcb_clksrc_init()
H A Dtimer-loongson1-pwm.c36 struct clocksource clksrc; member
41 return container_of(c, struct ls1x_clocksource, clksrc); in to_ls1x_clksrc()
207 .clksrc = {
231 return clocksource_register_hz(&ls1x_clocksource.clksrc, in ls1x_pwm_clocksource_init()
H A Dtimer-gx6605s.c135 * same timer in gx6605s. We use one for clkevt and another for clksrc. in gx6605s_timer_init()
H A Dtimer-mp-csky.c126 * clksrc. in csky_mptimer_init()
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c44 u64 clksrc; member
67 u64 clksrc; member
97 u64 clksrc; member
107 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); in sja1105_cgu_idiv_packing()
130 idiv.clksrc = 0x0A; /* 25MHz */ in sja1105_cgu_idiv_config()
146 sja1105_packing(buf, &cmd->clksrc, 28, 24, size, op); in sja1105_cgu_mii_control_packing()
171 int clksrc; in sja1105_cgu_mii_tx_clk_config() local
177 clksrc = mac_clk_sources[port]; in sja1105_cgu_mii_tx_clk_config()
179 clksrc = phy_clk_sources[port]; in sja1105_cgu_mii_tx_clk_config()
182 mii_tx_clk.clksrc = clksrc; in sja1105_cgu_mii_tx_clk_config()
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/linux/arch/arm/mach-spear/
H A Dtime.c33 #define CLKSRC 1 /* gpt0, channel1 as clocksource */ macro
75 writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC)); in spear_clocksource_init()
81 writew(0xFFFF, gpt_base + LOAD(CLKSRC)); in spear_clocksource_init()
83 val = readw(gpt_base + CR(CLKSRC)); in spear_clocksource_init()
86 writew(val, gpt_base + CR(CLKSRC)); in spear_clocksource_init()
89 clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate, in spear_clocksource_init()
/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
15 - for "ti,da850-pll1", shall be "clksrc"
60 clock-names = "clksrc", "extclksrc";
84 clock-names = "clksrc";
H A Dda8xx-cfgchip.txt40 - compatible: shall be "ti,da850-async1-clksrc".
48 - compatible: shall be "ti,da850-async3-clksrc".
78 compatible = "ti,da850-async1-clksrc";
84 compatible = "ti,da850-async3-clksrc";
/linux/drivers/clk/davinci/
H A Dpll-da850.c101 clk_register_clkdev(clk, "pll0_sysclk2", "da850-async3-clksrc"); in da850_pll0_init()
104 clk_register_clkdev(clk, "pll0_sysclk3", "da850-async1-clksrc"); in da850_pll0_init()
207 clk_register_clkdev(clk, "pll1_sysclk2", "da850-async3-clksrc"); in da850_pll1_init()
H A Dda8xx-cfgchip.c702 .compatible = "ti,da850-async1-clksrc",
706 .compatible = "ti,da850-async3-clksrc",
726 .name = "da850-async1-clksrc",
730 .name = "da850-async3-clksrc",
/linux/arch/m68k/atari/
H A Ddebug.c219 int clksrc, clkmode, div, reg3, reg5; in atari_init_scc_port() local
227 clksrc = clksrc_table[baud]; in atari_init_scc_port()
232 clksrc = 0x28; /* TRxC */ in atari_init_scc_port()
252 SCC_WRITE(11, clksrc); /* main clock source */ in atari_init_scc_port()
/linux/drivers/memory/tegra/
H A Dtegra210-emc-core.c721 static void tegra210_emc_set_clock(struct tegra210_emc *emc, u32 clksrc) in tegra210_emc_set_clock() argument
723 emc->sequence->set_clock(emc, clksrc); in tegra210_emc_set_clock()
732 u32 clksrc) in tegra210_change_dll_src() argument
738 emc_clk_src = (clksrc & EMC_CLK_EMC_2X_CLK_SRC_MASK) >> in tegra210_change_dll_src()
740 emc_clk_div = (clksrc & EMC_CLK_EMC_2X_CLK_DIVISOR_MASK) >> in tegra210_change_dll_src()
793 u32 clksrc; in tegra210_emc_set_refresh() local
795 clksrc = emc->provider.configs[index].value | in tegra210_emc_set_refresh()
801 tegra210_emc_set_clock(emc, clksrc); in tegra210_emc_set_refresh()
840 void tegra210_emc_do_clock_change(struct tegra210_emc *emc, u32 clksrc) in tegra210_emc_do_clock_change() argument
847 tegra210_clk_emc_update_setting(clksrc); in tegra210_emc_do_clock_change()
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H A Dtegra210-emc-cc-r21021.c337 static void tegra210_emc_r21021_set_clock(struct tegra210_emc *emc, u32 clksrc) in tegra210_emc_r21021_set_clock() argument
431 emc_dbg(emc, INFO, "Next EMC clksrc: 0x%08x\n", clksrc); in tegra210_emc_r21021_set_clock()
432 emc_dbg(emc, INFO, "DLL clksrc: 0x%08x\n", next->dll_clk_src); in tegra210_emc_r21021_set_clock()
573 value = tegra210_emc_dll_prelock(emc, clksrc); in tegra210_emc_r21021_set_clock()
1394 tegra210_emc_do_clock_change(emc, clksrc); in tegra210_emc_r21021_set_clock()
H A Dtegra210-emc.h939 void (*set_clock)(struct tegra210_emc *emc, u32 clksrc);
994 void tegra210_emc_do_clock_change(struct tegra210_emc *emc, u32 clksrc);
1008 u32 tegra210_emc_dll_prelock(struct tegra210_emc *emc, u32 clksrc);
/linux/drivers/net/can/mscan/
H A Dmpc5xxx_can.c134 /* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to in mpc512x_can_get_clock()
138 * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC] in mpc512x_can_get_clock()
207 dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n", in mpc512x_can_get_clock()
229 dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n", in mpc512x_can_get_clock()
/linux/sound/soc/codecs/
H A Dcs35l36.c52 int clksrc; member
999 prev_clksrc = cs35l36->clksrc; in cs35l36_component_set_sysclk()
1003 cs35l36->clksrc = CS35L36_PLLSRC_SCLK; in cs35l36_component_set_sysclk()
1006 cs35l36->clksrc = CS35L36_PLLSRC_LRCLK; in cs35l36_component_set_sysclk()
1009 cs35l36->clksrc = CS35L36_PLLSRC_PDMCLK; in cs35l36_component_set_sysclk()
1012 cs35l36->clksrc = CS35L36_PLLSRC_SELF; in cs35l36_component_set_sysclk()
1015 cs35l36->clksrc = CS35L36_PLLSRC_MCLK; in cs35l36_component_set_sysclk()
1038 cs35l36->clksrc); in cs35l36_component_set_sysclk()
1069 if (cs35l36->clksrc == CS35L36_PLLSRC_PDMCLK) { in cs35l36_component_set_sysclk()
/linux/drivers/gpu/drm/renesas/shmobile/
H A Dshmob_drm_drv.c41 enum shmob_drm_clk_source clksrc) in shmob_drm_setup_clocks() argument
46 switch (clksrc) { in shmob_drm_setup_clocks()
/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850.dtsi139 clock-names = "clksrc", "extclksrc";
407 compatible = "ti,da850-async1-clksrc";
413 compatible = "ti,da850-async3-clksrc";
700 clock-names = "clksrc";
/linux/include/linux/
H A Dsm501.h13 int clksrc, unsigned long freq);

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