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Searched full:clk_sel (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-visconti.c59 unsigned long clk_sel, val; in visconti_eth_set_clk_tx_rate() local
64 clk_sel = ETHER_CLK_SEL_FREQ_SEL_125M; in visconti_eth_set_clk_tx_rate()
68 clk_sel = ETHER_CLK_SEL_FREQ_SEL_25M; in visconti_eth_set_clk_tx_rate()
72 clk_sel = ETHER_CLK_SEL_FREQ_SEL_2P5M; in visconti_eth_set_clk_tx_rate()
87 val = clk_sel | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC; in visconti_eth_set_clk_tx_rate()
98 clk_sel = ETHER_CLK_SEL_DIV_SEL_2; in visconti_eth_set_clk_tx_rate()
102 clk_sel = ETHER_CLK_SEL_DIV_SEL_20; in visconti_eth_set_clk_tx_rate()
117 val = clk_sel | ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV | in visconti_eth_set_clk_tx_rate()
/linux/drivers/gpu/drm/imx/ipuv3/
H A Dimx-ldb.c87 struct clk *clk_sel[4]; /* parent of display clock */ member
88 struct clk *clk_parent[4]; /* original parent of clk_sel */
141 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); in imx_ldb_set_clock()
155 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) { in imx_ldb_encoder_enable()
161 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]); in imx_ldb_encoder_enable()
162 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]); in imx_ldb_encoder_enable()
167 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]); in imx_ldb_encoder_enable()
214 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) { in imx_ldb_encoder_atomic_mode_set()
302 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]); in imx_ldb_encoder_disable()
541 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname); in imx_ldb_probe()
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/linux/drivers/clk/sophgo/
H A Dclk-cv18xx-ip.c684 if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel)) in mmux_recalc_rate()
707 if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel)) in mmux_set_rate()
723 s8 clk_sel; in mmux_get_parent() local
728 if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel)) in mmux_get_parent()
729 clk_sel = 0; in mmux_get_parent()
731 clk_sel = 1; in mmux_get_parent()
732 mux = &mmux->mux[clk_sel]; in mmux_get_parent()
736 return mmux->sel2parent[clk_sel][cv1800_clk_regfield_get(reg, mux)]; in mmux_get_parent()
745 s8 clk_sel = mmux->parent2sel[index]; in mmux_set_parent() local
747 if (index == 0 || clk_sel == -1) { in mmux_set_parent()
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H A Dclk-cv18xx-ip.h53 struct cv1800_clk_regbit clk_sel; member
220 .clk_sel = CV1800_CLK_BIT(_clk_sel_reg, \
/linux/drivers/net/ethernet/atheros/atl1c/
H A Datl1c_hw.c274 void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel) in atl1c_start_phy_polling() argument
282 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | in atl1c_start_phy_polling()
306 u16 clk_sel = MDIO_CTRL_CLK_25_4; in atl1c_read_phy_core() local
315 clk_sel = MDIO_CTRL_CLK_25_128; in atl1c_read_phy_core()
320 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | in atl1c_read_phy_core()
326 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | in atl1c_read_phy_core()
339 atl1c_start_phy_polling(hw, clk_sel); in atl1c_read_phy_core()
355 u16 clk_sel = MDIO_CTRL_CLK_25_4; in atl1c_write_phy_core() local
363 clk_sel = MDIO_CTRL_CLK_25_128; in atl1c_write_phy_core()
369 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | in atl1c_write_phy_core()
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H A Datl1c_hw.h43 void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel);
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-gpio-defs.h53 uint64_t clk_sel:2; member
67 uint64_t clk_sel:2;
97 uint64_t clk_sel:2; member
111 uint64_t clk_sel:2;
360 uint64_t clk_sel:2; member
374 uint64_t clk_sel:2;
/linux/drivers/net/ethernet/atheros/alx/
H A Dhw.c64 u32 val, clk_sel; in alx_read_phy_core() local
70 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_read_phy_core()
81 clk_sel << ALX_MDIO_CLK_SEL_SHIFT; in alx_read_phy_core()
84 clk_sel << ALX_MDIO_CLK_SEL_SHIFT | in alx_read_phy_core()
101 u32 val, clk_sel; in alx_write_phy_core() local
104 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_write_phy_core()
114 clk_sel << ALX_MDIO_CLK_SEL_SHIFT | in alx_write_phy_core()
119 clk_sel << ALX_MDIO_CLK_SEL_SHIFT | in alx_write_phy_core()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c83 uint32_t clk_sel = 0; in dccg2_get_dccg_ref_freq() local
85 REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel); in dccg2_get_dccg_ref_freq()
/linux/drivers/tty/serial/
H A Dsamsung_tty.c1359 static void s3c24xx_serial_setsource(struct uart_port *port, u8 clk_sel) in s3c24xx_serial_setsource() argument
1368 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel) in s3c24xx_serial_setsource()
1372 ucon |= clk_sel << info->clksel_shift; in s3c24xx_serial_setsource()
1390 if (ourport->cfg->clk_sel && in s3c24xx_serial_getclk()
1391 !(ourport->cfg->clk_sel & (1 << cnt))) in s3c24xx_serial_getclk()
1482 u8 clk_sel = 0; in s3c24xx_serial_set_termios() local
1495 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel); in s3c24xx_serial_set_termios()
1506 s3c24xx_serial_setsource(port, clk_sel); in s3c24xx_serial_set_termios()
1785 u8 clk_sel, clk_num; in s3c24xx_serial_enable_baudclk() local
1787 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel; in s3c24xx_serial_enable_baudclk()
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H A Dxilinx_uartps.c507 * @div8: Value for clk_sel bit in mod (return value)
/linux/drivers/clk/mvebu/
H A Darmada-37xx-periph.c33 #define CLK_SEL 0x10 macro
67 u32 clk_sel; member
705 data->clk_sel = readl(data->reg + CLK_SEL); in armada_3700_periph_clock_suspend()
721 writel(data->clk_sel, data->reg + CLK_SEL); in armada_3700_periph_clock_resume()
/linux/drivers/gpio/
H A Dgpio-npcm-sgpio.c53 unsigned int *clk_sel; member
297 iowrite8(clk_cfg->clk_sel[i] | tmp, in npcm_sgpio_setup_clk()
588 .clk_sel = npcm750_CLK_SEL,
594 .clk_sel = npcm845_CLK_SEL,
/linux/drivers/clk/ralink/
H A Dclk-mt7621.c261 u32 clkcfg, clk_sel, curclk, ffiv, ffrac; in mt7621_cpu_recalc_rate() local
266 clk_sel = FIELD_GET(CPU_CLK_SEL_MASK, clkcfg); in mt7621_cpu_recalc_rate()
272 switch (clk_sel) { in mt7621_cpu_recalc_rate()
/linux/sound/soc/sti/
H A Duniperif_player.c957 if (player->clk_sel) { in uni_player_resume()
958 ret = regmap_field_write(player->clk_sel, 1); in uni_player_resume()
1031 player->clk_sel = regmap_field_alloc(regmap, regfield[0]); in uni_player_parse_dt_audio_glue()
1083 if (player->clk_sel) { in uni_player_init()
1084 ret = regmap_field_write(player->clk_sel, 1); in uni_player_init()
H A Duniperif.h1300 struct regmap_field *clk_sel; member
/linux/drivers/video/fbdev/
H A Dgrvga.c42 int clk_sel; member
112 par->clk_sel = i; in grvga_check_var()
180 __raw_writel((par->clk_sel << 6) | (func << 4) | 1, in grvga_set_par()
/linux/include/linux/
H A Dserial_s3c.h288 unsigned int clk_sel; member
/linux/drivers/iio/adc/
H A Dad4170-4.c2422 unsigned int clk_sel) in ad4170_sel_clk() argument
2425 st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, clk_sel); in ad4170_sel_clk()
2438 u32 clk_sel; in ad4170_clk_output_is_enabled() local
2440 clk_sel = FIELD_GET(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, st->clock_ctrl); in ad4170_clk_output_is_enabled()
2441 return clk_sel == AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT; in ad4170_clk_output_is_enabled()
/linux/drivers/media/dvb-frontends/
H A Dstv0900_core.c287 u32 m_div, clk_sel; in stv0900_set_mclk() local
298 clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6); in stv0900_set_mclk()
299 m_div = ((clk_sel * mclk) / intp->quartz) - 1; in stv0900_set_mclk()
H A Dstv090x.c4277 u32 reg, div, clk_sel; in stv090x_set_mclk() local
4280 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6); in stv090x_set_mclk()
4282 div = ((clk_sel * mclk) / config->xtal) - 1; in stv090x_set_mclk()
/linux/sound/soc/intel/atom/sst/
H A Dsst.h117 u64 clk_sel:3; member