Lines Matching full:clk_sel
684 if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel)) in mmux_recalc_rate()
707 if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel)) in mmux_set_rate()
723 s8 clk_sel; in mmux_get_parent() local
728 if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel)) in mmux_get_parent()
729 clk_sel = 0; in mmux_get_parent()
731 clk_sel = 1; in mmux_get_parent()
732 mux = &mmux->mux[clk_sel]; in mmux_get_parent()
736 return mmux->sel2parent[clk_sel][cv1800_clk_regfield_get(reg, mux)]; in mmux_get_parent()
745 s8 clk_sel = mmux->parent2sel[index]; in mmux_set_parent() local
747 if (index == 0 || clk_sel == -1) { in mmux_set_parent()
754 if (clk_sel) in mmux_set_parent()
755 cv1800_clk_clearbit(&mmux->common, &mmux->clk_sel); in mmux_set_parent()
757 cv1800_clk_setbit(&mmux->common, &mmux->clk_sel); in mmux_set_parent()
761 mux = &mmux->mux[clk_sel]; in mmux_set_parent()