| /linux/drivers/clk/mediatek/ |
| H A D | Makefile | 2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
5 obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg…
6 obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o
7 obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o
8 obj-$(CONFIG_COMMON_CLK_MT6735_VDECSYS) += clk-mt6735-vdecsys.o
9 obj-$(CONFIG_COMMON_CLK_MT6735_VENCSYS) += clk-mt6735-vencsys.o
10 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
11 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
12 obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o
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| /linux/drivers/clk/imx/ |
| H A D | Makefile | 3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
7 mxc-clk-objs += clk-composite-93.o
8 mxc-clk-objs += clk-fracn-gppll.o
9 mxc-clk-objs += clk-cpu.o
10 mxc-clk-objs += clk-divider-gate.o
11 mxc-clk-objs += clk-fixup-div.o
12 mxc-clk-objs += clk-fixup-mux.o
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| H A D | clk-vf610.c | 8 #include <linux/clk.h>
12 #include "clk.h"
113 static struct clk *clk[VF610_CLK_END]; variable
131 static struct clk * __init vf610_get_fixed_clock( in vf610_get_fixed_clock()
134 struct clk *clk = of_clk_get_by_name(ccm_node, name); in vf610_get_fixed_clock() local
137 if (IS_ERR(clk)) in vf610_get_fixed_clock()
138 clk = imx_obtain_fixed_clock(name, 0); in vf610_get_fixed_clock()
139 return clk; in vf610_get_fixed_clock()
184 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in vf610_clocks_init()
185 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); in vf610_clocks_init()
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| H A D | clk-imx27.c | 2 #include <linux/clk.h>
3 #include <linux/clk-provider.h>
13 #include "clk.h"
48 static struct clk *clk[IMX27_CLK_MAX]; variable
55 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx27_clocks_init()
56 clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); in _mx27_clocks_init()
57 clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); in _mx27_clocks_init()
58 clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); in _mx27_clocks_init()
59 clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); in _mx27_clocks_init()
60 clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); in _mx27_clocks_init()
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| H A D | clk-imx25.c | 9 #include <linux/clk.h>
18 #include "clk.h"
75 static struct clk *clk[clk_max]; variable
81 clk[dummy] = imx_clk_fixed("dummy", 0); in __mx25_clocks_init()
82 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); in __mx25_clocks_init()
83 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL)); in __mx25_clocks_init()
84 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); in __mx25_clocks_init()
85 …clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)… in __mx25_clocks_init()
86 clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2); in __mx25_clocks_init()
87 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
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| H A D | clk-imx35.c | 7 #include <linux/clk.h>
15 #include "clk.h"
82 static struct clk *clk[clk_max]; variable
98 pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel); in _mx35_clocks_init()
106 clk[ckih] = imx_clk_fixed("ckih", 24000000); in _mx35_clocks_init()
107 clk[ckil] = imx_clk_fixed("ckil", 32768); in _mx35_clocks_init()
108 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); in _mx35_clocks_init()
109 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
111 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); in _mx35_clocks_init()
114 clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm); in _mx35_clocks_init()
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| H A D | clk-imx31.c | 7 #include <linux/clk.h>
16 #include "clk.h"
50 static struct clk *clk[clk_max]; variable
55 clk[dummy] = imx_clk_fixed("dummy", 0); in _mx31_clocks_init()
56 clk[ckih] = imx_clk_fixed("ckih", fref); in _mx31_clocks_init()
57 clk[ckil] = imx_clk_fixed("ckil", 32768); in _mx31_clocks_init()
58 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); in _mx31_clocks_init()
59 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); in _mx31_clocks_init()
60 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL); in _mx31_clocks_init()
61 …clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_… in _mx31_clocks_init()
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| /linux/drivers/sh/clk/ |
| H A D | cpg.c | 11 #include <linux/clk.h>
19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static unsigned int sh_clk_read_status(struct clk *clk) in sh_clk_read_status() argument
31 void __iomem *mapped_status = (phys_addr_t)clk->status_reg - in sh_clk_read_status()
32 (phys_addr_t)clk->enable_reg + clk->mapped_reg; in sh_clk_read_status()
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| H A D | core.c | 29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
137 long clk_rate_table_round(struct clk *clk, in clk_rate_table_round() argument
143 .max = clk->nr_freqs - 1, in clk_rate_table_round()
149 if (clk->nr_freqs < 1) in clk_rate_table_round()
161 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, in clk_rate_div_range_round() argument
168 .arg = clk_get_parent(clk), in clk_rate_div_range_round()
181 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, in clk_rate_mult_range_round() argument
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| /linux/drivers/clk/spear/ |
| H A D | spear3xx_clock.c | 9 #include <linux/clk.h>
11 #include <linux/clk/spear.h>
16 #include "clk.h"
30 /* CORE CLK CFG register masks */
141 struct clk *clk; in spear300_clk_init() local
143 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, in spear300_clk_init()
145 clk_register_clkdev(clk, NULL, "60000000.clcd"); in spear300_clk_init()
147 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
149 clk_register_clkdev(clk, NULL, "94000000.flash"); in spear300_clk_init()
151 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
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| H A D | spear1310_clock.c | 12 #include <linux/clk/spear.h>
16 #include "clk.h"
262 /* For gmac phy input clk */
310 /* For parent clk = 49.152 MHz */
317 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
318 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
322 /* For parent clk = 49.152 MHz */
384 struct clk *clk, *clk1; in spear1310_clk_init() local
386 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear1310_clk_init()
387 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear1310_clk_init()
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| H A D | spear6xx_clock.c | 10 #include <linux/clk/spear.h>
13 #include "clk.h"
27 /* CORE CLK CFG register masks */
116 struct clk *clk, *clk1; in spear6xx_clk_init() local
118 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear6xx_clk_init()
119 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear6xx_clk_init()
121 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000); in spear6xx_clk_init()
122 clk_register_clkdev(clk, "osc_30m_clk", NULL); in spear6xx_clk_init()
124 /* clock derived from 32 KHz osc clk */ in spear6xx_clk_init()
125 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, in spear6xx_clk_init()
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| /linux/arch/mips/lantiq/ |
| H A D | clk.c | 12 #include <linux/clk.h>
23 #include "clk.h"
27 static struct clk cpu_clk_generic[4];
38 struct clk *clk_get_cpu(void) in clk_get_cpu()
43 struct clk *clk_get_fpi(void) in clk_get_fpi()
49 struct clk *clk_get_io(void) in clk_get_io()
55 struct clk *clk_get_ppe(void) in clk_get_ppe()
61 static inline int clk_good(struct clk *clk) in clk_good() argument
63 return clk && !IS_ERR(clk); in clk_good()
66 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mp-nominal.dtsi | 6 &clk {
7 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
8 <&clk IMX8MP_CLK_A53_CORE>,
9 <&clk IMX8MP_SYS_PLL3>,
10 <&clk IMX8MP_CLK_NOC>,
11 <&clk IMX8MP_CLK_NOC_IO>,
12 <&clk IMX8MP_CLK_GIC>;
13 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
14 <&clk IMX8MP_ARM_PLL_OUT>,
16 <&clk IMX8MP_SYS_PLL1_800M>,
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| /linux/arch/m68k/coldfire/ |
| H A D | clk.c | 5 * clk.c -- general ColdFire CPU kernel clk handling
16 #include <linux/clk.h>
31 void __clk_init_enabled(struct clk *clk) in __clk_init_enabled() argument
33 clk->enabled = 1; in __clk_init_enabled()
34 clk->clk_ops->enable(clk); in __clk_init_enabled()
37 void __clk_init_disabled(struct clk *clk) in __clk_init_disabled() argument
39 clk->enabled = 0; in __clk_init_disabled()
40 clk->clk_ops->disable(clk); in __clk_init_disabled()
43 static void __clk_enable0(struct clk *clk) in __clk_enable0() argument
45 __raw_writeb(clk->slot, MCFPM_PPMCR0); in __clk_enable0()
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| /linux/drivers/clk/ux500/ |
| H A D | u8500_of_clk.c | 11 #include <linux/clk-provider.h>
14 #include "clk.h"
18 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
19 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22 #define PRCC_SHOW(clk, base, bit) \ argument
23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
24 #define PRCC_PCLK_STORE(clk, base, bit) \ argument
25 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
26 #define PRCC_KCLK_STORE(clk, base, bit) \ argument
27 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
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| H A D | clk-sysctrl.c | 9 #include <linux/clk-provider.h>
16 #include "clk.h"
38 struct clk_sysctrl *clk = to_clk_sysctrl(hw); in clk_sysctrl_prepare() local
40 ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0], in clk_sysctrl_prepare()
41 clk->reg_bits[0]); in clk_sysctrl_prepare()
43 if (!ret && clk->enable_delay_us) in clk_sysctrl_prepare()
44 usleep_range(clk->enable_delay_us, clk->enable_delay_us + in clk_sysctrl_prepare()
45 (clk->enable_delay_us >> 2)); in clk_sysctrl_prepare()
52 struct clk_sysctrl *clk = to_clk_sysctrl(hw); in clk_sysctrl_unprepare() local
53 if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0])) in clk_sysctrl_unprepare()
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| H A D | clk-prcc.c | 9 #include <linux/clk-provider.h>
15 #include "clk.h"
37 struct clk_prcc *clk = to_clk_prcc(hw); in clk_prcc_pclk_enable() local
39 writel(clk->cg_sel, (clk->base + PRCC_PCKEN)); in clk_prcc_pclk_enable()
40 while (!(readl(clk->base + PRCC_PCKSR) & clk->cg_sel)) in clk_prcc_pclk_enable()
43 clk->is_enabled = 1; in clk_prcc_pclk_enable()
49 struct clk_prcc *clk = to_clk_prcc(hw); in clk_prcc_pclk_disable() local
51 writel(clk->cg_sel, (clk->base + PRCC_PCKDIS)); in clk_prcc_pclk_disable()
52 clk->is_enabled = 0; in clk_prcc_pclk_disable()
57 struct clk_prcc *clk = to_clk_prcc(hw); in clk_prcc_kclk_enable() local
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| /linux/drivers/clk/st/ |
| H A D | clk-flexgen.c | 3 * clk-flexgen.c
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
206 static struct clk *clk_register_flexgen(const char *name, in clk_register_flexgen()
211 struct clk *clk; in clk_register_flexgen() local
267 clk = clk_register(NULL, &fgxbar->hw); in clk_register_flexgen()
268 if (IS_ERR(clk)) in clk_register_flexgen()
272 __clk_get_name(clk), in clk_register_flexgen()
273 __clk_get_name(clk_get_parent(clk)), in clk_register_flexgen()
274 (unsigned int)clk_get_rate(clk)); in clk_register_flexgen()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | base.c | 41 nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, in nvkm_clk_adjust() argument
44 struct nvkm_bios *bios = clk->subdev.device->bios; in nvkm_clk_adjust()
79 nvkm_cstate_valid(struct nvkm_clk *clk, struct nvkm_cstate *cstate, in nvkm_cstate_valid() argument
82 const struct nvkm_domain *domain = clk->domains; in nvkm_cstate_valid()
83 struct nvkm_volt *volt = clk->subdev.device->volt; in nvkm_cstate_valid()
89 switch (clk->boost_mode) { in nvkm_cstate_valid()
91 if (clk->base_khz && freq > clk->base_khz) in nvkm_cstate_valid()
95 if (clk->boost_khz && freq > clk->boost_khz) in nvkm_cstate_valid()
112 nvkm_cstate_find_best(struct nvkm_clk *clk, struct nvkm_pstate *pstate, in nvkm_cstate_find_best() argument
115 struct nvkm_device *device = clk->subdev.device; in nvkm_cstate_find_best()
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| /linux/drivers/clk/rockchip/ |
| H A D | Makefile | 6 obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
8 clk-rockchip-y += clk.o
9 clk-rockchip-y += clk-pll.o
10 clk-rockchip-y += clk-cpu.o
11 clk-rockchip-y += clk-gate-grf.o
12 clk-rockchip-y += clk-half-divider.o
13 clk-rockchip-y += clk-inverter.o
14 clk-rockchip-y += clk-mmc-phase.o
15 clk-rockchip-y += clk-muxgrf.o
16 clk-rockchip-y += clk-ddr.o
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| /linux/kernel/time/ |
| H A D | posix-clock.c | 23 struct posix_clock *clk = pccontext->clk; in get_posix_clock() local
25 down_read(&clk->rwsem); in get_posix_clock()
27 if (!clk->zombie) in get_posix_clock()
28 return clk; in get_posix_clock()
30 up_read(&clk->rwsem); in get_posix_clock()
35 static void put_posix_clock(struct posix_clock *clk) in put_posix_clock() argument
37 up_read(&clk->rwsem); in put_posix_clock()
44 struct posix_clock *clk = get_posix_clock(fp); in posix_clock_read() local
47 if (!clk) in posix_clock_read()
50 if (clk->ops.read) in posix_clock_read()
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| /linux/drivers/clk/ |
| H A D | clk_kunit_helpers.c | 3 * KUnit helpers for clk providers and consumers
5 #include <linux/clk.h>
6 #include <linux/clk-provider.h>
11 #include <kunit/clk.h>
15 clk_disable_unprepare, struct clk *);
19 * @clk: clk to prepare and enable
23 int clk_prepare_enable_kunit(struct kunit *test, struct clk *clk) in clk_prepare_enable_kunit() argument
27 ret = clk_prepare_enable(clk); in clk_prepare_enable_kunit()
32 clk); in clk_prepare_enable_kunit()
36 KUNIT_DEFINE_ACTION_WRAPPER(clk_put_wrapper, clk_put, struct clk *);
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| /linux/rust/helpers/ |
| H A D | clk.c | 3 #include <linux/clk.h>
10 struct clk *rust_helper_clk_get(struct device *dev, const char *id) in rust_helper_clk_get()
15 void rust_helper_clk_put(struct clk *clk) in rust_helper_clk_put() argument
17 clk_put(clk); in rust_helper_clk_put()
20 int rust_helper_clk_enable(struct clk *clk) in rust_helper_clk_enable() argument
22 return clk_enable(clk); in rust_helper_clk_enable()
25 void rust_helper_clk_disable(struct clk *clk) in rust_helper_clk_disable() argument
27 clk_disable(clk); in rust_helper_clk_disable()
30 unsigned long rust_helper_clk_get_rate(struct clk *clk) in rust_helper_clk_get_rate() argument
32 return clk_get_rate(clk); in rust_helper_clk_get_rate()
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| /linux/include/linux/ |
| H A D | sh_clk.h | 10 #include <linux/clk.h>
13 struct clk;
24 void (*init)(struct clk *clk);
26 int (*enable)(struct clk *clk);
27 void (*disable)(struct clk *clk);
28 unsigned long (*recalc)(struct clk *clk);
29 int (*set_rate)(struct clk *clk, unsigned long rate);
30 int (*set_parent)(struct clk *clk, struct clk *parent);
31 long (*round_rate)(struct clk *clk, unsigned long rate);
38 struct clk { struct
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