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/freebsd/sys/contrib/device-tree/Bindings/iio/frequency/
H A Dadf4350.txt4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
21 - adi,reference-div2-enable: Enables reference divider.
[all …]
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
[all …]
/freebsd/sys/dev/clk/allwinner/
H A Dccu_a31.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_div.h>
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_mux.h>
45 #include <dev/clk/allwinner/aw_ccung.h>
47 #include <dt-bindings/clock/sun6i-a31-ccu.h>
48 #include <dt-bindings/reset/sun6i-a31-ccu.h>
50 /* Non-exported clocks */
148 CCU_GATE(CLK_AHB1_MIPIDSI, "ahb1-mipidsi", "ahb1", 0x60, 1)
[all …]
H A Dccu_a64.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_div.h>
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_mux.h>
45 #include <dev/clk/allwinner/aw_ccung.h>
47 #include <dt-bindings/clock/sun50i-a64-ccu.h>
48 #include <dt-bindings/reset/sun50i-a64-ccu.h>
50 /* Non-exported clocks */
141 CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1)
[all …]
H A Dccu_h3.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
45 #include <dev/clk/clk_div.h>
46 #include <dev/clk/clk_fixed.h>
47 #include <dev/clk/clk_mux.h>
53 #include <dev/clk/allwinner/aw_ccung.h>
55 #include <dt-bindings/clock/sun8i-h3-ccu.h>
56 #include <dt-bindings/reset/sun8i-h3-ccu.h>
58 /* Non-exported resets */
61 /* Non-exported clocks */
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
36 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
52 * divided by the divider controlled by ACLK_CLK_DIVISOR in
56 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */
60 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */
62 /** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */
64 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */
81 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */
83 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */
[all …]
/freebsd/sys/dev/usb/serial/
H A Dumcs.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
50 #define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong
52 #define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong
67 #define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */
69 #define MCS7840_DEV_REG_PLL_DIV_N 0x10 /* Loop divider for PLL, R/W */
78 /* DCRx_2-DCRx_4 Registers goes here (see below, they are documented) */
109 #define MCS7840_DEV_REG_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port
112 #define MCS7840_DEV_REG_BO_FIFO_STAT1 0x33 /* Bulk-out FIFO Stat for Port
115 #define MCS7840_DEV_REG_BI_FIFO_STAT2 0x34 /* Bulk-In FIFO Stat for Port
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h>
18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
27 stdout-path = &uart2;
36 compatible = "fixed-clock";
[all …]
H A Dimx8mm-venice-gw7901.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
30 stdout-path = &uart2;
38 gpio-keys {
39 compatible = "gpio-keys";
[all …]
H A Dimx8mm-venice-gw7903.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
25 stdout-path = &uart2;
33 gpio-keys {
34 compatible = "gpio-keys";
[all …]
H A Dimx8mm-venice-gw7904.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm";
20 stdout-path = &uart2;
28 gpio-keys {
29 compatible = "gpio-keys";
[all …]
H A Dimx8mn-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
24 stdout-path = &uart2;
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
[all …]
H A Dimx8mp-venice-gw74xx.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include <dt-bindings/net/ti-dp83867.h>
18 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
31 stdout-path = &uart2;
40 pinctrl-names = "default";
[all …]
/freebsd/sys/arm/freescale/vybrid/
H A Dvf_ccm.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com>
61 #define CCM_CSCDR1 0x14 /* Serial Clock Divider Register 1 */
62 #define CCM_CSCDR2 0x18 /* Serial Clock Divider Register 2 */
63 #define CCM_CSCDR3 0x1C /* Serial Clock Divider Register 3 */
153 struct clk { struct
165 static struct clk ipg_clk = { argument
178 PLL4 clock divider (before switching the clocks should be gated)
189 static struct clk pll4_clk = {
[all …]
/freebsd/sys/dev/clk/xilinx/
H A Dzynqmp_clk_pll.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
34 #include <dev/clk/clk.h>
36 #include <dev/clk/xilinx/zynqmp_clk_pll.h>
53 zynqmp_clk_pll_init(struct clknode *clk, device_t dev) in zynqmp_clk_pll_init() argument
56 clknode_init_parent_idx(clk, 0); in zynqmp_clk_pll_init()
61 zynqmp_clk_pll_recalc(struct clknode *clk, uint64_t *freq) in zynqmp_clk_pll_recalc() argument
65 uint32_t div, mode, frac; in zynqmp_clk_pll_recalc() local
68 sc = clknode_get_softc(clk); in zynqmp_clk_pll_recalc()
69 rv = ZYNQMP_FIRMWARE_CLOCK_GETDIVIDER(sc->firmware, sc->id, &div); in zynqmp_clk_pll_recalc()
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
37 #include <dev/clk/clk_div.h>
38 #include <dev/clk/clk_fixed.h>
39 #include <dev/clk/clk_gate.h>
40 #include <dev/clk/clk_mux.h>
42 #include <dt-bindings/clock/tegra210-car.h>
71 #define PLL_FLAG_PDIV_POWER2 0x01 /* P Divider is 2^n */
113 /* Post divider <-> register value mapping. */
115 uint32_t divider; /* real divider */ member
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsilabs,si5341.txt6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
14 in turn can be directed to any of the 10 (or 4) outputs through a divider.
20 The driver can be used in "as is" mode, reading the current settings from the
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
36 "silabs,si5342" - Si5342 A/B/C/D
[all …]
/freebsd/sys/arm64/rockchip/
H A Drk3568_combphy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
43 #include <dev/clk/clk.h>
49 #include <contrib/device-tree/include/dt-bindings/phy/phy.h>
57 {"rockchip,rk3568-naneng-combphy", 1},
72 int mode; member
174 switch (sc->mode) { in rk3568_combphy_enable()
179 bus_write_4(sc->mem, PHYREG7, in rk3568_combphy_enable()
183 bus_write_4(sc->mem, PHYREG15, in rk3568_combphy_enable()
184 bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN); in rk3568_combphy_enable()
[all …]
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_spi.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
58 {"broadcom,bcm2835-spi", 1},
59 {"brcm,bcm2835-spi", 1},
81 reg--; in bcm_spi_printr()
84 device_printf(dev, "CLK=%uMhz/%d=%luhz\n", in bcm_spi_printr()
105 mtx_assert(&sc->sc_mtx, MA_OWNED); in bcm_spi_modifyreg()
116 uint32_t clk; in bcm_spi_clock_proc() local
122 clk = BCM_SPI_READ(sc, SPI_CLK); in bcm_spi_clock_proc()
124 clk &= 0xffff; in bcm_spi_clock_proc()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/st/
H A Dst,flexgen.txt5 - a clock cross bar (represented by a mux element)
6 - a pre and final dividers (represented by a divider and gate elements)
13 -------------------------------------------------------------------
15 | --------------------------------------------- |
16 | | ------- -------- -------- | |
18 ---|-----------------|-->| | | | | | | |
20 | | ------- | | | |Pre | |Final | | |
22 | |->| | | | | | x32 | | x32 | | |
23 | | | odf_0|----|-->| | | | | | | |
28 | | ------- | | | | | | | | |
[all …]
/freebsd/sys/contrib/device-tree/src/arc/
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
[all …]
/freebsd/sys/dev/qcom_clk/
H A Dqcom_clk_rcg2.c1 /*-
34 #include <dev/clk/clk.h>
35 #include <dev/clk/clk_div.h>
36 #include <dev/clk/clk_fixed.h>
37 #include <dev/clk/clk_mux.h>
52 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_CFG_REG)
54 ((sc)->cmd_rcgr + QCOM_CLK_RCG2_CMD_REG)
56 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_M_REG)
58 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_N_REG)
60 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_D_REG)
[all …]
/freebsd/sys/dev/pwm/controller/rockchip/
H A Drk_pwm.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk.h>
75 /* Low power mode: disable prescaler when inactive */
97 { "rockchip,rk3288-pwm", 1 },
98 { "rockchip,rk3399-pwm", 1 },
104 { -1, 0 }
110 clk_t clk; member
123 #define RK_PWM_READ(sc, reg) bus_read_4((sc)->res, (reg))
124 #define RK_PWM_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
[all …]
/freebsd/sys/dev/spibus/controller/allwinner/
H A Daw_spi.c1 /*-
43 #include <dev/clk/clk.h>
56 #define AW_SPI_TCR_SDDM (1 << 14) /* Sending Delay Data Mode */
57 #define AW_SPI_TCR_SDM (1 << 13) /* Master Sample Data Mode */
60 #define AW_SPI_TCR_RPSM (1 << 10) /* Rapid Mode Select */
109 #define AW_SPI_CCR_DRS (1 << 12) /* Clock divider select */
126 { "allwinner,sun8i-h3-spi", 1 },
133 { -1, 0 }
156 #define AW_SPI_LOCK(sc) mtx_lock(&(sc)->mtx)
157 #define AW_SPI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
[all …]
/freebsd/sys/dev/spibus/controller/rockchip/
H A Drk_spi.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
45 #include <dev/clk/clk.h>
88 { "rockchip,rk3328-spi", 1 },
89 { "rockchip,rk3399-spi", 1 },
90 { "rockchip,rk3568-spi", 1 },
97 { -1, 0 }
121 #define RK_SPI_LOCK(sc) mtx_lock(&(sc)->mtx)
122 #define RK_SPI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
123 #define RK_SPI_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg))
[all …]

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