| /linux/drivers/irqchip/ |
| H A D | irq-mbigen.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/interrupt.h>
19 /* Interrupt numbers per mbigen node supported */
22 /* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
45 * of interrupt
50 * offset of interrupt type register
51 * This register is used to configure interrupt
57 * struct mbigen_device - holds the information of mbigen device.
60 * @base: mapped address of this mbigen chip.
64 void __iomem *base; member
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| H A D | irq-gic-v2m.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
5 * implement ARM Generic Interrupt Controller: GICv2m.
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/irqchip/arm-gic-common.h>
29 #include <linux/irqchip/irq-msi-lib.h>
52 /* APM X-Gene with GICv2m MSI_IIDR register value */
69 void __iomem *base; /* GICv2m virt address */ member
79 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) in gicv2m_get_msi_addr()
80 return v2m->res.start | ((hwirq - 32) << 3); in gicv2m_get_msi_addr()
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| H A D | irq-bcm7120-l2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom BCM7120 style Level 2 interrupt controller driver
19 #include <linux/interrupt.h>
28 /* Register offset in the L2 interrupt controller */
58 struct bcm7120_l2_intc_data *b = data->b; in bcm7120_l2_intc_irq_handle()
64 for (idx = 0; idx < b->n_words; idx++) { in bcm7120_l2_intc_irq_handle()
65 int base = idx * IRQS_PER_WORD; in bcm7120_l2_intc_irq_handle() local
70 gc = irq_get_domain_generic_chip(b->domain, base); in bcm7120_l2_intc_irq_handle()
71 scoped_guard (raw_spinlock, &gc->lock) { in bcm7120_l2_intc_irq_handle()
72 pending = irq_reg_readl(gc, b->stat_offset[idx]) & gc->mask_cache & in bcm7120_l2_intc_irq_handle()
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| /linux/drivers/hwmon/ |
| H A D | npcm750-pwm-fan.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2014-2018 Nuvoton Technology corporation.
7 #include <linux/hwmon-sysfs.h>
8 #include <linux/interrupt.h>
19 #define NPCM7XX_PWM_REG_BASE(base, n) ((base) + ((n) * 0x1000L)) argument
21 #define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00) argument
22 #define NPCM7XX_PWM_REG_CSR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x04) argument
23 #define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08) argument
24 #define NPCM7XX_PWM_REG_CNRx(base, n, ch) \ argument
25 (NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch)))
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| /linux/Documentation/devicetree/bindings/display/ |
| H A D | st,stih4xx.txt | 3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
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| /linux/arch/mips/pci/ |
| H A D | pci-rt3883.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
15 #include <linux/interrupt.h>
22 #include <asm/mach-ralink/rt3883.h>
23 #include <asm/mach-ralink/ralink_regs.h>
60 void __iomem *base; member
77 hose = (struct pci_controller *) bus->sysdata; in pci_bus_to_rt3883_controller()
84 return ioread32(rpc->base + reg); in rt3883_pci_r32()
90 iowrite32(val, rpc->base + reg); in rt3883_pci_w32()
143 generic_handle_domain_irq(rpc->irq_domain, bit); in rt3883_pci_irq_handler()
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| /linux/drivers/pci/controller/ |
| H A D | pci-mvebu.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
27 #include "../pci-bridge-emul.h"
40 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
94 phys_addr_t base; member
102 void __iomem *base; member
130 writel(val, port->base + reg); in mvebu_writel()
135 return readl(port->base + reg); in mvebu_readl()
140 return port->io_target != -1 && port->io_attr != -1; in mvebu_has_ioport()
199 * BAR[0] -> internal registers (needed for MSI)
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| /linux/drivers/pinctrl/intel/ |
| H A D | pinctrl-intel-platform.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021-2023, Intel Corporation
18 #include "pinctrl-intel.h"
25 static int intel_platform_pinctrl_prepare_pins(struct device *dev, size_t base, in intel_platform_pinctrl_prepare_pins() argument
37 descs = devm_krealloc_array(dev, pins->pins, base + size, sizeof(*descs), GFP_KERNEL); in intel_platform_pinctrl_prepare_pins()
39 return -ENOMEM; in intel_platform_pinctrl_prepare_pins()
42 unsigned int pin_number = base + i; in intel_platform_pinctrl_prepare_pins()
47 strreplace(pin_name, '-', '_'); in intel_platform_pinctrl_prepare_pins()
50 desc->number = pin_number; in intel_platform_pinctrl_prepare_pins()
51 desc->name = pin_name; in intel_platform_pinctrl_prepare_pins()
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| /linux/Documentation/devicetree/bindings/soc/dove/ |
| H A D | pmu.txt | 4 - compatible: value should be "marvell,dove-pmu".
5 May also include "simple-bus" if there are child devices, in which
7 - reg: two base addresses and sizes of the PM controller and PMU.
8 - interrupts: single interrupt number for the PMU interrupt
9 - interrupt-controller: must be specified as the PMU itself is an
10 interrupt controller.
11 - #interrupt-cells: must be 1.
12 - #reset-cells: must be 1.
13 - domains: sub-node containing domain descriptions
16 - ranges: defines the address mapping for child devices, as per the
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| /linux/drivers/pinctrl/starfive/ |
| H A D | pinctrl-starfive-jh7100.c | 1 // SPDX-License-Identifier: GPL-2.0
26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
29 #include "../pinctrl-utils.h"
33 #define DRIVER_NAME "pinctrl-starfive"
37 * https://github.com/starfive-tech/JH7100_Docs
48 * The following 32-bit registers come in pairs, but only the offset of the
49 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
50 * the second GPIO 32-63.
54 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
55 * interrupt is level-triggered.
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| /linux/include/linux/gpio/ |
| H A D | driver.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pinctrl/pinconf-generic.h>
49 * struct gpio_irq_chip - GPIO interrupt controller
62 * Interrupt translation domain; responsible for mapping between GPIO
79 * If non-NULL, will be set as the parent of this GPIO interrupt
80 * controller's IRQ domain to establish a hierarchical interrupt
82 * interrupt support.
89 * This callback translates a child hardware IRQ offset to a parent
90 * hardware IRQ offset on a hierarchical interrupt chip. The child
91 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
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| /linux/Documentation/devicetree/bindings/soc/ti/ |
| H A D | keystone-navigator-qmss.txt | 5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
9 management of the packet queues. Packets are queued/de-queued by writing or
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
32 -- managed-queues : the actual queues managed by each queue manager
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| /linux/drivers/mfd/ |
| H A D | mfd-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mfd/mfd-core.c
46 if (!acpi_match_device_ids(adev, wd->ids)) { in match_device_ids()
47 wd->adev = adev; in match_device_ids()
57 const struct mfd_cell_acpi_match *match = cell->acpi_match; in mfd_acpi_add_device()
61 parent = ACPI_COMPANION(pdev->dev.parent); in mfd_acpi_add_device()
66 * MFD child device gets its ACPI handle either from the ACPI device in mfd_acpi_add_device()
75 if (match->pnpid) { in mfd_acpi_add_device()
82 strscpy(ids[0].id, match->pnpid, sizeof(ids[0].id)); in mfd_acpi_add_device()
86 adev = acpi_find_child_device(parent, match->adr, false); in mfd_acpi_add_device()
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | octeon-usb.txt | 7 - compatible: must be "cavium,octeon-5750-usbn"
9 - reg: specifies the physical base address of the USBN block and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
21 - clock-frequency: speed of the USB reference clock. Allowed values are
24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
31 2) Child node
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| /linux/drivers/usb/cdns3/ |
| H A D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 NXP
6 * Copyright (C) 2018-2019 Cadence.
20 * struct cdns_role_driver - host/gadget role driver
51 * struct cdns - Representation of Cadence USB3 DRD controller.
53 * @xhci_regs: pointer to base of xhci registers
55 * @dev_regs: pointer to base of dev registers
57 * @otg_v0_regs: pointer to base of v0 otg registers
58 * @otg_v1_regs: pointer to base of v1 otg registers
59 * @otg_cdnsp_regs: pointer to base of CDNSP otg registers
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| /linux/drivers/gpio/ |
| H A D | gpio-ixp4xx.c | 1 // SPDX-License-Identifier: GPL-2.0
6 // based on previous work and know-how from:
29 * The hardware uses 3 bits to indicate interrupt "style".
55 * struct ixp4xx_gpio - IXP4 GPIO state container
58 * @base: remapped I/O-memory base
59 * @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
65 void __iomem *base; member
74 __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); in ixp4xx_gpio_irq_ack()
82 gpiochip_disable_irq(gc, d->hwirq); in ixp4xx_gpio_mask_irq()
90 /* ACK when unmasking if not edge-triggered */ in ixp4xx_gpio_irq_unmask()
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | ralink,rt3883-pci.txt | 7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
26 2) Child nodes
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
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| /linux/drivers/pinctrl/ |
| H A D | pinctrl-st.c | 1 // SPDX-License-Identifier: GPL-2.0-only
100 * (direction, retime-type, retime-clk, retime-delay)
102 * +----------------+
103 *[31:28]| reserved-3 |
104 * +----------------+-------------
106 * +----------------+ v
108 * +----------------+ ^
110 * +----------------+-------------
111 *[24] | reserved-2 |
112 * +----------------+-------------
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | brcm,nsp-gpio.txt | 4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
9 GPIO base, IO control registers
11 - #gpio-cells:
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
24 Interrupt ID
26 - interrupt-controller:
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| H A D | brcm,iproc-gpio.txt | 5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
23 - reg:
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| /linux/drivers/edac/ |
| H A D | altera_edac.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5 * Copyright 2011-2012 Calxeda, Inc.
12 #include <linux/firmware/intel/stratix10-smc.h>
14 #include <linux/interrupt.h>
17 #include <linux/mfd/altera-sysmgr.h>
84 struct altr_sdram_mc_data *drvdata = mci->pvt_info; in altr_sdram_mc_err_handler()
85 const struct altr_sdram_prv_data *priv = drvdata->data; in altr_sdram_mc_err_handler()
88 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); in altr_sdram_mc_err_handler()
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| /linux/drivers/i2c/busses/ |
| H A D | i2c-qcom-cci.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
3 // Copyright (c) 2017-2022 Linaro Limited.
9 #include <linux/interrupt.h>
98 u16 tsu_sto; /* set-up time for STOP condition */
99 u16 tsu_sta; /* set-up time for a repeated START condition */
128 void __iomem *base; member
142 val = readl(cci->base + CCI_IRQ_STATUS_0); in cci_isr()
143 writel(val, cci->base + CCI_IRQ_CLEAR_0); in cci_isr()
144 writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD); in cci_isr()
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| /linux/drivers/iio/adc/ |
| H A D | stm32-adc-core.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
8 * Inspired from: fsl-imx25-tsadc
14 #include <linux/interrupt.h>
30 #include "stm32-adc-core.h"
46 * struct stm32_adc_common_regs - stm32 common registers
51 * @ier: interrupt enable register offset for each adc
52 * @eocie_msk: end of conversion interrupt enable mask in @ier
66 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data
72 * @num_irqs: number of interrupt lines
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| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | socionext,uniphier-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
27 interrupt-controller: true
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| /linux/drivers/leds/ |
| H A D | leds-sun50i-a100.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021-2023 Samuel Holland <samuel@sholland.org>
5 * Partly based on drivers/leds/leds-turris-omnia.c, which is:
12 #include <linux/dma-mapping.h>
14 #include <linux/interrupt.h>
16 #include <linux/led-class-multicolor.h>
75 void __iomem *base; member
103 desc = dmaengine_prep_slave_single(priv->dma_chan, priv->dma_handle, in sun50i_a100_ledc_dma_xfer()
106 return -ENOMEM; in sun50i_a100_ledc_dma_xfer()
110 return -EIO; in sun50i_a100_ledc_dma_xfer()
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