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/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z13/
H A Dextended.json5 "BriefDescription": "L1D Read-only Exclusive Writes",
6 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
12 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
18 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
23 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
24 …on": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a …
29 "BriefDescription": "DTLB1 Two-Gigabyte Page Writes",
30 …on": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a …
36 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
42 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
[all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z14/
H A Dextended.json5 "BriefDescription": "L1D Read-only Exclusive Writes",
6 …Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
12 … written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache"
18 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
23 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
24 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
29 "BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
30 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"
36 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
42 …n into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache"
[all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a65/
H A Dcache.json111 …tion": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetche…
114 …tion": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetche…
117 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
120 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
123 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
126 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
141 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
144 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
147 …Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-st…
150 …Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-st…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A Dextended.json6 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
12 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
18 … directory write to the Level-1 Data cache directory where the returned cache line was sourced fro…
24 …ectory write to the Level-1 Instruction cache directory where the returned cache line was sourced …
30 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
36 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
42 … write to the Level-1 Data cache where the installed cache line was sourced from memory that is at…
48 …to the Level-1 Instruction cache where the installed cache line was sourced from memory that is at…
53 "BriefDescription": "L1D Read-only Exclusive Writes",
54 …Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updat…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z196/
H A Dextended.json6 …on": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced…
12 …on": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced…
18 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
30 "PublicDescription": "Incremented by one for every store sent to Level-2 cache"
35 "BriefDescription": "L1D Off-Book L3 Sourced Writes",
36 … "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced fro…
41 "BriefDescription": "L1D On-Book L4 Sourced Writes",
42 …: "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced fr…
47 "BriefDescription": "L1I On-Book L4 Sourced Writes",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a55/
H A Dcache.json105 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
108 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
111 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
114 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
117 …on": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetch…
120 …on": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetch…
123 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
126 …Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each …
132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z10/
H A Dextended.json6 …: "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced fr…
12 … "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced fr…
18 …Level-1 I-Cache directory where the installed cache line was sourced from the Level-3 cache that i…
24 … Level-1 D-Cache directory where the installtion cache line was source from the Level-3 cache that…
30 …Level-1 I-Cache directory where the installed cache line was sourced from a Level-3 cache that is …
36 …Level-1 D-Cache directory where the installed cache line was sourced from a Level-3 cache that is …
42 …te to the Level-1 D-Cache directory where the installed cache line was sourced from memory that is…
48 …ite to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached…
53 "BriefDescription": "L1D Read-only Exclusive Writes",
54 …Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updat…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/
H A Drecommended.json3 "PublicDescription": "Attributable Level 1 data cache access, read",
6 "BriefDescription": "L1D cache access, read"
9 "PublicDescription": "Attributable Level 1 data cache access, write",
12 "BriefDescription": "L1D cache access, write"
15 "PublicDescription": "Attributable Level 1 data cache refill, read",
18 "BriefDescription": "L1D cache refill, read"
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
24 "BriefDescription": "L1D cache refill, write"
27 "PublicDescription": "Attributable Level 1 data cache refill, inner",
30 "BriefDescription": "L1D cache refill, inner"
[all …]
H A Darmv8-recommended.json3 "PublicDescription": "Attributable Level 1 data cache access, read",
6 "BriefDescription": "L1D cache access, read"
9 "PublicDescription": "Attributable Level 1 data cache access, write",
12 "BriefDescription": "L1D cache access, write"
15 "PublicDescription": "Attributable Level 1 data cache refill, read",
18 "BriefDescription": "L1D cache refill, read"
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
24 "BriefDescription": "L1D cache refill, write"
27 "PublicDescription": "Attributable Level 1 data cache refill, inner",
30 "BriefDescription": "L1D cache refill, inner"
[all …]
H A Dcommon-and-microarch.json9 "PublicDescription": "Level 1 instruction cache refill",
12 "BriefDescription": "Level 1 instruction cache refill"
15 "PublicDescription": "Attributable Level 1 instruction TLB refill",
18 "BriefDescription": "Attributable Level 1 instruction TLB refill"
21 "PublicDescription": "Level 1 data cache refill",
24 "BriefDescription": "Level 1 data cache refill"
27 "PublicDescription": "Level 1 data cache access",
30 "BriefDescription": "Level 1 data cache access"
33 "PublicDescription": "Attributable Level 1 data TLB refill",
36 "BriefDescription": "Attributable Level 1 data TLB refill"
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dcpufreq-qcom-hw.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sdm670-cpufreq-hw
[all …]
H A Dcpufreq-qcom-hw.txt8 - compatible
11 Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
13 - clocks
18 - clock-names
23 - reg
25 Value type: <prop-encoded-array>
28 - reg-names
32 "freq-domain0", "freq-domain1".
34 - #freq-domain-cells:
38 * Property qcom,freq-domain
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
63 enable-method = "spin-table";
64 cpu-release-addr = <0 0>; /* To be filled by loader */
65 next-level-cache = <&l2_cache_0>;
66 i-cache-size = <0x20000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cache/
H A Dsocionext,uniphier-system-cache.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/socionext/
H A Dsocionext,uniphier-system-cache.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amd/
H A Delba-16core.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2023 Advanced Micro Devices, Inc.
8 #address-cells = <1>;
9 #size-cells = <0>;
11 cpu-map {
44 compatible = "arm,cortex-a72";
46 next-level-cache = <&l2_0>;
47 enable-method = "psci";
52 compatible = "arm,cortex-a72";
54 next-level-cache = <&l2_0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amazon/
H A Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp4080si-pre.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
91 #address-cells = <1>;
92 #size-cells = <0>;
98 next-level-cache = <&L2_0>;
99 fsl,portid-mapping = <0x80000000>;
100 L2_0: l2-cache {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am654.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dsifive-l2-cache.txt1 SiFive L2 Cache Controller
2 --------------------------
3 The SiFive Level 2 Cache Controller is used to provide access to fast copies
4 of memory for masters in a Core Complex. The Level 2 Cache Controller also
5 acts as directory-based coherency manager.
9 --------------------
10 - compatible: Should be "sifive,fu540-c000-ccache" and "cache"
12 - cache-block-size: Specifies the block size in bytes of the cache.
15 - cache-level: Should be set to 2 for a level 2 cache
17 - cache-sets: Specifies the number of associativity sets of the cache.
[all …]
H A Dsifive-l2-cache.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive L2 Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 The SiFive Level 2 Cache Controller is used to provide access to fast copies
16 of memory for masters in a Core Complex. The Level 2 Cache Controller also
17 acts as directory-based coherency manager.
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/
H A Dbcm2712.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #address-cells = <2>;
8 #size-cells = <2>;
10 interrupt-parent = <&gicv2>;
14 clk_osc: clk-osc {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-output-names = "osc";
18 clock-frequency = <54000000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls2088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a72-pmu";
25 compatible = "arm,cortex-a72";
28 cpu-idle-states = <&CPU_PW20>;
29 next-level-cache = <&cluster0_l2>;
30 #cooling-cells = <2>;
35 compatible = "arm,cortex-a72";
[all …]
/freebsd/crypto/krb5/src/man/
H A Dkdestroy.man4 .nr rst2man-indent-level 0
7 \\$1 \\n[an-margin]
8 level \\n[rst2man-indent-level]
9 level margin: \\n[rst2man-indent\\n[rst2man-indent-level]]
10 -
11 \\n[rst2man-indent0]
12 \\n[rst2man-indent1]
13 \\n[rst2man-indent2]
18 . nr rst2man-indent\\n[rst2man-indent-level] \\n[an-margin]
19 . nr rst2man-indent-level +1
[all …]

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