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Searched +full:bcm2835 +full:- +full:pixelvalve2 (Results 1 – 4 of 4) sorted by relevance

/linux/Documentation/devicetree/bindings/display/
H A Dbrcm,bcm2835-pixelvalve0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/brcm,bcm2835-pixelvalve0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eric Anholt <eric@anholt.net>
15 - brcm,bcm2835-pixelvalve0
16 - brcm,bcm2835-pixelvalve1
17 - brcm,bcm2835-pixelvalve2
18 - brcm,bcm2711-pixelvalve0
19 - brcm,bcm2711-pixelvalve1
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2835-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * bcm2835, bcm2836 and bcm2837 implementations.
8 interrupt-parent = <&intc>;
11 dma: dma-controller@7e007000 {
12 compatible = "brcm,bcm2835-dma";
25 /* dma channel 11-14 share one irq */
32 interrupt-names = "dma0",
47 "dma-shared-all";
48 #dma-cells = <1>;
49 brcm,dma-channel-mask = <0x7f35>;
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H A Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
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/linux/drivers/gpu/drm/vc4/
H A Dvc4_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
27 * output-specific clock. Since the encoders also directly consume
57 writel(val, vc4_crtc->regs + (offset)); \
63 readl(vc4_crtc->regs + (offset)); \
85 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_cob_allocation()
87 /* Top/base are supposed to be 4-pixel aligned, but the in vc4_crtc_get_cob_allocation()
94 return top - base + 4; in vc4_crtc_get_cob_allocation()
103 struct drm_device *dev = crtc->dev; in vc4_crtc_get_scanout_position()
105 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_scanout_position()
107 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); in vc4_crtc_get_scanout_position()
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