Lines Matching +full:bcm2835 +full:- +full:pixelvalve2
1 // SPDX-License-Identifier: GPL-2.0-only
27 * output-specific clock. Since the encoders also directly consume
57 writel(val, vc4_crtc->regs + (offset)); \
63 readl(vc4_crtc->regs + (offset)); \
85 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_cob_allocation()
87 /* Top/base are supposed to be 4-pixel aligned, but the in vc4_crtc_get_cob_allocation()
94 return top - base + 4; in vc4_crtc_get_cob_allocation()
103 struct drm_device *dev = crtc->dev; in vc4_crtc_get_scanout_position()
105 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_scanout_position()
107 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); in vc4_crtc_get_scanout_position()
108 unsigned int channel = vc4_crtc_state->assigned_channel; in vc4_crtc_get_scanout_position()
137 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { in vc4_crtc_get_scanout_position()
142 *hpos += mode->crtc_htotal / 2; in vc4_crtc_get_scanout_position()
146 /* This is the offset we need for translating hvs -> pv scanout pos. */ in vc4_crtc_get_scanout_position()
147 fifo_lines = cob_size / mode->crtc_hdisplay; in vc4_crtc_get_scanout_position()
162 * incrementing vpos. Therefore we choose HVS read position - in vc4_crtc_get_scanout_position()
166 *vpos -= fifo_lines + 1; in vc4_crtc_get_scanout_position()
174 * fifo with new lines from the top-most lines of the new framebuffers. in vc4_crtc_get_scanout_position()
180 vblank_lines = mode->vtotal - mode->vdisplay; in vc4_crtc_get_scanout_position()
192 *vpos = -vblank_lines; in vc4_crtc_get_scanout_position()
195 *stime = vc4_crtc->t_vblank; in vc4_crtc_get_scanout_position()
197 *etime = vc4_crtc->t_vblank; in vc4_crtc_get_scanout_position()
225 struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev); in vc4_get_fifo_full_level()
226 u32 fifo_len_bytes = pv_data->fifo_depth; in vc4_get_fifo_full_level()
241 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX; in vc4_get_fifo_full_level()
243 return fifo_len_bytes - 14; in vc4_get_fifo_full_level()
251 if (crtc_data->hvs_output == 5) in vc4_get_fifo_full_level()
267 if (vc4->gen == VC4_GEN_4) in vc4_get_fifo_full_level()
268 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1; in vc4_get_fifo_full_level()
270 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX; in vc4_get_fifo_full_level()
299 WARN_ON(hweight32(state->encoder_mask) > 1); in vc4_get_crtc_encoder()
301 drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) in vc4_get_crtc_encoder()
310 struct drm_device *dev = crtc->dev; in vc4_crtc_pixelvalve_reset()
326 struct drm_device *dev = crtc->dev; in vc4_crtc_config_pv()
331 struct drm_crtc_state *crtc_state = crtc->state; in vc4_crtc_config_pv()
332 struct drm_display_mode *mode = &crtc_state->adjusted_mode; in vc4_crtc_config_pv()
333 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; in vc4_crtc_config_pv()
334 bool is_hdmi = vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0 || in vc4_crtc_config_pv()
335 vc4_encoder->type == VC4_ENCODER_TYPE_HDMI1; in vc4_crtc_config_pv()
336 u32 pixel_rep = ((mode->flags & DRM_MODE_FLAG_DBLCLK) && !is_hdmi) ? 2 : 1; in vc4_crtc_config_pv()
337 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || in vc4_crtc_config_pv()
338 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); in vc4_crtc_config_pv()
339 bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1; in vc4_crtc_config_pv()
340 bool is_vec = vc4_encoder->type == VC4_ENCODER_TYPE_VEC; in vc4_crtc_config_pv()
342 u8 ppc = pv_data->pixels_per_clock; in vc4_crtc_config_pv()
344 u16 vert_bp = mode->crtc_vtotal - mode->crtc_vsync_end; in vc4_crtc_config_pv()
345 u16 vert_sync = mode->crtc_vsync_end - mode->crtc_vsync_start; in vc4_crtc_config_pv()
346 u16 vert_fp = mode->crtc_vsync_start - mode->crtc_vdisplay; in vc4_crtc_config_pv()
355 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev); in vc4_crtc_config_pv()
356 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n", in vc4_crtc_config_pv()
358 drm_print_regset32(&p, &vc4_crtc->regset); in vc4_crtc_config_pv()
364 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc, in vc4_crtc_config_pv()
366 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc, in vc4_crtc_config_pv()
370 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc, in vc4_crtc_config_pv()
372 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, in vc4_crtc_config_pv()
377 u32 field_delay = mode->htotal * pixel_rep / (2 * ppc); in vc4_crtc_config_pv()
384 if (mode->htotal == 858) { in vc4_crtc_config_pv()
385 /* 525-line mode (NTSC or PAL-M) */ in vc4_crtc_config_pv()
400 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); in vc4_crtc_config_pv()
427 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); in vc4_crtc_config_pv()
430 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); in vc4_crtc_config_pv()
432 if (vc4->gen == VC4_GEN_5) in vc4_crtc_config_pv()
440 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | in vc4_crtc_config_pv()
444 VC4_SET_FIELD(vc4_encoder->clock_select, in vc4_crtc_config_pv()
448 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev); in vc4_crtc_config_pv()
449 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n", in vc4_crtc_config_pv()
451 drm_print_regset32(&p, &vc4_crtc->regset); in vc4_crtc_config_pv()
460 struct vc4_hvs *hvs = vc4->hvs; in require_hvs_enabled()
473 struct drm_device *dev = crtc->dev; in vc4_crtc_disable()
478 return -ENODEV; in vc4_crtc_disable()
503 if (vc4_encoder && vc4_encoder->post_crtc_disable) in vc4_crtc_disable()
504 vc4_encoder->post_crtc_disable(encoder, state); in vc4_crtc_disable()
507 vc4_hvs_stop_channel(vc4->hvs, channel); in vc4_crtc_disable()
509 if (vc4_encoder && vc4_encoder->post_crtc_powerdown) in vc4_crtc_disable()
510 vc4_encoder->post_crtc_powerdown(encoder, state); in vc4_crtc_disable()
519 struct drm_device *drm = crtc->dev; in vc4_crtc_disable_at_boot()
530 if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node, in vc4_crtc_disable_at_boot()
531 "brcm,bcm2711-pixelvalve2") || in vc4_crtc_disable_at_boot()
532 of_device_is_compatible(vc4_crtc->pdev->dev.of_node, in vc4_crtc_disable_at_boot()
533 "brcm,bcm2711-pixelvalve4"))) in vc4_crtc_disable_at_boot()
542 channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output); in vc4_crtc_disable_at_boot()
551 encoder_type = pv_data->encoder_types[encoder_sel]; in vc4_crtc_disable_at_boot()
557 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); in vc4_crtc_disable_at_boot()
576 struct drm_device *dev = crtc->dev; in vc4_crtc_send_vblank()
579 if (!crtc->state || !crtc->state->event) in vc4_crtc_send_vblank()
582 spin_lock_irqsave(&dev->event_lock, flags); in vc4_crtc_send_vblank()
583 drm_crtc_send_vblank_event(crtc, crtc->state->event); in vc4_crtc_send_vblank()
584 crtc->state->event = NULL; in vc4_crtc_send_vblank()
585 spin_unlock_irqrestore(&dev->event_lock, flags); in vc4_crtc_send_vblank()
595 struct drm_device *dev = crtc->dev; in vc4_crtc_atomic_disable()
598 crtc->name, crtc->base.id, encoder->name, encoder->base.id); in vc4_crtc_atomic_disable()
605 vc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel); in vc4_crtc_atomic_disable()
619 struct drm_device *dev = crtc->dev; in vc4_crtc_atomic_enable()
626 crtc->name, crtc->base.id, encoder->name, encoder->base.id); in vc4_crtc_atomic_enable()
640 if (vc4_encoder->pre_crtc_configure) in vc4_crtc_atomic_enable()
641 vc4_encoder->pre_crtc_configure(encoder, state); in vc4_crtc_atomic_enable()
647 if (vc4_encoder->pre_crtc_enable) in vc4_crtc_atomic_enable()
648 vc4_encoder->pre_crtc_enable(encoder, state); in vc4_crtc_atomic_enable()
656 if (vc4_encoder->post_crtc_enable) in vc4_crtc_atomic_enable()
657 vc4_encoder->post_crtc_enable(encoder, state); in vc4_crtc_atomic_enable()
666 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { in vc4_crtc_mode_valid()
668 crtc->base.id); in vc4_crtc_mode_valid()
684 *left = vc4_state->margins.left; in vc4_crtc_get_margins()
685 *right = vc4_state->margins.right; in vc4_crtc_get_margins()
686 *top = vc4_state->margins.top; in vc4_crtc_get_margins()
687 *bottom = vc4_state->margins.bottom; in vc4_crtc_get_margins()
694 for_each_new_connector_in_state(state->state, conn, conn_state, i) { in vc4_crtc_get_margins()
695 if (conn_state->crtc != state->crtc) in vc4_crtc_get_margins()
698 *left = conn_state->tv.margins.left; in vc4_crtc_get_margins()
699 *right = conn_state->tv.margins.right; in vc4_crtc_get_margins()
700 *top = conn_state->tv.margins.top; in vc4_crtc_get_margins()
701 *bottom = conn_state->tv.margins.bottom; in vc4_crtc_get_margins()
723 const struct drm_display_mode *mode = &crtc_state->adjusted_mode; in vc4_crtc_atomic_check()
726 if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) { in vc4_crtc_atomic_check()
727 vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 8000, in vc4_crtc_atomic_check()
728 mode->clock * 9 / 10) * 1000; in vc4_crtc_atomic_check()
730 vc4_state->hvs_load = mode->clock * 1000; in vc4_crtc_atomic_check()
736 if (conn_state->crtc != crtc) in vc4_crtc_atomic_check()
739 if (memcmp(&vc4_state->margins, &conn_state->tv.margins, in vc4_crtc_atomic_check()
740 sizeof(vc4_state->margins))) { in vc4_crtc_atomic_check()
741 memcpy(&vc4_state->margins, &conn_state->tv.margins, in vc4_crtc_atomic_check()
742 sizeof(vc4_state->margins)); in vc4_crtc_atomic_check()
748 crtc_state->zpos_changed = true; in vc4_crtc_atomic_check()
759 struct drm_device *dev = crtc->dev; in vc4_enable_vblank()
763 return -ENODEV; in vc4_enable_vblank()
775 struct drm_device *dev = crtc->dev; in vc4_disable_vblank()
788 struct drm_crtc *crtc = &vc4_crtc->base; in vc4_crtc_handle_page_flip()
789 struct drm_device *dev = crtc->dev; in vc4_crtc_handle_page_flip()
791 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_handle_page_flip()
792 u32 chan = vc4_crtc->current_hvs_channel; in vc4_crtc_handle_page_flip()
795 spin_lock_irqsave(&dev->event_lock, flags); in vc4_crtc_handle_page_flip()
796 spin_lock(&vc4_crtc->irq_lock); in vc4_crtc_handle_page_flip()
797 if (vc4_crtc->event && in vc4_crtc_handle_page_flip()
798 (vc4_crtc->current_dlist == HVS_READ(SCALER_DISPLACTX(chan)) || in vc4_crtc_handle_page_flip()
799 vc4_crtc->feeds_txp)) { in vc4_crtc_handle_page_flip()
800 drm_crtc_send_vblank_event(crtc, vc4_crtc->event); in vc4_crtc_handle_page_flip()
801 vc4_crtc->event = NULL; in vc4_crtc_handle_page_flip()
812 spin_unlock(&vc4_crtc->irq_lock); in vc4_crtc_handle_page_flip()
813 spin_unlock_irqrestore(&dev->event_lock, flags); in vc4_crtc_handle_page_flip()
818 crtc->t_vblank = ktime_get(); in vc4_crtc_handle_vblank()
819 drm_crtc_handle_vblank(&crtc->base); in vc4_crtc_handle_vblank()
856 struct drm_crtc *crtc = flip_state->crtc; in vc4_async_page_flip_complete()
857 struct drm_device *dev = crtc->dev; in vc4_async_page_flip_complete()
858 struct drm_plane *plane = crtc->primary; in vc4_async_page_flip_complete()
860 vc4_plane_async_set_fb(plane, flip_state->fb); in vc4_async_page_flip_complete()
861 if (flip_state->event) { in vc4_async_page_flip_complete()
864 spin_lock_irqsave(&dev->event_lock, flags); in vc4_async_page_flip_complete()
865 drm_crtc_send_vblank_event(crtc, flip_state->event); in vc4_async_page_flip_complete()
866 spin_unlock_irqrestore(&dev->event_lock, flags); in vc4_async_page_flip_complete()
870 drm_framebuffer_put(flip_state->fb); in vc4_async_page_flip_complete()
872 if (flip_state->old_fb) in vc4_async_page_flip_complete()
873 drm_framebuffer_put(flip_state->old_fb); in vc4_async_page_flip_complete()
884 if (flip_state->old_fb) { in vc4_async_page_flip_seqno_complete()
886 drm_fb_dma_get_gem_obj(flip_state->old_fb, 0); in vc4_async_page_flip_seqno_complete()
887 bo = to_vc4_bo(&dma_bo->base); in vc4_async_page_flip_seqno_complete()
897 * FIXME: we should move to generic async-page-flip when in vc4_async_page_flip_seqno_complete()
899 * hand-made cleanup_fb() logic. in vc4_async_page_flip_seqno_complete()
918 struct drm_framebuffer *fb = flip_state->fb; in vc4_async_set_fence_cb()
924 if (vc4->gen == VC4_GEN_4) { in vc4_async_set_fence_cb()
925 struct vc4_bo *bo = to_vc4_bo(&dma_bo->base); in vc4_async_set_fence_cb()
927 return vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno, in vc4_async_set_fence_cb()
931 ret = dma_resv_get_singleton(dma_bo->base.resv, DMA_RESV_USAGE_READ, &fence); in vc4_async_set_fence_cb()
937 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence); in vc4_async_set_fence_cb()
942 if (dma_fence_add_callback(fence, &flip_state->cb.fence, in vc4_async_set_fence_cb()
944 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence); in vc4_async_set_fence_cb()
955 struct drm_device *dev = crtc->dev; in vc4_async_page_flip_common()
956 struct drm_plane *plane = crtc->primary; in vc4_async_page_flip_common()
961 return -ENOMEM; in vc4_async_page_flip_common()
964 flip_state->fb = fb; in vc4_async_page_flip_common()
965 flip_state->crtc = crtc; in vc4_async_page_flip_common()
966 flip_state->event = event; in vc4_async_page_flip_common()
972 * FIXME: we should move to generic async-page-flip when it's in vc4_async_page_flip_common()
973 * available, so that we can get rid of this hand-made cleanup_fb() in vc4_async_page_flip_common()
976 flip_state->old_fb = plane->state->fb; in vc4_async_page_flip_common()
977 if (flip_state->old_fb) in vc4_async_page_flip_common()
978 drm_framebuffer_get(flip_state->old_fb); in vc4_async_page_flip_common()
986 drm_atomic_set_fb_for_plane(plane->state, fb); in vc4_async_page_flip_common()
994 /* Implements async (non-vblank-synced) page flips.
1005 struct drm_device *dev = crtc->dev; in vc4_async_page_flip()
1008 struct vc4_bo *bo = to_vc4_bo(&dma_bo->base); in vc4_async_page_flip()
1011 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) in vc4_async_page_flip()
1012 return -ENODEV; in vc4_async_page_flip()
1017 * plane is later updated through the non-async path. in vc4_async_page_flip()
1019 * FIXME: we should move to generic async-page-flip when in vc4_async_page_flip()
1021 * hand-made prepare_fb() logic. in vc4_async_page_flip()
1051 struct drm_device *dev = crtc->dev; in vc4_page_flip()
1054 if (vc4->gen > VC4_GEN_4) in vc4_page_flip()
1071 old_vc4_state = to_vc4_crtc_state(crtc->state); in vc4_crtc_duplicate_state()
1072 vc4_state->margins = old_vc4_state->margins; in vc4_crtc_duplicate_state()
1073 vc4_state->assigned_channel = old_vc4_state->assigned_channel; in vc4_crtc_duplicate_state()
1075 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base); in vc4_crtc_duplicate_state()
1076 return &vc4_state->base; in vc4_crtc_duplicate_state()
1082 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev); in vc4_crtc_destroy_state()
1085 if (drm_mm_node_allocated(&vc4_state->mm)) { in vc4_crtc_destroy_state()
1088 spin_lock_irqsave(&vc4->hvs->mm_lock, flags); in vc4_crtc_destroy_state()
1089 drm_mm_remove_node(&vc4_state->mm); in vc4_crtc_destroy_state()
1090 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); in vc4_crtc_destroy_state()
1101 if (crtc->state) in vc4_crtc_reset()
1102 vc4_crtc_destroy_state(crtc, crtc->state); in vc4_crtc_reset()
1106 crtc->state = NULL; in vc4_crtc_reset()
1110 vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED; in vc4_crtc_reset()
1111 __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base); in vc4_crtc_reset()
1116 struct drm_device *drm = crtc->dev; in vc4_crtc_late_register()
1120 vc4_debugfs_add_regset32(drm, crtc_data->debugfs_name, in vc4_crtc_late_register()
1121 &vc4_crtc->regset); in vc4_crtc_late_register()
1153 .name = "pixelvalve-0",
1168 .name = "pixelvalve-1",
1183 .name = "pixelvalve-2",
1198 .name = "pixelvalve-0",
1213 .name = "pixelvalve-1",
1228 .name = "pixelvalve-2",
1242 .name = "pixelvalve-3",
1256 .name = "pixelvalve-4",
1269 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1270 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1271 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1272 { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1273 { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1274 { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1275 { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1276 { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1285 const enum vc4_encoder_type *encoder_types = pv_data->encoder_types; in vc4_set_crtc_possible_masks()
1292 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) in vc4_set_crtc_possible_masks()
1296 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) { in vc4_set_crtc_possible_masks()
1297 if (vc4_encoder->type == encoder_types[i]) { in vc4_set_crtc_possible_masks()
1298 vc4_encoder->clock_select = i; in vc4_set_crtc_possible_masks()
1299 encoder->possible_crtcs |= drm_crtc_mask(crtc); in vc4_set_crtc_possible_masks()
1307 * __vc4_crtc_init - Initializes a CRTC
1334 struct drm_crtc *crtc = &vc4_crtc->base; in __vc4_crtc_init()
1338 vc4_crtc->data = data; in __vc4_crtc_init()
1339 vc4_crtc->pdev = pdev; in __vc4_crtc_init()
1340 vc4_crtc->feeds_txp = feeds_txp; in __vc4_crtc_init()
1341 spin_lock_init(&vc4_crtc->irq_lock); in __vc4_crtc_init()
1343 crtc_funcs, data->name); in __vc4_crtc_init()
1349 if (vc4->gen == VC4_GEN_4) { in __vc4_crtc_init()
1350 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); in __vc4_crtc_init()
1351 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); in __vc4_crtc_init()
1356 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size); in __vc4_crtc_init()
1359 for (i = 0; i < crtc->gamma_size; i++) { in __vc4_crtc_init()
1360 vc4_crtc->lut_r[i] = i; in __vc4_crtc_init()
1361 vc4_crtc->lut_g[i] = i; in __vc4_crtc_init()
1362 vc4_crtc->lut_b[i] = i; in __vc4_crtc_init()
1385 dev_err(drm->dev, "failed to construct primary plane\n"); in vc4_crtc_init()
1404 return -ENOMEM; in vc4_crtc_bind()
1405 crtc = &vc4_crtc->base; in vc4_crtc_bind()
1409 return -ENODEV; in vc4_crtc_bind()
1411 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0); in vc4_crtc_bind()
1412 if (IS_ERR(vc4_crtc->regs)) in vc4_crtc_bind()
1413 return PTR_ERR(vc4_crtc->regs); in vc4_crtc_bind()
1415 vc4_crtc->regset.base = vc4_crtc->regs; in vc4_crtc_bind()
1416 vc4_crtc->regset.regs = crtc_regs; in vc4_crtc_bind()
1417 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs); in vc4_crtc_bind()
1419 ret = vc4_crtc_init(drm, pdev, vc4_crtc, &pv_data->base, in vc4_crtc_bind()
1458 return component_add(&pdev->dev, &vc4_crtc_ops); in vc4_crtc_dev_probe()
1463 component_del(&pdev->dev, &vc4_crtc_ops); in vc4_crtc_dev_remove()