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Searched full:base_clk (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/mmc/host/
H A Dsdhci-brcmstb.c52 struct clk *base_clk; member
376 struct clk *base_clk = NULL; in sdhci_brcmstb_probe() local
456 base_clk = devm_clk_get_optional(&pdev->dev, "sdio_freq"); in sdhci_brcmstb_probe()
457 if (IS_ERR(base_clk)) { in sdhci_brcmstb_probe()
462 res = clk_prepare_enable(base_clk); in sdhci_brcmstb_probe()
467 clk_set_rate(base_clk, priv->base_freq_hz); in sdhci_brcmstb_probe()
468 actual_clock_mhz = clk_get_rate(base_clk) / 1000000; in sdhci_brcmstb_probe()
477 priv->base_clk = base_clk; in sdhci_brcmstb_probe()
489 clk_disable_unprepare(base_clk); in sdhci_brcmstb_probe()
508 clk_disable_unprepare(priv->base_clk); in sdhci_brcmstb_suspend()
[all …]
/linux/drivers/clk/sunxi/
H A Dclk-a10-pll2.c42 struct clk **clks, *base_clk, *prediv_clk; in sun4i_pll2_setup() local
95 base_clk = clk_register_composite(NULL, "pll2-base", in sun4i_pll2_setup()
101 if (IS_ERR(base_clk)) { in sun4i_pll2_setup()
106 parent = __clk_get_name(base_clk); in sun4i_pll2_setup()
/linux/drivers/pwm/
H A Dpwm-samsung.c76 * @base_clk: base clock used to drive the timers
87 struct clk *base_clk; member
172 rate = clk_get_rate(our_chip->base_clk); in pwm_samsung_get_tin_rate()
573 our_chip->base_clk = devm_clk_get_enabled(&pdev->dev, "timers"); in pwm_samsung_probe()
574 if (IS_ERR(our_chip->base_clk)) in pwm_samsung_probe()
575 return dev_err_probe(dev, PTR_ERR(our_chip->base_clk), in pwm_samsung_probe()
592 dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n", in pwm_samsung_probe()
593 clk_get_rate(our_chip->base_clk), in pwm_samsung_probe()
/linux/Documentation/devicetree/bindings/mmc/
H A Dmicrochip,sdhci-pic32.yaml37 - const: base_clk
60 clock-names = "base_clk", "sys_clk";
/linux/arch/arm/boot/dts/nspire/
H A Dnspire.dtsi44 base_clk: base_clk { label
52 clocks = <&base_clk>;
H A Dnspire-classic.dtsi44 &base_clk {
H A Dnspire-cx.dts39 &base_clk {
/linux/Documentation/devicetree/bindings/clock/
H A Dnspire-clock.txt23 clocks = <&base_clk>;
/linux/drivers/spi/
H A Dspi-bcm-qspi.c225 u32 base_clk; member
653 qspi->base_clk = MSPI_BASE_FREQ; in bcm_qspi_hw_set_parms()
657 qspi->base_clk = MSPI_BASE_FREQ * 4; in bcm_qspi_hw_set_parms()
685 qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2); in bcm_qspi_hw_set_parms()
686 spbr = bcm_qspi_calc_spbr(qspi->base_clk, xp); in bcm_qspi_hw_set_parms()
1591 qspi->base_clk = clk_get_rate(qspi->clk); in bcm_qspi_probe()
1593 qspi->base_clk = MSPI_BASE_FREQ; in bcm_qspi_probe()
1607 qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2); in bcm_qspi_probe()
/linux/arch/mips/boot/dts/pic32/
H A Dpic32mzda.dtsi233 clock-names = "base_clk", "sys_clk";