| /freebsd/contrib/ofed/include/ |
| H A D | udma_barrier.h | 38 /* Barriers for DMA.
40 These barriers are expliclty only for use with user DMA operations. If you
41 are looking for barriers to use with cache-coherent multi-threaded
44 of these barriers.
46 When reasoning about these barriers there are two objects:
60 The providers have a very regular and predictable use of these barriers,
192 barriers.
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| /freebsd/sys/dev/ath/ |
| H A D | ah_osdep.h | 113 * Read and write barriers. Some platforms require more strongly ordered
115 * is either an x86 or the bus layer will do the barriers for you.
117 * Read barriers should occur before each read, and write barriers
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| /freebsd/lib/libsys/ |
| H A D | membarrier.2 | 67 memory barriers.
75 memory barriers.
85 memory barriers.
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| /freebsd/share/man/man9/ |
| H A D | atomic.9 | 228 one-way barriers to reordering that enable the implementations of
288 Essentially, this is why fences are two-way barriers.
403 and do not have any variants with memory barriers at this time.
426 and do not have any variants with memory barriers at this time.
457 and do not have any variants with memory barriers at this time.
488 and generally do not have any variants with memory barriers at this time
|
| H A D | bus_space.9 | 717 .Dq barriers
720 are three types of barriers: read, write, and read/write.
725 write barriers.)
726 Read/write barriers force all reads and writes started
730 appropriate barriers, and assume only the read/write ordering imposed by
1277 .Sh BARRIERS
1356 The barriers in the example above are specified to cover the absolute
1422 There is no way to insert barriers between reads of
1474 There is no way to insert barriers between writes of
1529 There is no way to insert barriers between reads or writes of
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMOptimizeBarriersPass.cpp | 17 #define DEBUG_TYPE "double barriers"
34 StringRef getPassName() const override { return "optimise barriers pass"; } in getPassName()
102 /// barriers
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| /freebsd/sys/compat/linuxkpi/common/include/linux/ |
| H A D | io.h | 73 /* Access MMIO registers atomically without barriers and byte swapping. */
135 /* Access little-endian MMIO registers atomically with memory barriers. */
231 /* Access little-endian MMIO registers atomically without memory barriers. */
|
| /freebsd/contrib/bmake/unit-tests/ |
| H A D | depsrc-wait.mk | 31 # There are 3 groups of 3 targets, with .WAIT barriers in between. Each of
|
| /freebsd/contrib/llvm-project/openmp/runtime/src/ |
| H A D | kmp_itt.inl | 126 LINKAGE void __kmp_itt_region_forking(int gtid, int team_size, int barriers) { argument
159 if (barriers) {
390 /* Barriers reporting.
412 different barriers (even whithin the same team). So let us use team address
429 // solution, and reporting fork/join barriers to ITT should be revisited.
437 // barriers of different types do not have the same ids.
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SpeculationHardening.cpp | 84 // - Implement this functionality using full speculation barriers, akin to the
87 // Note that this pass already inserts the full speculation barriers if the
362 // If full control flow speculation barriers are used, emit a control flow in insertSPToRegTaintPropagation()
387 // If full control flow speculation barriers are used, there will not be in insertRegToSPTaintPropagation()
564 // miss-speculation isn't happening because we're already inserting barriers in expandSpeculationSafeValue()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCA/ |
| H A D | X86CustomBehaviour.h | 28 /// as load and store barriers.
|
| /freebsd/share/man/man3/ |
| H A D | pthread_barrierattr.3 | 136 Support for process-shared barriers appeared in
|
| H A D | ATOMIC_VAR_INIT.3 | 225 .Sh BARRIERS
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| /freebsd/contrib/lua/src/ |
| H A D | lstate.h | 51 ** lists. Moreover, barriers can age young objects in young lists as
86 ** marked black because assignments to them must activate barriers (to
88 ** - Open upvales are kept gray to avoid barriers, but they stay out
|
| /freebsd/cddl/contrib/opensolaris/tools/ctf/cvt/ |
| H A D | barrier.c | 31 * threads to wait for each other at given points. Barriers are initialized
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSubtarget.cpp | 135 "cannot combine indirect jumps with hazard barriers and microMIPS"); in MipsSubtarget()
138 "indirect jumps with hazard barriers requires MIPS32R2 or later"); in MipsSubtarget()
|
| /freebsd/contrib/netbsd-tests/lib/libpthread/ |
| H A D | t_barrier.c | 71 atf_tc_set_md_var(tc, "descr", "Checks barriers"); in ATF_TC_HEAD()
|
| /freebsd/sys/dev/uart/ |
| H A D | uart.h | 103 * the UART. Since barriers don't use the length field currently, we put
|
| /freebsd/sys/contrib/ck/src/ |
| H A D | ck_barrier_dissemination.c | 118 * Dissemination barriers use two sets of flags to prevent race conditions in ck_barrier_dissemination()
|
| H A D | ck_barrier_combining.c | 70 * This implementation of software combining tree barriers
|
| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | arm,cci-400.yaml | 15 and manage coherency, TLB invalidations and memory barriers.
|
| H A D | cci.txt | 7 transactions and manage coherency, TLB invalidations and memory barriers.
|
| /freebsd/sys/sys/ |
| H A D | smr_types.h | 40 * are synchronized with readers via included barriers.
|
| /freebsd/sys/dev/virtio/block/ |
| H A D | virtio_blk.h | 48 #define VIRTIO_BLK_F_BARRIER 0x0001 /* Does host support barriers? */
|
| /freebsd/sys/kern/ |
| H A D | subr_devstat.c | 287 * atomic instructions using appropriate memory barriers.
395 * XXX guarantees us proper write barriers. I don't believe the in sysctl_devstat()
|