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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
H A Dbase.c27 nvkm_bar_flush(struct nvkm_bar *bar) in nvkm_bar_flush() argument
29 if (bar && bar->func->flush) in nvkm_bar_flush()
30 bar->func->flush(bar); in nvkm_bar_flush()
36 return device->bar->func->bar1.vmm(device->bar); in nvkm_bar_bar1_vmm()
42 struct nvkm_bar *bar = device->bar; in nvkm_bar_bar1_reset() local
43 if (bar) { in nvkm_bar_bar1_reset()
44 bar->func->bar1.init(bar); in nvkm_bar_bar1_reset()
45 bar->func->bar1.wait(bar); in nvkm_bar_bar1_reset()
55 struct nvkm_bar *bar = device->bar; in nvkm_bar_bar2_vmm() local
56 if (bar && bar->bar2) in nvkm_bar_bar2_vmm()
[all …]
H A Dnv50.c34 struct nv50_bar *bar = nv50_bar(base); in nv50_bar_flush() local
35 struct nvkm_device *device = bar->base.subdev.device; in nv50_bar_flush()
37 spin_lock_irqsave(&bar->base.lock, flags); in nv50_bar_flush()
43 spin_unlock_irqrestore(&bar->base.lock, flags); in nv50_bar_flush()
59 nv50_bar_bar1_fini(struct nvkm_bar *bar) in nv50_bar_bar1_fini() argument
61 nvkm_wr32(bar->subdev.device, 0x001708, 0x00000000); in nv50_bar_bar1_fini()
68 struct nv50_bar *bar = nv50_bar(base); in nv50_bar_bar1_init() local
69 nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4); in nv50_bar_bar1_init()
79 nv50_bar_bar2_fini(struct nvkm_bar *bar) in nv50_bar_bar2_fini() argument
81 nvkm_wr32(bar->subdev.device, 0x00170c, 0x00000000); in nv50_bar_bar2_fini()
[all …]
H A Dgf100.c34 return gf100_bar(base)->bar[1].vmm; in gf100_bar_bar1_vmm()
46 gf100_bar_bar1_fini(struct nvkm_bar *bar) in gf100_bar_bar1_fini() argument
48 nvkm_mask(bar->subdev.device, 0x001704, 0x80000000, 0x00000000); in gf100_bar_bar1_fini()
55 struct gf100_bar *bar = gf100_bar(base); in gf100_bar_bar1_init() local
56 const u32 addr = nvkm_memory_addr(bar->bar[1].inst) >> 12; in gf100_bar_bar1_init()
63 return gf100_bar(base)->bar[0].vmm; in gf100_bar_bar2_vmm()
67 gf100_bar_bar2_fini(struct nvkm_bar *bar) in gf100_bar_bar2_fini() argument
69 nvkm_mask(bar->subdev.device, 0x001714, 0x80000000, 0x00000000); in gf100_bar_bar2_fini()
76 struct gf100_bar *bar = gf100_bar(base); in gf100_bar_bar2_init() local
77 u32 addr = nvkm_memory_addr(bar->bar[0].inst) >> 12; in gf100_bar_bar2_init()
[all …]
H A Dtu102.c29 tu102_bar_bar2_wait(struct nvkm_bar *bar) in tu102_bar_bar2_wait() argument
31 struct nvkm_device *device = bar->subdev.device; in tu102_bar_bar2_wait()
39 tu102_bar_bar2_fini(struct nvkm_bar *bar) in tu102_bar_bar2_fini() argument
41 nvkm_mask(bar->subdev.device, 0xb80f48, 0x80000000, 0x00000000); in tu102_bar_bar2_fini()
48 struct gf100_bar *bar = gf100_bar(base); in tu102_bar_bar2_init() local
49 u32 addr = nvkm_memory_addr(bar->bar[0].inst) >> 12; in tu102_bar_bar2_init()
50 if (bar->bar2_halve) in tu102_bar_bar2_init()
56 tu102_bar_bar1_wait(struct nvkm_bar *bar) in tu102_bar_bar1_wait() argument
58 struct nvkm_device *device = bar->subdev.device; in tu102_bar_bar1_wait()
66 tu102_bar_bar1_fini(struct nvkm_bar *bar) in tu102_bar_bar1_fini() argument
[all …]
/linux/drivers/pci/
H A Drebar.c3 * PCI Resizable BAR Extended Capability handling.
22 * pci_rebar_bytes_to_size - Convert size in bytes to PCI BAR Size
25 * Convert size in bytes to encoded BAR Size in Resizable BAR Capability
28 * Return: encoded BAR Size as defined in the PCIe spec (0=1MB, 31=128TB)
41 * pci_rebar_size_to_bytes - Convert encoded BAR Size to size in bytes
42 * @size: encoded BAR Size as defined in the PCIe spec (0=1MB, 31=128TB)
44 * Return: BAR size in bytes
58 * pci_rebar_find_pos - find position of resize control reg for BAR
60 * @bar: BAR to find
62 * Helper to find the position of the control register for a BAR.
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H A Diomap.c15 * pci_iomap_range - create a virtual mapping cookie for a PCI BAR
16 * @dev: PCI device that owns the BAR
17 * @bar: BAR number
18 * @offset: map memory at the given offset in BAR
21 * Using this function you will get a __iomem address to your device BAR.
27 * the complete BAR from offset to the end, pass %0 here.
30 int bar, in pci_iomap_range() argument
37 if (!pci_bar_index_is_valid(bar)) in pci_iomap_range()
40 start = pci_resource_start(dev, bar); in pci_iomap_range()
41 len = pci_resource_len(dev, bar); in pci_iomap_range()
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/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp6000_pcie.c15 * abstraction builds upon this BAR interface.
98 #define NFP_PCIE_P2C_FIXED_SIZE(bar) (1 << (bar)->bitsize) argument
99 #define NFP_PCIE_P2C_BULK_SIZE(bar) (1 << (bar)->bitsize) argument
100 #define NFP_PCIE_P2C_GENERAL_TARGET_OFFSET(bar, x) ((x) << ((bar)->bitsize - 2)) argument
101 #define NFP_PCIE_P2C_GENERAL_TOKEN_OFFSET(bar, x) ((x) << ((bar)->bitsize - 4)) argument
102 #define NFP_PCIE_P2C_GENERAL_SIZE(bar) (1 << ((bar)->bitsize - 4)) argument
116 * struct nfp_bar - describes BAR configuration and usage
118 * @barcfg: cached contents of BAR config CSR
119 * @base: the BAR's base CPP offset
120 * @mask: mask for the BAR aperture (read only)
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
H A Dbar.c22 #include <subdev/bar/gf100.h>
30 #include "nvrm/bar.h"
34 r535_bar_flush(struct nvkm_bar *bar) in r535_bar_flush() argument
39 if (unlikely(!bar->bar2)) { in r535_bar_flush()
40 g84_bar_flush(bar); in r535_bar_flush()
44 ioread32_native(bar->flushBAR2); in r535_bar_flush()
69 r535_bar_bar2_fini(struct nvkm_bar *bar) in r535_bar_bar2_fini() argument
71 struct nvkm_vmm *vmm = gf100_bar(bar)->bar[0].vmm; in r535_bar_bar2_fini()
72 struct nvkm_gsp *gsp = bar->subdev.device->gsp; in r535_bar_bar2_fini()
74 bar->flushBAR2 = bar->flushBAR2PhysMode; in r535_bar_bar2_fini()
[all …]
/linux/drivers/pci/endpoint/functions/
H A Dpci-epf-test.c125 /* default BAR sizes, can be overridden by the user using configfs */
737 enum pci_barno bar; in pci_epf_test_enable_doorbell() local
749 if (db->bar != NO_BAR) { in pci_epf_test_enable_doorbell()
752 * fixed BAR in pci_epf_test_enable_doorbell()
754 bar = db->bar; in pci_epf_test_enable_doorbell()
757 bar = pci_epc_get_next_free_bar(epf_test->epc_features, in pci_epf_test_enable_doorbell()
759 if (bar < BAR_0) in pci_epf_test_enable_doorbell()
776 reg->doorbell_bar = cpu_to_le32(bar); in pci_epf_test_enable_doorbell()
778 if (db->bar == NO_BAR) { in pci_epf_test_enable_doorbell()
779 ret = pci_epf_align_inbound_addr(epf, bar, in pci_epf_test_enable_doorbell()
[all …]
/linux/tools/testing/selftests/bpf/prog_tests/
H A Dcgroup_attach_override.c8 #define BAR "/foo/bar/" macro
28 int drop_prog = -1, allow_prog = -1, foo = -1, bar = -1; in serial_test_cgroup_attach_override() local
55 bar = test__join_cgroup(BAR); in serial_test_cgroup_attach_override()
56 if (CHECK(bar < 0, "cgroup_join_bar", "cgroup setup failed\n")) in serial_test_cgroup_attach_override()
63 if (CHECK(bpf_prog_attach(allow_prog, bar, BPF_CGROUP_INET_EGRESS, in serial_test_cgroup_attach_override()
66 "attach prog to %s failed, errno=%d\n", BAR, errno)) in serial_test_cgroup_attach_override()
72 if (CHECK(bpf_prog_detach(bar, BPF_CGROUP_INET_EGRESS), in serial_test_cgroup_attach_override()
74 "detach prog from %s failed, errno=%d\n", BAR, errno)) in serial_test_cgroup_attach_override()
81 if (CHECK(bpf_prog_attach(allow_prog, bar, BPF_CGROUP_INET_EGRESS, in serial_test_cgroup_attach_override()
84 "attach prog to %s failed, errno=%d\n", BAR, errno)) in serial_test_cgroup_attach_override()
[all …]
H A Dtest_veristat.c243 * veristat_bar.bpf.o, both defining programs 'foo', 'bar' and 'buz'.
259 { "", "foo", "bar", true },
261 { "", "bar", "foo", true },
262 { "", "bar", "bar", true },
263 { "", "bar", "buz", true },
265 { "-f '!*foo*'", "foo", "bar", false },
266 { "-f '!*foo*'", "bar", "foo", false },
267 { "-f '!*foo*'", "bar", "bar", true },
268 { "-f '!*foo*/bar'", "foo", "bar", false },
269 { "-f '!*foo*/bar'", "foo", "buz", true },
[all …]
/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence-hpa-regs.h34 #define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn) \ argument
35 (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(fn) : \
39 #define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn) \ argument
40 (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(fn) : \
56 /* Root Complex BAR Configuration Register */
76 /* BAR control values applicable to both Endpoint Function and Root Complex */
84 #define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ argument
85 (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) * 10))
86 #define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ argument
87 (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) * 10))
[all …]
/linux/drivers/net/ethernet/sfc/
H A Def100.c37 unsigned int bar; member
71 u32 bar = ef100_pci_get_bar_bits(efx, entry_location, EF100_BAR); in ef100_pci_parse_ef100_entry() local
74 "Found EF100 function control window bar=%d offset=0x%llx\n", in ef100_pci_parse_ef100_entry()
75 bar, offset); in ef100_pci_parse_ef100_entry()
83 if (bar == ESE_GZ_CFGBAR_EF100_BAR_NUM_EXPANSION_ROM || in ef100_pci_parse_ef100_entry()
84 bar == ESE_GZ_CFGBAR_EF100_BAR_NUM_INVALID) { in ef100_pci_parse_ef100_entry()
86 "Bad BAR value of %d in Xilinx capabilities EF100 entry.\n", in ef100_pci_parse_ef100_entry()
87 bar); in ef100_pci_parse_ef100_entry()
91 result->bar = bar; in ef100_pci_parse_ef100_entry()
97 static bool ef100_pci_does_bar_overflow(struct efx_nic *efx, int bar, in ef100_pci_does_bar_overflow() argument
[all …]
/linux/samples/trace_events/
H A Dtrace-events-sample.h70 * Here it is trace_foo_bar(char *foo, int bar).
73 * Here it is simply "foo, bar".
94 * __field_struct(struct bar, foo)
96 * __entry->bar.x = y;
108 * memcpy(__entry->foo, bar, 10);
119 * __dynamic_array( int, foo, bar) is similar to: int foo[bar];
124 * memcpy(__get_dynamic_array(foo), bar, 10);
135 * __string(foo, bar) is similar to: strcpy(foo, bar)
175 * __string_len(foo, bar, len)
186 * memcpy(__get_str(foo), bar, len);
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/linux/arch/powerpc/platforms/powernv/
H A Dpci-sriov.c15 * the PHB maps MMIO addresses to a specific PE using the "Memory BAR Table".
24 * For a SR-IOV BAR things are a little more awkward since size and alignment
25 * are not coupled. The alignment is set based on the per-VF BAR size, but
26 * the total BAR area is: number-of-vfs * per-vf-size. The number of VFs
28 * we need to finesse (read: hack) the Linux BAR allocator so that it will
33 * so as a baseline we can assume that we have the following BAR modes
38 * a) A segmented BAR that splits the mapped range into $PE_COUNT equally sized
40 * b) An un-segmented BAR that maps the whole address range to a specific PE.
43 * We prefer to use mode a) since it only requires one MBT entry per SR-IOV BAR
44 * For comparison b) requires one entry per-VF per-BAR, or:
[all …]
/linux/drivers/xen/xen-pciback/
H A Dconf_space_header.c129 struct pci_bar_info *bar = data; in rom_write() local
131 if (unlikely(!bar)) { in rom_write()
140 bar->which = 1; in rom_write()
144 if (tmpval != bar->val && value == bar->val) { in rom_write()
145 /* Allow restoration of bar value. */ in rom_write()
146 pci_write_config_dword(dev, offset, bar->val); in rom_write()
148 bar->which = 0; in rom_write()
162 struct pci_bar_info *bar = data; in bar_write() local
167 if (unlikely(!bar)) { in bar_write()
182 bar->which = 1; in bar_write()
[all …]
/linux/drivers/dma/dw-edma/
H A Ddw-edma-pcie.c50 .bar = a, \
56 enum pci_barno bar; member
99 .rg.bar = BAR_0,
104 /* Channel 0 - BAR 2, offset 0 Mbytes, size 2 Kbytes */
106 /* Channel 1 - BAR 2, offset 2 Mbytes, size 2 Kbytes */
110 /* Channel 0 - BAR 2, offset 4 Mbytes, size 2 Kbytes */
112 /* Channel 1 - BAR 2, offset 6 Mbytes, size 2 Kbytes */
117 /* Channel 0 - BAR 2, offset 8 Mbytes, size 2 Kbytes */
119 /* Channel 1 - BAR 2, offset 9 Mbytes, size 2 Kbytes */
123 /* Channel 0 - BAR 2, offset 10 Mbytes, size 2 Kbytes */
[all …]
/linux/tools/perf/Documentation/
H A Dcallchain-overhead-calculation.txt29 void bar(void) {
35 bar()
40 In this case 'foo' is a child of 'bar', and 'bar' is an immediate
42 'main' is a parent of 'foo' and 'bar', and 'bar' is a parent of 'foo'.
44 Suppose all samples are recorded in 'foo' and 'bar' only. When it's
54 bar
58 40.00% bar
60 --- bar
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/linux/arch/csky/include/asm/
H A Dbarrier.h13 * bar.brwarws: ordering barrier for all load/store instructions
26 * bar.brw
27 * bar.br
28 * bar.bw
29 * bar.arw
30 * bar.ar
31 * bar.aw
32 * bar.brwarw
33 * bar.brarw
34 * bar.bwarw
[all …]
/linux/samples/rust/
H A Drust_driver_pci.rs46 type Bar0<'bound> = pci::Bar<'bound, { regs::END }>;
69 bar: Bar0<'bound>,
85 fn testdev(index: &TestIndex, bar: &Bar0<'_>) -> Result<u32> { in config_space()
87 bar.write_reg(regs::TEST::zeroed().with_index(*index)); in config_space()
89 let offset = bar.read(regs::OFFSET).into_raw() as usize; in config_space()
90 let data = bar.read(regs::DATA).into(); in config_space()
95 bar.try_write8(data, offset)?;
97 Ok(bar.read(regs::COUNT).into())
113 BAR(u32)[6] @ 0x10 { in probe()
132 "pci-testdev config space read32 BAR in unbind()
40 bar: Devres<Bar0>, global() field
117 let bar = bar.access(pdev.as_ref())?; probe() localVariable
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/linux/include/linux/
H A Dpci-epc.h70 * register windows and descriptor memories into BAR space. This enum
83 * @bar: BAR number where this resource is already exposed to the RC
85 * @bar_offset: offset within @bar where the resource starts (valid iff
86 * @bar != NO_BAR)
93 enum pci_barno bar; member
108 * @set_bar: ops to configure the BAR
109 * @clear_bar: ops to reset the BAR
237 * enum pci_epc_bar_type - configurability of endpoint BAR
238 * @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC.
239 * @BAR_FIXED: The BAR mask is fixed by the hardware.
[all …]
H A Dpci-epf.h114 * struct pci_epf_bar_submap - BAR subrange for inbound mapping
119 * complete BAR layout. This allows an EPC driver to program multiple
120 * inbound translation windows for a single BAR when supported by the
121 * controller. The array order defines the BAR layout (submap[0] at offset
130 * struct pci_epf_bar - represents the BAR of EPF device
131 * @phys_addr: physical address that should be mapped to the BAR
133 * @size: the size of the address space present in BAR
136 * @barno: BAR number
137 * @flags: flags that are set for the BAR
162 * @msg: Doorbell address/data pair to be mapped into BAR space.
[all …]
H A Dpnp.h60 unsigned int bar) in pnp_port_start() argument
62 struct resource *res = pnp_get_resource(dev, IORESOURCE_IO, bar); in pnp_port_start()
70 unsigned int bar) in pnp_port_end() argument
72 struct resource *res = pnp_get_resource(dev, IORESOURCE_IO, bar); in pnp_port_end()
80 unsigned int bar) in pnp_port_flags() argument
82 struct resource *res = pnp_get_resource(dev, IORESOURCE_IO, bar); in pnp_port_flags()
89 static inline int pnp_port_valid(struct pnp_dev *dev, unsigned int bar) in pnp_port_valid() argument
91 return pnp_resource_valid(pnp_get_resource(dev, IORESOURCE_IO, bar)); in pnp_port_valid()
95 unsigned int bar) in pnp_port_len() argument
97 struct resource *res = pnp_get_resource(dev, IORESOURCE_IO, bar); in pnp_port_len()
[all …]
/linux/arch/arm/mm/
H A Dpmsa-v8.c141 static int __init __pmsav8_setup_region(unsigned int number, u32 bar, u32 lar) in __pmsav8_setup_region() argument
150 prbar_write(bar); in __pmsav8_setup_region()
153 mpu_rgn_info.rgns[number].prbar = bar; in __pmsav8_setup_region()
163 u32 bar, lar; in pmsav8_setup_ram() local
168 bar = start; in pmsav8_setup_ram()
171 bar |= PMSAv8_AP_PL1RW_PL0RW | PMSAv8_RGN_SHARED; in pmsav8_setup_ram()
174 return __pmsav8_setup_region(number, bar, lar); in pmsav8_setup_ram()
179 u32 bar, lar; in pmsav8_setup_io() local
184 bar = start; in pmsav8_setup_io()
187 bar |= PMSAv8_AP_PL1RW_PL0RW | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN; in pmsav8_setup_io()
[all …]
/linux/sound/soc/sof/
H A Dops.c46 bool snd_sof_dsp_update_bits_unlocked(struct snd_sof_dev *sdev, u32 bar, in snd_sof_pci_update_bits()
52 ret = snd_sof_dsp_read(sdev, bar, offset); in snd_sof_dsp_update_bits_unlocked()
60 snd_sof_dsp_write(sdev, bar, offset, new); in snd_sof_dsp_update_bits_unlocked()
66 bool snd_sof_dsp_update_bits64_unlocked(struct snd_sof_dev *sdev, u32 bar, in snd_sof_dsp_update_bits_unlocked()
71 old = snd_sof_dsp_read64(sdev, bar, offset); in snd_sof_dsp_update_bits64_unlocked() argument
78 snd_sof_dsp_write64(sdev, bar, offset, new); in snd_sof_dsp_update_bits64_unlocked()
85 bool snd_sof_dsp_update_bits(struct snd_sof_dev *sdev, u32 bar, u32 offset, in snd_sof_dsp_update_bits64_unlocked()
89 return snd_sof_dsp_update_bits_unlocked(sdev, bar, offset, mask, value);
93 bool snd_sof_dsp_update_bits64(struct snd_sof_dev *sdev, u32 bar, u32 offset, in snd_sof_dsp_update_bits()
97 return snd_sof_dsp_update_bits64_unlocked(sdev, bar, offse in snd_sof_dsp_update_bits()
51 snd_sof_dsp_update_bits_unlocked(struct snd_sof_dev * sdev,u32 bar,u32 offset,u32 mask,u32 value) snd_sof_dsp_update_bits_unlocked() argument
90 snd_sof_dsp_update_bits(struct snd_sof_dev * sdev,u32 bar,u32 offset,u32 mask,u32 value) snd_sof_dsp_update_bits() argument
104 snd_sof_dsp_update_bits64(struct snd_sof_dev * sdev,u32 bar,u32 offset,u64 mask,u64 value) snd_sof_dsp_update_bits64() argument
119 snd_sof_dsp_update_bits_forced_unlocked(struct snd_sof_dev * sdev,u32 bar,u32 offset,u32 mask,u32 value) snd_sof_dsp_update_bits_forced_unlocked() argument
134 snd_sof_dsp_update_bits_forced(struct snd_sof_dev * sdev,u32 bar,u32 offset,u32 mask,u32 value) snd_sof_dsp_update_bits_forced() argument
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