| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsDSPInstrInfo.td | 115 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
158 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
216 class RDDSP_ENC : RDDSP_FMT<0b10010>;
235 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
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| H A D | Mips16InstrInfo.td | 855 def LwRxSpImmX16: FEXT_RRI16_mem_ins<0b10010, "lw", mem16sp, II_LW>, MayLoad;
893 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIM16Alu> {
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SMEInstrInfo.td | 696 defm FRINTP_2Z2Z: sme2_frint_vector_vg2_multi<"frintp", 0b10010>;
849 defm SMLSLL_MZZ_HtoD : sme2_mla_ll_array_single<"smlsll", 0b10010, MatrixOp64, ZPR16, ZPR4b16…
852 defm SMLSLL_VG2_M2Z2Z_HtoD : sme2_mla_ll_array_vg2_multi<"smlsll", 0b10010, MatrixOp64, ZZ_h_mul_r…
853 defm SMLSLL_VG4_M4Z4Z_HtoD : sme2_mla_ll_array_vg4_multi<"smlsll", 0b10010, MatrixOp64, ZZZZ_h_mul…
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| H A D | AArch64InstrInfo.td | 5853 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", truncssat_u>;
5863 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
6012 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla", null_frag>;
6013 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls", null_frag>;
6458 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
6505 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
8455 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
8471 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
8533 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
8553 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
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| H A D | AArch64SVEInstrInfo.td | 2266 defm SQDECW_XPiWdI : sve_int_pred_pattern_b_s32<0b10010, "sqdecw", int_aarch64_sve_sqdecw_n32>;
2290 defm SQDECW_ZPiI : sve_int_countvlv<0b10010, "sqdecw", ZPR32, int_aarch64_sve_sqdecw, nxv4i32>;
3729 defm UMLALB_ZZZ : sve2_int_mla_long<0b10010, "umlalb", int_aarch64_sve_umlalb>;
4084 …defm LDNT1B_ZZR_D : sve2_mem_gldnt_vs_64_ptrs<0b10010, "ldnt1b", AArch64ldnt1_gather_z, nxv2i8>;
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| H A D | SVEInstrFormats.td | 4358 let Inst{15-11} = 0b10010;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoXTHead.td | 288 def TH_REVW : THRev_r<0b10010, 0b00, "th.revw">;
380 def TH_LURBU : THLoadIndexed<GPR, 0b10010, "th.lurbu">,
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| H A D | RISCVInstrInfoXqci.td | 814 def QC_WRAP : QCIRVInstRR<0b10010, GPR, "qc.wrap">;
1016 def QC_C_MRET : QCIRVInst16CI_NONE<0b10010, "qc.c.mret">;
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| H A D | RISCVInstrInfoXCV.td | 514 defm DOTSP : CVSIMDBinarySigned<0b10010, 0, 0, "dotsp">;
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| H A D | RISCVInstrInfoV.td | 1537 defm VFNCVT_F_XU_W : VNCVTF_IV_VS2<"vfncvt.f.xu.w", 0b010010, 0b10010>;
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| H A D | RISCVInstrInfo.td | 996 let rs2 = 0b10010;
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/ |
| H A D | ResourceManager.h | 338 // C | 0b10010 | 0b10000 | 5
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.td | 401 defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo.td | 1056 def TLBI_VAAS32 : I_5_X_CACHE<0b100010, 0b10010, "tlbi32.vaas">;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrThumb.td | 367 let Inst{9-5} = 0b10010;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepInstrInfo.td | 8904 let Inst{31-27} = 0b10010;
8992 let Inst{31-27} = 0b10010;
9080 let Inst{31-27} = 0b10010;
9180 let Inst{31-27} = 0b10010;
9266 let Inst{31-27} = 0b10010;
9366 let Inst{31-27} = 0b10010;
9452 let Inst{31-27} = 0b10010;
9577 let Inst{31-27} = 0b10010;
9686 let Inst{31-27} = 0b10010;
9811 let Inst{31-27} = 0b10010;
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchInstrInfo.td | 1983 def : Pat<(atomic_fence 5, timm), (DBAR 0b10010)>; // release
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