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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dxilinx-pcie.txt1 * Xilinx AXI PCIe Root Port Bridge DT description
4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
8 - compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
9 - reg: Should contain AXI PCIe registers location and length
10 - device_type: must be "pci"
11 - interrupts: Should contain AXI PCIe interrupt
12 - interrupt-map-mask,
[all …]
H A Dxlnx,axi-pcie-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI PCIe Root Port Bridge
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
17 const: xlnx,axi-pcie-host-1.00.a
20 maxItems: 1
23 maxItems: 1
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H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic PCI host controller
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
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H A Dbrcm,iproc-pcie.txt1 * Broadcom iProc PCIe controller with the platform bus interface
4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
15 - reg: base address and length of the PCIe controller I/O register space
16 - #interrupt-cells: set to <1>
17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
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H A Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Root Port Bridge Host
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
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H A Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pci
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H A Dcdns-pcie-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe Host
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: cdns-pcie.yaml#
17 cdns,max-outbound-regions:
20 minimum: 1
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H A Dti-pci.txt3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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H A Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe interfac
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/freebsd/sys/contrib/device-tree/src/mips/img/
H A Dboston.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/boston-clock.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 stdout-path = "uart0:115200";
23 #address-cells = <1>;
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_pcie.c1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
66 #define AL_PCIE_MIN_MEMORY_BAR_SIZE (1 << 12)
67 #define AL_PCIE_MIN_IO_BAR_SIZE (1 << 8)
72 /** RC - Revisions 1/2 */
77 /** EP - Revisions 1/2 */
82 /** RC - Revision 3 */
87 /** EP - Revision 3 */
96 #define AL_PCIE_PARSE_LANES(v) (((1 << v) - 1) << \
113 al_reg_write32(&pcie_port->regs->port_regs->rd_only_wr_en, in al_pcie_port_wr_to_ro_set()
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/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dapm-xgene.txt1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
11 Second memory resource shall be the host controller
13 Third memory resource shall be the host controller
15 4th memory resource shall be the host controller
16 AXI memory resource.
17 5th optional memory resource shall be the host
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/freebsd/sys/contrib/device-tree/include/dt-bindings/memory/
H A Dtegra186-mc.h117 /* PCIE reads */
119 /* High-definition audio (HDA) reads */
121 /* Host channel data reads */
126 /* Reads from Cortex-A9 4 CPU cores via the L2 cache */
129 /* PCIE writes */
131 /* High-definition audio (HDA) writes */
133 /* Writes from Cortex-A9 4 CPU cores via the L2 cache */
199 /* 3D, ltcx reads instance 1 */
201 /* 3D, ltcx writes instance 1 */
203 /* AXI Switch read client */
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/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
27 next-level-cache = <&l2>;
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/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-binding
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/freebsd/sys/dev/bhnd/
H A Dbhnd_ids.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 1999-2015, Broadcom Corporation
9 * with the dd-wrt project, and the hndsoc.h header distributed with Broadcom's
30 * JEDEC JEP-106 Core Vendor IDs
32 * These are the JEDEC JEP-106 manufacturer ID representions (with ARM's
33 * non-standard 4-bit continutation code), as used in ARM's PrimeCell
38 * will need to convert bus-specific vendor IDs to their BHND_MFGID
39 * JEP-106 equivalents.
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/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A Dmicrochip-mpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
6 #include "microchip-mpfs-fabric.dtsi"
9 #address-cells = <2>;
10 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
21 i-cache-block-size = <64>;
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/freebsd/share/misc/
H A Dpci_vendors5 # Date: 2024-09-20 03:15:02
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-2500TX V3 Ethernet
41 7a09 PCI-to-PCI Bridge
49 7a19 PCI-to-PCI Bridge
53 7a29 PCI-to-PCI Bridge
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/freebsd/sys/arm/nvidia/
H A Dtegra_pcie.c1 /*-
8 * 1. Redistributions of source code must retain the above copyright
29 * Nvidia Integrated PCI/PCI-Express controller driver.
99 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
103 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
104 #define AFI_INTR_MASK_INT_MASK (1 << 0)
108 #define AFI_INTR_CODE_INT_CODE_INI_SLVERR 1
126 #define AFI_SM_INTR_RP_DEASSERT (1 << 14)
127 #define AFI_SM_INTR_RP_ASSERT (1 << 13)
128 #define AFI_SM_INTR_HOTPLUG (1 << 12)
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6sx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gi
1442 pcie: pcie@8ffc000 { global() label
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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/bcm4908/
H A Dbcm4908.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/phy/phy.h>
6 #include <dt-bindings/soc/bcm-pmb.h>
8 /dts-v1/;
11 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
21 stdout-path = "serial0:115200n8";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-binding
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/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
[all...]
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dpci.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
36 ATH10K_PCI_RESET_WARM_ONLY = 1,
43 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
46 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
62 /* PCI-E QCA988X V2 (Ubiquiti branded) */
65 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
66 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
67 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
[all …]
/freebsd/sys/dev/pms/RefTisa/sallsdk/spc/
H A Dsahw.c2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions …
83 * \return -void-
112 if (agNULL != agRoot->sdkData) in saHwReset()
114 saRoot = (agsaLLRoot_t*) agRoot->sdkData; in saHwReset()
115 sysIntsActive = saRoot->sysIntsActive; in saHwReset()
131 if (agNULL != agRoot->sdkData) in saHwReset()
163 fatal_error.regDumpBusBaseNum0 = saRoot->mainConfigTable.regDumpPCIBAR; in saHwReset()
164 fatal_error.regDumpBusBaseNum1 = saRoot->mainConfigTable.regDumpPCIBAR; in saHwReset()
165 fatal_error.regDumpLen0 = saRoot->mainConfigTable.FatalErrorDumpLength0; in saHwReset()
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