1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AmLogic Meson-AXG Clock Controller Driver 4 * 5 * Copyright (c) 2016 Baylibre SAS. 6 * Author: Michael Turquette <mturquette@baylibre.com> 7 * 8 * Copyright (c) 2017 Amlogic, inc. 9 * Author: Qiufang Dai <qiufang.dai@amlogic.com> 10 */ 11 12 #include <linux/clk-provider.h> 13 #include <linux/init.h> 14 #include <linux/platform_device.h> 15 #include <linux/module.h> 16 17 #include "clk-regmap.h" 18 #include "clk-pll.h" 19 #include "clk-mpll.h" 20 #include "meson-clkc-utils.h" 21 22 #include <dt-bindings/clock/axg-clkc.h> 23 24 #define HHI_GP0_PLL_CNTL 0x40 25 #define HHI_GP0_PLL_CNTL2 0x44 26 #define HHI_GP0_PLL_CNTL3 0x48 27 #define HHI_GP0_PLL_CNTL4 0x4c 28 #define HHI_GP0_PLL_CNTL5 0x50 29 #define HHI_GP0_PLL_STS 0x54 30 #define HHI_GP0_PLL_CNTL1 0x58 31 #define HHI_HIFI_PLL_CNTL 0x80 32 #define HHI_HIFI_PLL_CNTL2 0x84 33 #define HHI_HIFI_PLL_CNTL3 0x88 34 #define HHI_HIFI_PLL_CNTL4 0x8C 35 #define HHI_HIFI_PLL_CNTL5 0x90 36 #define HHI_HIFI_PLL_STS 0x94 37 #define HHI_HIFI_PLL_CNTL1 0x98 38 39 #define HHI_XTAL_DIVN_CNTL 0xbc 40 #define HHI_GCLK2_MPEG0 0xc0 41 #define HHI_GCLK2_MPEG1 0xc4 42 #define HHI_GCLK2_MPEG2 0xc8 43 #define HHI_GCLK2_OTHER 0xd0 44 #define HHI_GCLK2_AO 0xd4 45 #define HHI_PCIE_PLL_CNTL 0xd8 46 #define HHI_PCIE_PLL_CNTL1 0xdC 47 #define HHI_PCIE_PLL_CNTL2 0xe0 48 #define HHI_PCIE_PLL_CNTL3 0xe4 49 #define HHI_PCIE_PLL_CNTL4 0xe8 50 #define HHI_PCIE_PLL_CNTL5 0xec 51 #define HHI_PCIE_PLL_CNTL6 0xf0 52 #define HHI_PCIE_PLL_STS 0xf4 53 54 #define HHI_MEM_PD_REG0 0x100 55 #define HHI_VPU_MEM_PD_REG0 0x104 56 #define HHI_VIID_CLK_DIV 0x128 57 #define HHI_VIID_CLK_CNTL 0x12c 58 59 #define HHI_GCLK_MPEG0 0x140 60 #define HHI_GCLK_MPEG1 0x144 61 #define HHI_GCLK_MPEG2 0x148 62 #define HHI_GCLK_OTHER 0x150 63 #define HHI_GCLK_AO 0x154 64 #define HHI_SYS_CPU_CLK_CNTL1 0x15c 65 #define HHI_SYS_CPU_RESET_CNTL 0x160 66 #define HHI_VID_CLK_DIV 0x164 67 #define HHI_SPICC_HCLK_CNTL 0x168 68 69 #define HHI_MPEG_CLK_CNTL 0x174 70 #define HHI_VID_CLK_CNTL 0x17c 71 #define HHI_TS_CLK_CNTL 0x190 72 #define HHI_VID_CLK_CNTL2 0x194 73 #define HHI_SYS_CPU_CLK_CNTL0 0x19c 74 #define HHI_VID_PLL_CLK_DIV 0x1a0 75 #define HHI_VPU_CLK_CNTL 0x1bC 76 77 #define HHI_VAPBCLK_CNTL 0x1F4 78 79 #define HHI_GEN_CLK_CNTL 0x228 80 81 #define HHI_VDIN_MEAS_CLK_CNTL 0x250 82 #define HHI_NAND_CLK_CNTL 0x25C 83 #define HHI_SD_EMMC_CLK_CNTL 0x264 84 85 #define HHI_MPLL_CNTL 0x280 86 #define HHI_MPLL_CNTL2 0x284 87 #define HHI_MPLL_CNTL3 0x288 88 #define HHI_MPLL_CNTL4 0x28C 89 #define HHI_MPLL_CNTL5 0x290 90 #define HHI_MPLL_CNTL6 0x294 91 #define HHI_MPLL_CNTL7 0x298 92 #define HHI_MPLL_CNTL8 0x29C 93 #define HHI_MPLL_CNTL9 0x2A0 94 #define HHI_MPLL_CNTL10 0x2A4 95 96 #define HHI_MPLL3_CNTL0 0x2E0 97 #define HHI_MPLL3_CNTL1 0x2E4 98 #define HHI_PLL_TOP_MISC 0x2E8 99 100 #define HHI_SYS_PLL_CNTL1 0x2FC 101 #define HHI_SYS_PLL_CNTL 0x300 102 #define HHI_SYS_PLL_CNTL2 0x304 103 #define HHI_SYS_PLL_CNTL3 0x308 104 #define HHI_SYS_PLL_CNTL4 0x30c 105 #define HHI_SYS_PLL_CNTL5 0x310 106 #define HHI_SYS_PLL_STS 0x314 107 #define HHI_DPLL_TOP_I 0x318 108 #define HHI_DPLL_TOP2_I 0x31C 109 110 static struct clk_regmap axg_fixed_pll_dco = { 111 .data = &(struct meson_clk_pll_data){ 112 .en = { 113 .reg_off = HHI_MPLL_CNTL, 114 .shift = 30, 115 .width = 1, 116 }, 117 .m = { 118 .reg_off = HHI_MPLL_CNTL, 119 .shift = 0, 120 .width = 9, 121 }, 122 .n = { 123 .reg_off = HHI_MPLL_CNTL, 124 .shift = 9, 125 .width = 5, 126 }, 127 .frac = { 128 .reg_off = HHI_MPLL_CNTL2, 129 .shift = 0, 130 .width = 12, 131 }, 132 .l = { 133 .reg_off = HHI_MPLL_CNTL, 134 .shift = 31, 135 .width = 1, 136 }, 137 .rst = { 138 .reg_off = HHI_MPLL_CNTL, 139 .shift = 29, 140 .width = 1, 141 }, 142 }, 143 .hw.init = &(struct clk_init_data){ 144 .name = "fixed_pll_dco", 145 .ops = &meson_clk_pll_ro_ops, 146 .parent_data = &(const struct clk_parent_data) { 147 .fw_name = "xtal", 148 }, 149 .num_parents = 1, 150 }, 151 }; 152 153 static struct clk_regmap axg_fixed_pll = { 154 .data = &(struct clk_regmap_div_data){ 155 .offset = HHI_MPLL_CNTL, 156 .shift = 16, 157 .width = 2, 158 .flags = CLK_DIVIDER_POWER_OF_TWO, 159 }, 160 .hw.init = &(struct clk_init_data){ 161 .name = "fixed_pll", 162 .ops = &clk_regmap_divider_ro_ops, 163 .parent_hws = (const struct clk_hw *[]) { 164 &axg_fixed_pll_dco.hw 165 }, 166 .num_parents = 1, 167 /* 168 * This clock won't ever change at runtime so 169 * CLK_SET_RATE_PARENT is not required 170 */ 171 }, 172 }; 173 174 static struct clk_regmap axg_sys_pll_dco = { 175 .data = &(struct meson_clk_pll_data){ 176 .en = { 177 .reg_off = HHI_SYS_PLL_CNTL, 178 .shift = 30, 179 .width = 1, 180 }, 181 .m = { 182 .reg_off = HHI_SYS_PLL_CNTL, 183 .shift = 0, 184 .width = 9, 185 }, 186 .n = { 187 .reg_off = HHI_SYS_PLL_CNTL, 188 .shift = 9, 189 .width = 5, 190 }, 191 .l = { 192 .reg_off = HHI_SYS_PLL_CNTL, 193 .shift = 31, 194 .width = 1, 195 }, 196 .rst = { 197 .reg_off = HHI_SYS_PLL_CNTL, 198 .shift = 29, 199 .width = 1, 200 }, 201 }, 202 .hw.init = &(struct clk_init_data){ 203 .name = "sys_pll_dco", 204 .ops = &meson_clk_pll_ro_ops, 205 .parent_data = &(const struct clk_parent_data) { 206 .fw_name = "xtal", 207 }, 208 .num_parents = 1, 209 }, 210 }; 211 212 static struct clk_regmap axg_sys_pll = { 213 .data = &(struct clk_regmap_div_data){ 214 .offset = HHI_SYS_PLL_CNTL, 215 .shift = 16, 216 .width = 2, 217 .flags = CLK_DIVIDER_POWER_OF_TWO, 218 }, 219 .hw.init = &(struct clk_init_data){ 220 .name = "sys_pll", 221 .ops = &clk_regmap_divider_ro_ops, 222 .parent_hws = (const struct clk_hw *[]) { 223 &axg_sys_pll_dco.hw 224 }, 225 .num_parents = 1, 226 .flags = CLK_SET_RATE_PARENT, 227 }, 228 }; 229 230 static const struct pll_params_table axg_gp0_pll_params_table[] = { 231 PLL_PARAMS(40, 1), 232 PLL_PARAMS(41, 1), 233 PLL_PARAMS(42, 1), 234 PLL_PARAMS(43, 1), 235 PLL_PARAMS(44, 1), 236 PLL_PARAMS(45, 1), 237 PLL_PARAMS(46, 1), 238 PLL_PARAMS(47, 1), 239 PLL_PARAMS(48, 1), 240 PLL_PARAMS(49, 1), 241 PLL_PARAMS(50, 1), 242 PLL_PARAMS(51, 1), 243 PLL_PARAMS(52, 1), 244 PLL_PARAMS(53, 1), 245 PLL_PARAMS(54, 1), 246 PLL_PARAMS(55, 1), 247 PLL_PARAMS(56, 1), 248 PLL_PARAMS(57, 1), 249 PLL_PARAMS(58, 1), 250 PLL_PARAMS(59, 1), 251 PLL_PARAMS(60, 1), 252 PLL_PARAMS(61, 1), 253 PLL_PARAMS(62, 1), 254 PLL_PARAMS(63, 1), 255 PLL_PARAMS(64, 1), 256 PLL_PARAMS(65, 1), 257 PLL_PARAMS(66, 1), 258 PLL_PARAMS(67, 1), 259 PLL_PARAMS(68, 1), 260 { /* sentinel */ }, 261 }; 262 263 static const struct reg_sequence axg_gp0_init_regs[] = { 264 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 265 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 266 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 267 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 268 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 269 }; 270 271 static struct clk_regmap axg_gp0_pll_dco = { 272 .data = &(struct meson_clk_pll_data){ 273 .en = { 274 .reg_off = HHI_GP0_PLL_CNTL, 275 .shift = 30, 276 .width = 1, 277 }, 278 .m = { 279 .reg_off = HHI_GP0_PLL_CNTL, 280 .shift = 0, 281 .width = 9, 282 }, 283 .n = { 284 .reg_off = HHI_GP0_PLL_CNTL, 285 .shift = 9, 286 .width = 5, 287 }, 288 .frac = { 289 .reg_off = HHI_GP0_PLL_CNTL1, 290 .shift = 0, 291 .width = 10, 292 }, 293 .l = { 294 .reg_off = HHI_GP0_PLL_CNTL, 295 .shift = 31, 296 .width = 1, 297 }, 298 .rst = { 299 .reg_off = HHI_GP0_PLL_CNTL, 300 .shift = 29, 301 .width = 1, 302 }, 303 .table = axg_gp0_pll_params_table, 304 .init_regs = axg_gp0_init_regs, 305 .init_count = ARRAY_SIZE(axg_gp0_init_regs), 306 }, 307 .hw.init = &(struct clk_init_data){ 308 .name = "gp0_pll_dco", 309 .ops = &meson_clk_pll_ops, 310 .parent_data = &(const struct clk_parent_data) { 311 .fw_name = "xtal", 312 }, 313 .num_parents = 1, 314 }, 315 }; 316 317 static struct clk_regmap axg_gp0_pll = { 318 .data = &(struct clk_regmap_div_data){ 319 .offset = HHI_GP0_PLL_CNTL, 320 .shift = 16, 321 .width = 2, 322 .flags = CLK_DIVIDER_POWER_OF_TWO, 323 }, 324 .hw.init = &(struct clk_init_data){ 325 .name = "gp0_pll", 326 .ops = &clk_regmap_divider_ops, 327 .parent_hws = (const struct clk_hw *[]) { 328 &axg_gp0_pll_dco.hw 329 }, 330 .num_parents = 1, 331 .flags = CLK_SET_RATE_PARENT, 332 }, 333 }; 334 335 static const struct reg_sequence axg_hifi_pll_init_regs[] = { 336 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 }, 337 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be }, 338 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 }, 339 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d }, 340 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 }, 341 }; 342 343 static struct clk_regmap axg_hifi_pll_dco = { 344 .data = &(struct meson_clk_pll_data){ 345 .en = { 346 .reg_off = HHI_HIFI_PLL_CNTL, 347 .shift = 30, 348 .width = 1, 349 }, 350 .m = { 351 .reg_off = HHI_HIFI_PLL_CNTL, 352 .shift = 0, 353 .width = 9, 354 }, 355 .n = { 356 .reg_off = HHI_HIFI_PLL_CNTL, 357 .shift = 9, 358 .width = 5, 359 }, 360 .frac = { 361 .reg_off = HHI_HIFI_PLL_CNTL5, 362 .shift = 0, 363 .width = 13, 364 }, 365 .l = { 366 .reg_off = HHI_HIFI_PLL_CNTL, 367 .shift = 31, 368 .width = 1, 369 }, 370 .rst = { 371 .reg_off = HHI_HIFI_PLL_CNTL, 372 .shift = 29, 373 .width = 1, 374 }, 375 .table = axg_gp0_pll_params_table, 376 .init_regs = axg_hifi_pll_init_regs, 377 .init_count = ARRAY_SIZE(axg_hifi_pll_init_regs), 378 .flags = CLK_MESON_PLL_ROUND_CLOSEST, 379 }, 380 .hw.init = &(struct clk_init_data){ 381 .name = "hifi_pll_dco", 382 .ops = &meson_clk_pll_ops, 383 .parent_data = &(const struct clk_parent_data) { 384 .fw_name = "xtal", 385 }, 386 .num_parents = 1, 387 }, 388 }; 389 390 static struct clk_regmap axg_hifi_pll = { 391 .data = &(struct clk_regmap_div_data){ 392 .offset = HHI_HIFI_PLL_CNTL, 393 .shift = 16, 394 .width = 2, 395 .flags = CLK_DIVIDER_POWER_OF_TWO, 396 }, 397 .hw.init = &(struct clk_init_data){ 398 .name = "hifi_pll", 399 .ops = &clk_regmap_divider_ops, 400 .parent_hws = (const struct clk_hw *[]) { 401 &axg_hifi_pll_dco.hw 402 }, 403 .num_parents = 1, 404 .flags = CLK_SET_RATE_PARENT, 405 }, 406 }; 407 408 static struct clk_fixed_factor axg_fclk_div2_div = { 409 .mult = 1, 410 .div = 2, 411 .hw.init = &(struct clk_init_data){ 412 .name = "fclk_div2_div", 413 .ops = &clk_fixed_factor_ops, 414 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 415 .num_parents = 1, 416 }, 417 }; 418 419 static struct clk_regmap axg_fclk_div2 = { 420 .data = &(struct clk_regmap_gate_data){ 421 .offset = HHI_MPLL_CNTL6, 422 .bit_idx = 27, 423 }, 424 .hw.init = &(struct clk_init_data){ 425 .name = "fclk_div2", 426 .ops = &clk_regmap_gate_ops, 427 .parent_hws = (const struct clk_hw *[]) { 428 &axg_fclk_div2_div.hw 429 }, 430 .num_parents = 1, 431 .flags = CLK_IS_CRITICAL, 432 }, 433 }; 434 435 static struct clk_fixed_factor axg_fclk_div3_div = { 436 .mult = 1, 437 .div = 3, 438 .hw.init = &(struct clk_init_data){ 439 .name = "fclk_div3_div", 440 .ops = &clk_fixed_factor_ops, 441 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 442 .num_parents = 1, 443 }, 444 }; 445 446 static struct clk_regmap axg_fclk_div3 = { 447 .data = &(struct clk_regmap_gate_data){ 448 .offset = HHI_MPLL_CNTL6, 449 .bit_idx = 28, 450 }, 451 .hw.init = &(struct clk_init_data){ 452 .name = "fclk_div3", 453 .ops = &clk_regmap_gate_ops, 454 .parent_hws = (const struct clk_hw *[]) { 455 &axg_fclk_div3_div.hw 456 }, 457 .num_parents = 1, 458 /* 459 * FIXME: 460 * This clock, as fdiv2, is used by the SCPI FW and is required 461 * by the platform to operate correctly. 462 * Until the following condition are met, we need this clock to 463 * be marked as critical: 464 * a) The SCPI generic driver claims and enable all the clocks 465 * it needs 466 * b) CCF has a clock hand-off mechanism to make the sure the 467 * clock stays on until the proper driver comes along 468 */ 469 .flags = CLK_IS_CRITICAL, 470 }, 471 }; 472 473 static struct clk_fixed_factor axg_fclk_div4_div = { 474 .mult = 1, 475 .div = 4, 476 .hw.init = &(struct clk_init_data){ 477 .name = "fclk_div4_div", 478 .ops = &clk_fixed_factor_ops, 479 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 480 .num_parents = 1, 481 }, 482 }; 483 484 static struct clk_regmap axg_fclk_div4 = { 485 .data = &(struct clk_regmap_gate_data){ 486 .offset = HHI_MPLL_CNTL6, 487 .bit_idx = 29, 488 }, 489 .hw.init = &(struct clk_init_data){ 490 .name = "fclk_div4", 491 .ops = &clk_regmap_gate_ops, 492 .parent_hws = (const struct clk_hw *[]) { 493 &axg_fclk_div4_div.hw 494 }, 495 .num_parents = 1, 496 }, 497 }; 498 499 static struct clk_fixed_factor axg_fclk_div5_div = { 500 .mult = 1, 501 .div = 5, 502 .hw.init = &(struct clk_init_data){ 503 .name = "fclk_div5_div", 504 .ops = &clk_fixed_factor_ops, 505 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw }, 506 .num_parents = 1, 507 }, 508 }; 509 510 static struct clk_regmap axg_fclk_div5 = { 511 .data = &(struct clk_regmap_gate_data){ 512 .offset = HHI_MPLL_CNTL6, 513 .bit_idx = 30, 514 }, 515 .hw.init = &(struct clk_init_data){ 516 .name = "fclk_div5", 517 .ops = &clk_regmap_gate_ops, 518 .parent_hws = (const struct clk_hw *[]) { 519 &axg_fclk_div5_div.hw 520 }, 521 .num_parents = 1, 522 }, 523 }; 524 525 static struct clk_fixed_factor axg_fclk_div7_div = { 526 .mult = 1, 527 .div = 7, 528 .hw.init = &(struct clk_init_data){ 529 .name = "fclk_div7_div", 530 .ops = &clk_fixed_factor_ops, 531 .parent_hws = (const struct clk_hw *[]) { 532 &axg_fixed_pll.hw 533 }, 534 .num_parents = 1, 535 }, 536 }; 537 538 static struct clk_regmap axg_fclk_div7 = { 539 .data = &(struct clk_regmap_gate_data){ 540 .offset = HHI_MPLL_CNTL6, 541 .bit_idx = 31, 542 }, 543 .hw.init = &(struct clk_init_data){ 544 .name = "fclk_div7", 545 .ops = &clk_regmap_gate_ops, 546 .parent_hws = (const struct clk_hw *[]) { 547 &axg_fclk_div7_div.hw 548 }, 549 .num_parents = 1, 550 }, 551 }; 552 553 static struct clk_regmap axg_mpll_prediv = { 554 .data = &(struct clk_regmap_div_data){ 555 .offset = HHI_MPLL_CNTL5, 556 .shift = 12, 557 .width = 1, 558 }, 559 .hw.init = &(struct clk_init_data){ 560 .name = "mpll_prediv", 561 .ops = &clk_regmap_divider_ro_ops, 562 .parent_hws = (const struct clk_hw *[]) { 563 &axg_fixed_pll.hw 564 }, 565 .num_parents = 1, 566 }, 567 }; 568 569 static struct clk_regmap axg_mpll0_div = { 570 .data = &(struct meson_clk_mpll_data){ 571 .sdm = { 572 .reg_off = HHI_MPLL_CNTL7, 573 .shift = 0, 574 .width = 14, 575 }, 576 .sdm_en = { 577 .reg_off = HHI_MPLL_CNTL7, 578 .shift = 15, 579 .width = 1, 580 }, 581 .n2 = { 582 .reg_off = HHI_MPLL_CNTL7, 583 .shift = 16, 584 .width = 9, 585 }, 586 .misc = { 587 .reg_off = HHI_PLL_TOP_MISC, 588 .shift = 0, 589 .width = 1, 590 }, 591 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 592 }, 593 .hw.init = &(struct clk_init_data){ 594 .name = "mpll0_div", 595 .ops = &meson_clk_mpll_ops, 596 .parent_hws = (const struct clk_hw *[]) { 597 &axg_mpll_prediv.hw 598 }, 599 .num_parents = 1, 600 }, 601 }; 602 603 static struct clk_regmap axg_mpll0 = { 604 .data = &(struct clk_regmap_gate_data){ 605 .offset = HHI_MPLL_CNTL7, 606 .bit_idx = 14, 607 }, 608 .hw.init = &(struct clk_init_data){ 609 .name = "mpll0", 610 .ops = &clk_regmap_gate_ops, 611 .parent_hws = (const struct clk_hw *[]) { 612 &axg_mpll0_div.hw 613 }, 614 .num_parents = 1, 615 .flags = CLK_SET_RATE_PARENT, 616 }, 617 }; 618 619 static struct clk_regmap axg_mpll1_div = { 620 .data = &(struct meson_clk_mpll_data){ 621 .sdm = { 622 .reg_off = HHI_MPLL_CNTL8, 623 .shift = 0, 624 .width = 14, 625 }, 626 .sdm_en = { 627 .reg_off = HHI_MPLL_CNTL8, 628 .shift = 15, 629 .width = 1, 630 }, 631 .n2 = { 632 .reg_off = HHI_MPLL_CNTL8, 633 .shift = 16, 634 .width = 9, 635 }, 636 .misc = { 637 .reg_off = HHI_PLL_TOP_MISC, 638 .shift = 1, 639 .width = 1, 640 }, 641 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 642 }, 643 .hw.init = &(struct clk_init_data){ 644 .name = "mpll1_div", 645 .ops = &meson_clk_mpll_ops, 646 .parent_hws = (const struct clk_hw *[]) { 647 &axg_mpll_prediv.hw 648 }, 649 .num_parents = 1, 650 }, 651 }; 652 653 static struct clk_regmap axg_mpll1 = { 654 .data = &(struct clk_regmap_gate_data){ 655 .offset = HHI_MPLL_CNTL8, 656 .bit_idx = 14, 657 }, 658 .hw.init = &(struct clk_init_data){ 659 .name = "mpll1", 660 .ops = &clk_regmap_gate_ops, 661 .parent_hws = (const struct clk_hw *[]) { 662 &axg_mpll1_div.hw 663 }, 664 .num_parents = 1, 665 .flags = CLK_SET_RATE_PARENT, 666 }, 667 }; 668 669 static struct clk_regmap axg_mpll2_div = { 670 .data = &(struct meson_clk_mpll_data){ 671 .sdm = { 672 .reg_off = HHI_MPLL_CNTL9, 673 .shift = 0, 674 .width = 14, 675 }, 676 .sdm_en = { 677 .reg_off = HHI_MPLL_CNTL9, 678 .shift = 15, 679 .width = 1, 680 }, 681 .n2 = { 682 .reg_off = HHI_MPLL_CNTL9, 683 .shift = 16, 684 .width = 9, 685 }, 686 .ssen = { 687 .reg_off = HHI_MPLL_CNTL, 688 .shift = 25, 689 .width = 1, 690 }, 691 .misc = { 692 .reg_off = HHI_PLL_TOP_MISC, 693 .shift = 2, 694 .width = 1, 695 }, 696 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 697 }, 698 .hw.init = &(struct clk_init_data){ 699 .name = "mpll2_div", 700 .ops = &meson_clk_mpll_ops, 701 .parent_hws = (const struct clk_hw *[]) { 702 &axg_mpll_prediv.hw 703 }, 704 .num_parents = 1, 705 }, 706 }; 707 708 static struct clk_regmap axg_mpll2 = { 709 .data = &(struct clk_regmap_gate_data){ 710 .offset = HHI_MPLL_CNTL9, 711 .bit_idx = 14, 712 }, 713 .hw.init = &(struct clk_init_data){ 714 .name = "mpll2", 715 .ops = &clk_regmap_gate_ops, 716 .parent_hws = (const struct clk_hw *[]) { 717 &axg_mpll2_div.hw 718 }, 719 .num_parents = 1, 720 .flags = CLK_SET_RATE_PARENT, 721 }, 722 }; 723 724 static struct clk_regmap axg_mpll3_div = { 725 .data = &(struct meson_clk_mpll_data){ 726 .sdm = { 727 .reg_off = HHI_MPLL3_CNTL0, 728 .shift = 12, 729 .width = 14, 730 }, 731 .sdm_en = { 732 .reg_off = HHI_MPLL3_CNTL0, 733 .shift = 11, 734 .width = 1, 735 }, 736 .n2 = { 737 .reg_off = HHI_MPLL3_CNTL0, 738 .shift = 2, 739 .width = 9, 740 }, 741 .misc = { 742 .reg_off = HHI_PLL_TOP_MISC, 743 .shift = 3, 744 .width = 1, 745 }, 746 .flags = CLK_MESON_MPLL_ROUND_CLOSEST, 747 }, 748 .hw.init = &(struct clk_init_data){ 749 .name = "mpll3_div", 750 .ops = &meson_clk_mpll_ops, 751 .parent_hws = (const struct clk_hw *[]) { 752 &axg_mpll_prediv.hw 753 }, 754 .num_parents = 1, 755 }, 756 }; 757 758 static struct clk_regmap axg_mpll3 = { 759 .data = &(struct clk_regmap_gate_data){ 760 .offset = HHI_MPLL3_CNTL0, 761 .bit_idx = 0, 762 }, 763 .hw.init = &(struct clk_init_data){ 764 .name = "mpll3", 765 .ops = &clk_regmap_gate_ops, 766 .parent_hws = (const struct clk_hw *[]) { 767 &axg_mpll3_div.hw 768 }, 769 .num_parents = 1, 770 .flags = CLK_SET_RATE_PARENT, 771 }, 772 }; 773 774 static const struct pll_params_table axg_pcie_pll_params_table[] = { 775 { 776 .m = 200, 777 .n = 3, 778 }, 779 { /* sentinel */ }, 780 }; 781 782 static const struct reg_sequence axg_pcie_pll_init_regs[] = { 783 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa }, 784 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be }, 785 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e }, 786 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d }, 787 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 }, 788 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 }, 789 { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 }, 790 }; 791 792 static struct clk_regmap axg_pcie_pll_dco = { 793 .data = &(struct meson_clk_pll_data){ 794 .en = { 795 .reg_off = HHI_PCIE_PLL_CNTL, 796 .shift = 30, 797 .width = 1, 798 }, 799 .m = { 800 .reg_off = HHI_PCIE_PLL_CNTL, 801 .shift = 0, 802 .width = 9, 803 }, 804 .n = { 805 .reg_off = HHI_PCIE_PLL_CNTL, 806 .shift = 9, 807 .width = 5, 808 }, 809 .frac = { 810 .reg_off = HHI_PCIE_PLL_CNTL1, 811 .shift = 0, 812 .width = 12, 813 }, 814 .l = { 815 .reg_off = HHI_PCIE_PLL_CNTL, 816 .shift = 31, 817 .width = 1, 818 }, 819 .rst = { 820 .reg_off = HHI_PCIE_PLL_CNTL, 821 .shift = 29, 822 .width = 1, 823 }, 824 .table = axg_pcie_pll_params_table, 825 .init_regs = axg_pcie_pll_init_regs, 826 .init_count = ARRAY_SIZE(axg_pcie_pll_init_regs), 827 }, 828 .hw.init = &(struct clk_init_data){ 829 .name = "pcie_pll_dco", 830 .ops = &meson_clk_pll_ops, 831 .parent_data = &(const struct clk_parent_data) { 832 .fw_name = "xtal", 833 }, 834 .num_parents = 1, 835 }, 836 }; 837 838 static struct clk_regmap axg_pcie_pll_od = { 839 .data = &(struct clk_regmap_div_data){ 840 .offset = HHI_PCIE_PLL_CNTL, 841 .shift = 16, 842 .width = 2, 843 .flags = CLK_DIVIDER_POWER_OF_TWO, 844 }, 845 .hw.init = &(struct clk_init_data){ 846 .name = "pcie_pll_od", 847 .ops = &clk_regmap_divider_ops, 848 .parent_hws = (const struct clk_hw *[]) { 849 &axg_pcie_pll_dco.hw 850 }, 851 .num_parents = 1, 852 .flags = CLK_SET_RATE_PARENT, 853 }, 854 }; 855 856 static struct clk_regmap axg_pcie_pll = { 857 .data = &(struct clk_regmap_div_data){ 858 .offset = HHI_PCIE_PLL_CNTL6, 859 .shift = 6, 860 .width = 2, 861 .flags = CLK_DIVIDER_POWER_OF_TWO, 862 }, 863 .hw.init = &(struct clk_init_data){ 864 .name = "pcie_pll", 865 .ops = &clk_regmap_divider_ops, 866 .parent_hws = (const struct clk_hw *[]) { 867 &axg_pcie_pll_od.hw 868 }, 869 .num_parents = 1, 870 .flags = CLK_SET_RATE_PARENT, 871 }, 872 }; 873 874 static struct clk_regmap axg_pcie_mux = { 875 .data = &(struct clk_regmap_mux_data){ 876 .offset = HHI_PCIE_PLL_CNTL6, 877 .mask = 0x1, 878 .shift = 2, 879 /* skip the parent mpll3, reserved for debug */ 880 .table = (u32[]){ 1 }, 881 }, 882 .hw.init = &(struct clk_init_data){ 883 .name = "pcie_mux", 884 .ops = &clk_regmap_mux_ops, 885 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw }, 886 .num_parents = 1, 887 .flags = CLK_SET_RATE_PARENT, 888 }, 889 }; 890 891 static struct clk_regmap axg_pcie_ref = { 892 .data = &(struct clk_regmap_mux_data){ 893 .offset = HHI_PCIE_PLL_CNTL6, 894 .mask = 0x1, 895 .shift = 1, 896 /* skip the parent 0, reserved for debug */ 897 .table = (u32[]){ 1 }, 898 }, 899 .hw.init = &(struct clk_init_data){ 900 .name = "pcie_ref", 901 .ops = &clk_regmap_mux_ops, 902 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw }, 903 .num_parents = 1, 904 .flags = CLK_SET_RATE_PARENT, 905 }, 906 }; 907 908 static struct clk_regmap axg_pcie_cml_en0 = { 909 .data = &(struct clk_regmap_gate_data){ 910 .offset = HHI_PCIE_PLL_CNTL6, 911 .bit_idx = 4, 912 }, 913 .hw.init = &(struct clk_init_data) { 914 .name = "pcie_cml_en0", 915 .ops = &clk_regmap_gate_ops, 916 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw }, 917 .num_parents = 1, 918 .flags = CLK_SET_RATE_PARENT, 919 920 }, 921 }; 922 923 static struct clk_regmap axg_pcie_cml_en1 = { 924 .data = &(struct clk_regmap_gate_data){ 925 .offset = HHI_PCIE_PLL_CNTL6, 926 .bit_idx = 3, 927 }, 928 .hw.init = &(struct clk_init_data) { 929 .name = "pcie_cml_en1", 930 .ops = &clk_regmap_gate_ops, 931 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw }, 932 .num_parents = 1, 933 .flags = CLK_SET_RATE_PARENT, 934 }, 935 }; 936 937 /* clk81 is often referred as "mpeg_clk" */ 938 static u32 clk81_parents_val_table[] = { 0, 2, 3, 4, 5, 6, 7 }; 939 static const struct clk_parent_data clk81_parents[] = { 940 { .fw_name = "xtal", }, 941 { .hw = &axg_fclk_div7.hw }, 942 { .hw = &axg_mpll1.hw }, 943 { .hw = &axg_mpll2.hw }, 944 { .hw = &axg_fclk_div4.hw }, 945 { .hw = &axg_fclk_div3.hw }, 946 { .hw = &axg_fclk_div5.hw }, 947 }; 948 949 static struct clk_regmap axg_clk81_sel = { 950 .data = &(struct clk_regmap_mux_data){ 951 .offset = HHI_MPEG_CLK_CNTL, 952 .mask = 0x7, 953 .shift = 12, 954 .table = clk81_parents_val_table, 955 }, 956 .hw.init = &(struct clk_init_data){ 957 .name = "clk81_sel", 958 .ops = &clk_regmap_mux_ro_ops, 959 .parent_data = clk81_parents, 960 .num_parents = ARRAY_SIZE(clk81_parents), 961 }, 962 }; 963 964 static struct clk_regmap axg_clk81_div = { 965 .data = &(struct clk_regmap_div_data){ 966 .offset = HHI_MPEG_CLK_CNTL, 967 .shift = 0, 968 .width = 7, 969 }, 970 .hw.init = &(struct clk_init_data){ 971 .name = "clk81_div", 972 .ops = &clk_regmap_divider_ops, 973 .parent_hws = (const struct clk_hw *[]) { 974 &axg_clk81_sel.hw 975 }, 976 .num_parents = 1, 977 .flags = CLK_SET_RATE_PARENT, 978 }, 979 }; 980 981 static struct clk_regmap axg_clk81 = { 982 .data = &(struct clk_regmap_gate_data){ 983 .offset = HHI_MPEG_CLK_CNTL, 984 .bit_idx = 7, 985 }, 986 .hw.init = &(struct clk_init_data){ 987 .name = "clk81", 988 .ops = &clk_regmap_gate_ops, 989 .parent_hws = (const struct clk_hw *[]) { 990 &axg_clk81_div.hw 991 }, 992 .num_parents = 1, 993 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 994 }, 995 }; 996 997 static const struct clk_parent_data axg_sd_emmc_clk0_parents[] = { 998 { .fw_name = "xtal", }, 999 { .hw = &axg_fclk_div2.hw }, 1000 { .hw = &axg_fclk_div3.hw }, 1001 { .hw = &axg_fclk_div5.hw }, 1002 { .hw = &axg_fclk_div7.hw }, 1003 /* 1004 * Following these parent clocks, we should also have had mpll2, mpll3 1005 * and gp0_pll but these clocks are too precious to be used here. All 1006 * the necessary rates for MMC and NAND operation can be achieved using 1007 * xtal or fclk_div clocks 1008 */ 1009 }; 1010 1011 /* SDcard clock */ 1012 static struct clk_regmap axg_sd_emmc_b_clk0_sel = { 1013 .data = &(struct clk_regmap_mux_data){ 1014 .offset = HHI_SD_EMMC_CLK_CNTL, 1015 .mask = 0x7, 1016 .shift = 25, 1017 }, 1018 .hw.init = &(struct clk_init_data) { 1019 .name = "sd_emmc_b_clk0_sel", 1020 .ops = &clk_regmap_mux_ops, 1021 .parent_data = axg_sd_emmc_clk0_parents, 1022 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parents), 1023 .flags = CLK_SET_RATE_PARENT, 1024 }, 1025 }; 1026 1027 static struct clk_regmap axg_sd_emmc_b_clk0_div = { 1028 .data = &(struct clk_regmap_div_data){ 1029 .offset = HHI_SD_EMMC_CLK_CNTL, 1030 .shift = 16, 1031 .width = 7, 1032 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1033 }, 1034 .hw.init = &(struct clk_init_data) { 1035 .name = "sd_emmc_b_clk0_div", 1036 .ops = &clk_regmap_divider_ops, 1037 .parent_hws = (const struct clk_hw *[]) { 1038 &axg_sd_emmc_b_clk0_sel.hw 1039 }, 1040 .num_parents = 1, 1041 .flags = CLK_SET_RATE_PARENT, 1042 }, 1043 }; 1044 1045 static struct clk_regmap axg_sd_emmc_b_clk0 = { 1046 .data = &(struct clk_regmap_gate_data){ 1047 .offset = HHI_SD_EMMC_CLK_CNTL, 1048 .bit_idx = 23, 1049 }, 1050 .hw.init = &(struct clk_init_data){ 1051 .name = "sd_emmc_b_clk0", 1052 .ops = &clk_regmap_gate_ops, 1053 .parent_hws = (const struct clk_hw *[]) { 1054 &axg_sd_emmc_b_clk0_div.hw 1055 }, 1056 .num_parents = 1, 1057 .flags = CLK_SET_RATE_PARENT, 1058 }, 1059 }; 1060 1061 /* EMMC/NAND clock */ 1062 static struct clk_regmap axg_sd_emmc_c_clk0_sel = { 1063 .data = &(struct clk_regmap_mux_data){ 1064 .offset = HHI_NAND_CLK_CNTL, 1065 .mask = 0x7, 1066 .shift = 9, 1067 }, 1068 .hw.init = &(struct clk_init_data) { 1069 .name = "sd_emmc_c_clk0_sel", 1070 .ops = &clk_regmap_mux_ops, 1071 .parent_data = axg_sd_emmc_clk0_parents, 1072 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parents), 1073 .flags = CLK_SET_RATE_PARENT, 1074 }, 1075 }; 1076 1077 static struct clk_regmap axg_sd_emmc_c_clk0_div = { 1078 .data = &(struct clk_regmap_div_data){ 1079 .offset = HHI_NAND_CLK_CNTL, 1080 .shift = 0, 1081 .width = 7, 1082 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1083 }, 1084 .hw.init = &(struct clk_init_data) { 1085 .name = "sd_emmc_c_clk0_div", 1086 .ops = &clk_regmap_divider_ops, 1087 .parent_hws = (const struct clk_hw *[]) { 1088 &axg_sd_emmc_c_clk0_sel.hw 1089 }, 1090 .num_parents = 1, 1091 .flags = CLK_SET_RATE_PARENT, 1092 }, 1093 }; 1094 1095 static struct clk_regmap axg_sd_emmc_c_clk0 = { 1096 .data = &(struct clk_regmap_gate_data){ 1097 .offset = HHI_NAND_CLK_CNTL, 1098 .bit_idx = 7, 1099 }, 1100 .hw.init = &(struct clk_init_data){ 1101 .name = "sd_emmc_c_clk0", 1102 .ops = &clk_regmap_gate_ops, 1103 .parent_hws = (const struct clk_hw *[]) { 1104 &axg_sd_emmc_c_clk0_div.hw 1105 }, 1106 .num_parents = 1, 1107 .flags = CLK_SET_RATE_PARENT, 1108 }, 1109 }; 1110 1111 /* VPU Clock */ 1112 1113 static const struct clk_hw *axg_vpu_parents[] = { 1114 &axg_fclk_div4.hw, 1115 &axg_fclk_div3.hw, 1116 &axg_fclk_div5.hw, 1117 &axg_fclk_div7.hw, 1118 }; 1119 1120 static struct clk_regmap axg_vpu_0_sel = { 1121 .data = &(struct clk_regmap_mux_data){ 1122 .offset = HHI_VPU_CLK_CNTL, 1123 .mask = 0x3, 1124 .shift = 9, 1125 }, 1126 .hw.init = &(struct clk_init_data){ 1127 .name = "vpu_0_sel", 1128 .ops = &clk_regmap_mux_ops, 1129 .parent_hws = axg_vpu_parents, 1130 .num_parents = ARRAY_SIZE(axg_vpu_parents), 1131 /* We need a specific parent for VPU clock source, let it be set in DT */ 1132 .flags = CLK_SET_RATE_NO_REPARENT, 1133 }, 1134 }; 1135 1136 static struct clk_regmap axg_vpu_0_div = { 1137 .data = &(struct clk_regmap_div_data){ 1138 .offset = HHI_VPU_CLK_CNTL, 1139 .shift = 0, 1140 .width = 7, 1141 }, 1142 .hw.init = &(struct clk_init_data){ 1143 .name = "vpu_0_div", 1144 .ops = &clk_regmap_divider_ops, 1145 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_sel.hw }, 1146 .num_parents = 1, 1147 .flags = CLK_SET_RATE_PARENT, 1148 }, 1149 }; 1150 1151 static struct clk_regmap axg_vpu_0 = { 1152 .data = &(struct clk_regmap_gate_data){ 1153 .offset = HHI_VPU_CLK_CNTL, 1154 .bit_idx = 8, 1155 }, 1156 .hw.init = &(struct clk_init_data) { 1157 .name = "vpu_0", 1158 .ops = &clk_regmap_gate_ops, 1159 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_div.hw }, 1160 .num_parents = 1, 1161 /* 1162 * We want to avoid CCF to disable the VPU clock if 1163 * display has been set by Bootloader 1164 */ 1165 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1166 }, 1167 }; 1168 1169 static struct clk_regmap axg_vpu_1_sel = { 1170 .data = &(struct clk_regmap_mux_data){ 1171 .offset = HHI_VPU_CLK_CNTL, 1172 .mask = 0x3, 1173 .shift = 25, 1174 }, 1175 .hw.init = &(struct clk_init_data){ 1176 .name = "vpu_1_sel", 1177 .ops = &clk_regmap_mux_ops, 1178 .parent_hws = axg_vpu_parents, 1179 .num_parents = ARRAY_SIZE(axg_vpu_parents), 1180 /* We need a specific parent for VPU clock source, let it be set in DT */ 1181 .flags = CLK_SET_RATE_NO_REPARENT, 1182 }, 1183 }; 1184 1185 static struct clk_regmap axg_vpu_1_div = { 1186 .data = &(struct clk_regmap_div_data){ 1187 .offset = HHI_VPU_CLK_CNTL, 1188 .shift = 16, 1189 .width = 7, 1190 }, 1191 .hw.init = &(struct clk_init_data){ 1192 .name = "vpu_1_div", 1193 .ops = &clk_regmap_divider_ops, 1194 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_sel.hw }, 1195 .num_parents = 1, 1196 .flags = CLK_SET_RATE_PARENT, 1197 }, 1198 }; 1199 1200 static struct clk_regmap axg_vpu_1 = { 1201 .data = &(struct clk_regmap_gate_data){ 1202 .offset = HHI_VPU_CLK_CNTL, 1203 .bit_idx = 24, 1204 }, 1205 .hw.init = &(struct clk_init_data) { 1206 .name = "vpu_1", 1207 .ops = &clk_regmap_gate_ops, 1208 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_div.hw }, 1209 .num_parents = 1, 1210 /* 1211 * We want to avoid CCF to disable the VPU clock if 1212 * display has been set by Bootloader 1213 */ 1214 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1215 }, 1216 }; 1217 1218 static struct clk_regmap axg_vpu = { 1219 .data = &(struct clk_regmap_mux_data){ 1220 .offset = HHI_VPU_CLK_CNTL, 1221 .mask = 1, 1222 .shift = 31, 1223 }, 1224 .hw.init = &(struct clk_init_data){ 1225 .name = "vpu", 1226 .ops = &clk_regmap_mux_ops, 1227 .parent_hws = (const struct clk_hw *[]) { 1228 &axg_vpu_0.hw, 1229 &axg_vpu_1.hw 1230 }, 1231 .num_parents = 2, 1232 .flags = CLK_SET_RATE_NO_REPARENT, 1233 }, 1234 }; 1235 1236 /* VAPB Clock */ 1237 1238 static struct clk_regmap axg_vapb_0_sel = { 1239 .data = &(struct clk_regmap_mux_data){ 1240 .offset = HHI_VAPBCLK_CNTL, 1241 .mask = 0x3, 1242 .shift = 9, 1243 }, 1244 .hw.init = &(struct clk_init_data){ 1245 .name = "vapb_0_sel", 1246 .ops = &clk_regmap_mux_ops, 1247 .parent_hws = axg_vpu_parents, 1248 .num_parents = ARRAY_SIZE(axg_vpu_parents), 1249 .flags = CLK_SET_RATE_NO_REPARENT, 1250 }, 1251 }; 1252 1253 static struct clk_regmap axg_vapb_0_div = { 1254 .data = &(struct clk_regmap_div_data){ 1255 .offset = HHI_VAPBCLK_CNTL, 1256 .shift = 0, 1257 .width = 7, 1258 }, 1259 .hw.init = &(struct clk_init_data){ 1260 .name = "vapb_0_div", 1261 .ops = &clk_regmap_divider_ops, 1262 .parent_hws = (const struct clk_hw *[]) { 1263 &axg_vapb_0_sel.hw 1264 }, 1265 .num_parents = 1, 1266 .flags = CLK_SET_RATE_PARENT, 1267 }, 1268 }; 1269 1270 static struct clk_regmap axg_vapb_0 = { 1271 .data = &(struct clk_regmap_gate_data){ 1272 .offset = HHI_VAPBCLK_CNTL, 1273 .bit_idx = 8, 1274 }, 1275 .hw.init = &(struct clk_init_data) { 1276 .name = "vapb_0", 1277 .ops = &clk_regmap_gate_ops, 1278 .parent_hws = (const struct clk_hw *[]) { 1279 &axg_vapb_0_div.hw 1280 }, 1281 .num_parents = 1, 1282 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1283 }, 1284 }; 1285 1286 static struct clk_regmap axg_vapb_1_sel = { 1287 .data = &(struct clk_regmap_mux_data){ 1288 .offset = HHI_VAPBCLK_CNTL, 1289 .mask = 0x3, 1290 .shift = 25, 1291 }, 1292 .hw.init = &(struct clk_init_data){ 1293 .name = "vapb_1_sel", 1294 .ops = &clk_regmap_mux_ops, 1295 .parent_hws = axg_vpu_parents, 1296 .num_parents = ARRAY_SIZE(axg_vpu_parents), 1297 .flags = CLK_SET_RATE_NO_REPARENT, 1298 }, 1299 }; 1300 1301 static struct clk_regmap axg_vapb_1_div = { 1302 .data = &(struct clk_regmap_div_data){ 1303 .offset = HHI_VAPBCLK_CNTL, 1304 .shift = 16, 1305 .width = 7, 1306 }, 1307 .hw.init = &(struct clk_init_data){ 1308 .name = "vapb_1_div", 1309 .ops = &clk_regmap_divider_ops, 1310 .parent_hws = (const struct clk_hw *[]) { 1311 &axg_vapb_1_sel.hw 1312 }, 1313 .num_parents = 1, 1314 .flags = CLK_SET_RATE_PARENT, 1315 }, 1316 }; 1317 1318 static struct clk_regmap axg_vapb_1 = { 1319 .data = &(struct clk_regmap_gate_data){ 1320 .offset = HHI_VAPBCLK_CNTL, 1321 .bit_idx = 24, 1322 }, 1323 .hw.init = &(struct clk_init_data) { 1324 .name = "vapb_1", 1325 .ops = &clk_regmap_gate_ops, 1326 .parent_hws = (const struct clk_hw *[]) { 1327 &axg_vapb_1_div.hw 1328 }, 1329 .num_parents = 1, 1330 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1331 }, 1332 }; 1333 1334 static struct clk_regmap axg_vapb_sel = { 1335 .data = &(struct clk_regmap_mux_data){ 1336 .offset = HHI_VAPBCLK_CNTL, 1337 .mask = 1, 1338 .shift = 31, 1339 }, 1340 .hw.init = &(struct clk_init_data){ 1341 .name = "vapb_sel", 1342 .ops = &clk_regmap_mux_ops, 1343 .parent_hws = (const struct clk_hw *[]) { 1344 &axg_vapb_0.hw, 1345 &axg_vapb_1.hw 1346 }, 1347 .num_parents = 2, 1348 .flags = CLK_SET_RATE_NO_REPARENT, 1349 }, 1350 }; 1351 1352 static struct clk_regmap axg_vapb = { 1353 .data = &(struct clk_regmap_gate_data){ 1354 .offset = HHI_VAPBCLK_CNTL, 1355 .bit_idx = 30, 1356 }, 1357 .hw.init = &(struct clk_init_data) { 1358 .name = "vapb", 1359 .ops = &clk_regmap_gate_ops, 1360 .parent_hws = (const struct clk_hw *[]) { &axg_vapb_sel.hw }, 1361 .num_parents = 1, 1362 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1363 }, 1364 }; 1365 1366 /* Video Clocks */ 1367 1368 static const struct clk_hw *axg_vclk_parents[] = { 1369 &axg_gp0_pll.hw, 1370 &axg_fclk_div4.hw, 1371 &axg_fclk_div3.hw, 1372 &axg_fclk_div5.hw, 1373 &axg_fclk_div2.hw, 1374 &axg_fclk_div7.hw, 1375 &axg_mpll1.hw, 1376 }; 1377 1378 static struct clk_regmap axg_vclk_sel = { 1379 .data = &(struct clk_regmap_mux_data){ 1380 .offset = HHI_VID_CLK_CNTL, 1381 .mask = 0x7, 1382 .shift = 16, 1383 }, 1384 .hw.init = &(struct clk_init_data){ 1385 .name = "vclk_sel", 1386 .ops = &clk_regmap_mux_ops, 1387 .parent_hws = axg_vclk_parents, 1388 .num_parents = ARRAY_SIZE(axg_vclk_parents), 1389 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1390 }, 1391 }; 1392 1393 static struct clk_regmap axg_vclk2_sel = { 1394 .data = &(struct clk_regmap_mux_data){ 1395 .offset = HHI_VIID_CLK_CNTL, 1396 .mask = 0x7, 1397 .shift = 16, 1398 }, 1399 .hw.init = &(struct clk_init_data){ 1400 .name = "vclk2_sel", 1401 .ops = &clk_regmap_mux_ops, 1402 .parent_hws = axg_vclk_parents, 1403 .num_parents = ARRAY_SIZE(axg_vclk_parents), 1404 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1405 }, 1406 }; 1407 1408 static struct clk_regmap axg_vclk_input = { 1409 .data = &(struct clk_regmap_gate_data){ 1410 .offset = HHI_VID_CLK_DIV, 1411 .bit_idx = 16, 1412 }, 1413 .hw.init = &(struct clk_init_data) { 1414 .name = "vclk_input", 1415 .ops = &clk_regmap_gate_ops, 1416 .parent_hws = (const struct clk_hw *[]) { &axg_vclk_sel.hw }, 1417 .num_parents = 1, 1418 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1419 }, 1420 }; 1421 1422 static struct clk_regmap axg_vclk2_input = { 1423 .data = &(struct clk_regmap_gate_data){ 1424 .offset = HHI_VIID_CLK_DIV, 1425 .bit_idx = 16, 1426 }, 1427 .hw.init = &(struct clk_init_data) { 1428 .name = "vclk2_input", 1429 .ops = &clk_regmap_gate_ops, 1430 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2_sel.hw }, 1431 .num_parents = 1, 1432 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1433 }, 1434 }; 1435 1436 static struct clk_regmap axg_vclk_div = { 1437 .data = &(struct clk_regmap_div_data){ 1438 .offset = HHI_VID_CLK_DIV, 1439 .shift = 0, 1440 .width = 8, 1441 }, 1442 .hw.init = &(struct clk_init_data){ 1443 .name = "vclk_div", 1444 .ops = &clk_regmap_divider_ops, 1445 .parent_hws = (const struct clk_hw *[]) { 1446 &axg_vclk_input.hw 1447 }, 1448 .num_parents = 1, 1449 .flags = CLK_GET_RATE_NOCACHE, 1450 }, 1451 }; 1452 1453 static struct clk_regmap axg_vclk2_div = { 1454 .data = &(struct clk_regmap_div_data){ 1455 .offset = HHI_VIID_CLK_DIV, 1456 .shift = 0, 1457 .width = 8, 1458 }, 1459 .hw.init = &(struct clk_init_data){ 1460 .name = "vclk2_div", 1461 .ops = &clk_regmap_divider_ops, 1462 .parent_hws = (const struct clk_hw *[]) { 1463 &axg_vclk2_input.hw 1464 }, 1465 .num_parents = 1, 1466 .flags = CLK_GET_RATE_NOCACHE, 1467 }, 1468 }; 1469 1470 static struct clk_regmap axg_vclk = { 1471 .data = &(struct clk_regmap_gate_data){ 1472 .offset = HHI_VID_CLK_CNTL, 1473 .bit_idx = 19, 1474 }, 1475 .hw.init = &(struct clk_init_data) { 1476 .name = "vclk", 1477 .ops = &clk_regmap_gate_ops, 1478 .parent_hws = (const struct clk_hw *[]) { &axg_vclk_div.hw }, 1479 .num_parents = 1, 1480 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1481 }, 1482 }; 1483 1484 static struct clk_regmap axg_vclk2 = { 1485 .data = &(struct clk_regmap_gate_data){ 1486 .offset = HHI_VIID_CLK_CNTL, 1487 .bit_idx = 19, 1488 }, 1489 .hw.init = &(struct clk_init_data) { 1490 .name = "vclk2", 1491 .ops = &clk_regmap_gate_ops, 1492 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2_div.hw }, 1493 .num_parents = 1, 1494 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1495 }, 1496 }; 1497 1498 static struct clk_regmap axg_vclk_div1 = { 1499 .data = &(struct clk_regmap_gate_data){ 1500 .offset = HHI_VID_CLK_CNTL, 1501 .bit_idx = 0, 1502 }, 1503 .hw.init = &(struct clk_init_data) { 1504 .name = "vclk_div1", 1505 .ops = &clk_regmap_gate_ops, 1506 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1507 .num_parents = 1, 1508 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1509 }, 1510 }; 1511 1512 static struct clk_regmap axg_vclk_div2_en = { 1513 .data = &(struct clk_regmap_gate_data){ 1514 .offset = HHI_VID_CLK_CNTL, 1515 .bit_idx = 1, 1516 }, 1517 .hw.init = &(struct clk_init_data) { 1518 .name = "vclk_div2_en", 1519 .ops = &clk_regmap_gate_ops, 1520 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1521 .num_parents = 1, 1522 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1523 }, 1524 }; 1525 1526 static struct clk_regmap axg_vclk_div4_en = { 1527 .data = &(struct clk_regmap_gate_data){ 1528 .offset = HHI_VID_CLK_CNTL, 1529 .bit_idx = 2, 1530 }, 1531 .hw.init = &(struct clk_init_data) { 1532 .name = "vclk_div4_en", 1533 .ops = &clk_regmap_gate_ops, 1534 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1535 .num_parents = 1, 1536 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1537 }, 1538 }; 1539 1540 static struct clk_regmap axg_vclk_div6_en = { 1541 .data = &(struct clk_regmap_gate_data){ 1542 .offset = HHI_VID_CLK_CNTL, 1543 .bit_idx = 3, 1544 }, 1545 .hw.init = &(struct clk_init_data) { 1546 .name = "vclk_div6_en", 1547 .ops = &clk_regmap_gate_ops, 1548 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1549 .num_parents = 1, 1550 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1551 }, 1552 }; 1553 1554 static struct clk_regmap axg_vclk_div12_en = { 1555 .data = &(struct clk_regmap_gate_data){ 1556 .offset = HHI_VID_CLK_CNTL, 1557 .bit_idx = 4, 1558 }, 1559 .hw.init = &(struct clk_init_data) { 1560 .name = "vclk_div12_en", 1561 .ops = &clk_regmap_gate_ops, 1562 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw }, 1563 .num_parents = 1, 1564 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1565 }, 1566 }; 1567 1568 static struct clk_regmap axg_vclk2_div1 = { 1569 .data = &(struct clk_regmap_gate_data){ 1570 .offset = HHI_VIID_CLK_CNTL, 1571 .bit_idx = 0, 1572 }, 1573 .hw.init = &(struct clk_init_data) { 1574 .name = "vclk2_div1", 1575 .ops = &clk_regmap_gate_ops, 1576 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1577 .num_parents = 1, 1578 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1579 }, 1580 }; 1581 1582 static struct clk_regmap axg_vclk2_div2_en = { 1583 .data = &(struct clk_regmap_gate_data){ 1584 .offset = HHI_VIID_CLK_CNTL, 1585 .bit_idx = 1, 1586 }, 1587 .hw.init = &(struct clk_init_data) { 1588 .name = "vclk2_div2_en", 1589 .ops = &clk_regmap_gate_ops, 1590 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1591 .num_parents = 1, 1592 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1593 }, 1594 }; 1595 1596 static struct clk_regmap axg_vclk2_div4_en = { 1597 .data = &(struct clk_regmap_gate_data){ 1598 .offset = HHI_VIID_CLK_CNTL, 1599 .bit_idx = 2, 1600 }, 1601 .hw.init = &(struct clk_init_data) { 1602 .name = "vclk2_div4_en", 1603 .ops = &clk_regmap_gate_ops, 1604 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1605 .num_parents = 1, 1606 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1607 }, 1608 }; 1609 1610 static struct clk_regmap axg_vclk2_div6_en = { 1611 .data = &(struct clk_regmap_gate_data){ 1612 .offset = HHI_VIID_CLK_CNTL, 1613 .bit_idx = 3, 1614 }, 1615 .hw.init = &(struct clk_init_data) { 1616 .name = "vclk2_div6_en", 1617 .ops = &clk_regmap_gate_ops, 1618 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1619 .num_parents = 1, 1620 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1621 }, 1622 }; 1623 1624 static struct clk_regmap axg_vclk2_div12_en = { 1625 .data = &(struct clk_regmap_gate_data){ 1626 .offset = HHI_VIID_CLK_CNTL, 1627 .bit_idx = 4, 1628 }, 1629 .hw.init = &(struct clk_init_data) { 1630 .name = "vclk2_div12_en", 1631 .ops = &clk_regmap_gate_ops, 1632 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw }, 1633 .num_parents = 1, 1634 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1635 }, 1636 }; 1637 1638 static struct clk_fixed_factor axg_vclk_div2 = { 1639 .mult = 1, 1640 .div = 2, 1641 .hw.init = &(struct clk_init_data){ 1642 .name = "vclk_div2", 1643 .ops = &clk_fixed_factor_ops, 1644 .parent_hws = (const struct clk_hw *[]) { 1645 &axg_vclk_div2_en.hw 1646 }, 1647 .num_parents = 1, 1648 }, 1649 }; 1650 1651 static struct clk_fixed_factor axg_vclk_div4 = { 1652 .mult = 1, 1653 .div = 4, 1654 .hw.init = &(struct clk_init_data){ 1655 .name = "vclk_div4", 1656 .ops = &clk_fixed_factor_ops, 1657 .parent_hws = (const struct clk_hw *[]) { 1658 &axg_vclk_div4_en.hw 1659 }, 1660 .num_parents = 1, 1661 }, 1662 }; 1663 1664 static struct clk_fixed_factor axg_vclk_div6 = { 1665 .mult = 1, 1666 .div = 6, 1667 .hw.init = &(struct clk_init_data){ 1668 .name = "vclk_div6", 1669 .ops = &clk_fixed_factor_ops, 1670 .parent_hws = (const struct clk_hw *[]) { 1671 &axg_vclk_div6_en.hw 1672 }, 1673 .num_parents = 1, 1674 }, 1675 }; 1676 1677 static struct clk_fixed_factor axg_vclk_div12 = { 1678 .mult = 1, 1679 .div = 12, 1680 .hw.init = &(struct clk_init_data){ 1681 .name = "vclk_div12", 1682 .ops = &clk_fixed_factor_ops, 1683 .parent_hws = (const struct clk_hw *[]) { 1684 &axg_vclk_div12_en.hw 1685 }, 1686 .num_parents = 1, 1687 }, 1688 }; 1689 1690 static struct clk_fixed_factor axg_vclk2_div2 = { 1691 .mult = 1, 1692 .div = 2, 1693 .hw.init = &(struct clk_init_data){ 1694 .name = "vclk2_div2", 1695 .ops = &clk_fixed_factor_ops, 1696 .parent_hws = (const struct clk_hw *[]) { 1697 &axg_vclk2_div2_en.hw 1698 }, 1699 .num_parents = 1, 1700 }, 1701 }; 1702 1703 static struct clk_fixed_factor axg_vclk2_div4 = { 1704 .mult = 1, 1705 .div = 4, 1706 .hw.init = &(struct clk_init_data){ 1707 .name = "vclk2_div4", 1708 .ops = &clk_fixed_factor_ops, 1709 .parent_hws = (const struct clk_hw *[]) { 1710 &axg_vclk2_div4_en.hw 1711 }, 1712 .num_parents = 1, 1713 }, 1714 }; 1715 1716 static struct clk_fixed_factor axg_vclk2_div6 = { 1717 .mult = 1, 1718 .div = 6, 1719 .hw.init = &(struct clk_init_data){ 1720 .name = "vclk2_div6", 1721 .ops = &clk_fixed_factor_ops, 1722 .parent_hws = (const struct clk_hw *[]) { 1723 &axg_vclk2_div6_en.hw 1724 }, 1725 .num_parents = 1, 1726 }, 1727 }; 1728 1729 static struct clk_fixed_factor axg_vclk2_div12 = { 1730 .mult = 1, 1731 .div = 12, 1732 .hw.init = &(struct clk_init_data){ 1733 .name = "vclk2_div12", 1734 .ops = &clk_fixed_factor_ops, 1735 .parent_hws = (const struct clk_hw *[]) { 1736 &axg_vclk2_div12_en.hw 1737 }, 1738 .num_parents = 1, 1739 }, 1740 }; 1741 1742 static u32 axg_cts_encl_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 1743 static const struct clk_hw *axg_cts_encl_parents[] = { 1744 &axg_vclk_div1.hw, 1745 &axg_vclk_div2.hw, 1746 &axg_vclk_div4.hw, 1747 &axg_vclk_div6.hw, 1748 &axg_vclk_div12.hw, 1749 &axg_vclk2_div1.hw, 1750 &axg_vclk2_div2.hw, 1751 &axg_vclk2_div4.hw, 1752 &axg_vclk2_div6.hw, 1753 &axg_vclk2_div12.hw, 1754 }; 1755 1756 static struct clk_regmap axg_cts_encl_sel = { 1757 .data = &(struct clk_regmap_mux_data){ 1758 .offset = HHI_VIID_CLK_DIV, 1759 .mask = 0xf, 1760 .shift = 12, 1761 .table = axg_cts_encl_parents_val_table, 1762 }, 1763 .hw.init = &(struct clk_init_data){ 1764 .name = "cts_encl_sel", 1765 .ops = &clk_regmap_mux_ops, 1766 .parent_hws = axg_cts_encl_parents, 1767 .num_parents = ARRAY_SIZE(axg_cts_encl_parents), 1768 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1769 }, 1770 }; 1771 1772 static struct clk_regmap axg_cts_encl = { 1773 .data = &(struct clk_regmap_gate_data){ 1774 .offset = HHI_VID_CLK_CNTL2, 1775 .bit_idx = 3, 1776 }, 1777 .hw.init = &(struct clk_init_data) { 1778 .name = "cts_encl", 1779 .ops = &clk_regmap_gate_ops, 1780 .parent_hws = (const struct clk_hw *[]) { 1781 &axg_cts_encl_sel.hw 1782 }, 1783 .num_parents = 1, 1784 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1785 }, 1786 }; 1787 1788 /* MIPI DSI Host Clock */ 1789 1790 static u32 axg_vdin_meas_parents_val_table[] = { 0, 1, 2, 3, 6, 7 }; 1791 static const struct clk_parent_data axg_vdin_meas_parents[] = { 1792 { .fw_name = "xtal", }, 1793 { .hw = &axg_fclk_div4.hw }, 1794 { .hw = &axg_fclk_div3.hw }, 1795 { .hw = &axg_fclk_div5.hw }, 1796 { .hw = &axg_fclk_div2.hw }, 1797 { .hw = &axg_fclk_div7.hw }, 1798 }; 1799 1800 static struct clk_regmap axg_vdin_meas_sel = { 1801 .data = &(struct clk_regmap_mux_data){ 1802 .offset = HHI_VDIN_MEAS_CLK_CNTL, 1803 .mask = 0x7, 1804 .shift = 21, 1805 .flags = CLK_MUX_ROUND_CLOSEST, 1806 .table = axg_vdin_meas_parents_val_table, 1807 }, 1808 .hw.init = &(struct clk_init_data){ 1809 .name = "vdin_meas_sel", 1810 .ops = &clk_regmap_mux_ops, 1811 .parent_data = axg_vdin_meas_parents, 1812 .num_parents = ARRAY_SIZE(axg_vdin_meas_parents), 1813 .flags = CLK_SET_RATE_PARENT, 1814 }, 1815 }; 1816 1817 static struct clk_regmap axg_vdin_meas_div = { 1818 .data = &(struct clk_regmap_div_data){ 1819 .offset = HHI_VDIN_MEAS_CLK_CNTL, 1820 .shift = 12, 1821 .width = 7, 1822 }, 1823 .hw.init = &(struct clk_init_data){ 1824 .name = "vdin_meas_div", 1825 .ops = &clk_regmap_divider_ops, 1826 .parent_hws = (const struct clk_hw *[]) { 1827 &axg_vdin_meas_sel.hw }, 1828 .num_parents = 1, 1829 .flags = CLK_SET_RATE_PARENT, 1830 }, 1831 }; 1832 1833 static struct clk_regmap axg_vdin_meas = { 1834 .data = &(struct clk_regmap_gate_data){ 1835 .offset = HHI_VDIN_MEAS_CLK_CNTL, 1836 .bit_idx = 20, 1837 }, 1838 .hw.init = &(struct clk_init_data) { 1839 .name = "vdin_meas", 1840 .ops = &clk_regmap_gate_ops, 1841 .parent_hws = (const struct clk_hw *[]) { 1842 &axg_vdin_meas_div.hw }, 1843 .num_parents = 1, 1844 .flags = CLK_SET_RATE_PARENT, 1845 }, 1846 }; 1847 1848 static u32 gen_clk_parents_val_table[] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, }; 1849 static const struct clk_parent_data gen_clk_parents[] = { 1850 { .fw_name = "xtal", }, 1851 { .hw = &axg_hifi_pll.hw }, 1852 { .hw = &axg_mpll0.hw }, 1853 { .hw = &axg_mpll1.hw }, 1854 { .hw = &axg_mpll2.hw }, 1855 { .hw = &axg_mpll3.hw }, 1856 { .hw = &axg_fclk_div4.hw }, 1857 { .hw = &axg_fclk_div3.hw }, 1858 { .hw = &axg_fclk_div5.hw }, 1859 { .hw = &axg_fclk_div7.hw }, 1860 { .hw = &axg_gp0_pll.hw }, 1861 }; 1862 1863 static struct clk_regmap axg_gen_clk_sel = { 1864 .data = &(struct clk_regmap_mux_data){ 1865 .offset = HHI_GEN_CLK_CNTL, 1866 .mask = 0xf, 1867 .shift = 12, 1868 .table = gen_clk_parents_val_table, 1869 }, 1870 .hw.init = &(struct clk_init_data){ 1871 .name = "gen_clk_sel", 1872 .ops = &clk_regmap_mux_ops, 1873 /* 1874 * bits 15:12 selects from 14 possible parents: 1875 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 1876 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4, 1877 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 1878 */ 1879 .parent_data = gen_clk_parents, 1880 .num_parents = ARRAY_SIZE(gen_clk_parents), 1881 }, 1882 }; 1883 1884 static struct clk_regmap axg_gen_clk_div = { 1885 .data = &(struct clk_regmap_div_data){ 1886 .offset = HHI_GEN_CLK_CNTL, 1887 .shift = 0, 1888 .width = 11, 1889 }, 1890 .hw.init = &(struct clk_init_data){ 1891 .name = "gen_clk_div", 1892 .ops = &clk_regmap_divider_ops, 1893 .parent_hws = (const struct clk_hw *[]) { 1894 &axg_gen_clk_sel.hw 1895 }, 1896 .num_parents = 1, 1897 .flags = CLK_SET_RATE_PARENT, 1898 }, 1899 }; 1900 1901 static struct clk_regmap axg_gen_clk = { 1902 .data = &(struct clk_regmap_gate_data){ 1903 .offset = HHI_GEN_CLK_CNTL, 1904 .bit_idx = 7, 1905 }, 1906 .hw.init = &(struct clk_init_data){ 1907 .name = "gen_clk", 1908 .ops = &clk_regmap_gate_ops, 1909 .parent_hws = (const struct clk_hw *[]) { 1910 &axg_gen_clk_div.hw 1911 }, 1912 .num_parents = 1, 1913 .flags = CLK_SET_RATE_PARENT, 1914 }, 1915 }; 1916 1917 static const struct clk_parent_data axg_pclk_parents = { .hw = &axg_clk81.hw }; 1918 1919 #define AXG_PCLK(_name, _reg, _bit, _flags) \ 1920 MESON_PCLK(axg_##_name, _reg, _bit, &axg_pclk_parents, _flags) 1921 1922 /* 1923 * Everything Else (EE) domain gates 1924 * 1925 * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons 1926 * Users are encouraged to test without it and submit changes to: 1927 * - remove the flag if not necessary 1928 * - replace the flag with something more adequate, such as CLK_IS_CRITICAL, 1929 * if appropriate. 1930 * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable 1931 * for a particular clock. 1932 */ 1933 static AXG_PCLK(ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED); 1934 static AXG_PCLK(audio_locker, HHI_GCLK_MPEG0, 2, CLK_IGNORE_UNUSED); 1935 static AXG_PCLK(mipi_dsi_host, HHI_GCLK_MPEG0, 3, CLK_IGNORE_UNUSED); 1936 static AXG_PCLK(isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED); 1937 static AXG_PCLK(pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED); 1938 static AXG_PCLK(periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED); 1939 static AXG_PCLK(spicc_0, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED); 1940 static AXG_PCLK(i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED); 1941 static AXG_PCLK(rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED); 1942 static AXG_PCLK(uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED); 1943 static AXG_PCLK(mipi_dsi_phy, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED); 1944 static AXG_PCLK(spicc_1, HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED); 1945 static AXG_PCLK(pcie_a, HHI_GCLK_MPEG0, 16, CLK_IGNORE_UNUSED); 1946 static AXG_PCLK(pcie_b, HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED); 1947 static AXG_PCLK(hiu_reg, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED); 1948 static AXG_PCLK(assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED); 1949 static AXG_PCLK(emmc_b, HHI_GCLK_MPEG0, 25, CLK_IGNORE_UNUSED); 1950 static AXG_PCLK(emmc_c, HHI_GCLK_MPEG0, 26, CLK_IGNORE_UNUSED); 1951 static AXG_PCLK(dma, HHI_GCLK_MPEG0, 27, CLK_IGNORE_UNUSED); 1952 static AXG_PCLK(spi, HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED); 1953 1954 static AXG_PCLK(audio, HHI_GCLK_MPEG1, 0, CLK_IGNORE_UNUSED); 1955 static AXG_PCLK(eth_core, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED); 1956 static AXG_PCLK(uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED); 1957 static AXG_PCLK(g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED); 1958 static AXG_PCLK(usb0, HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED); 1959 static AXG_PCLK(usb1, HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED); 1960 static AXG_PCLK(reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED); 1961 static AXG_PCLK(usb_general, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED); 1962 static AXG_PCLK(ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED); 1963 static AXG_PCLK(efuse, HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED); 1964 static AXG_PCLK(boot_rom, HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUSED); 1965 1966 static AXG_PCLK(ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED); 1967 static AXG_PCLK(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED); 1968 static AXG_PCLK(usb1_to_ddr, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUSED); 1969 static AXG_PCLK(usb0_to_ddr, HHI_GCLK_MPEG2, 9, CLK_IGNORE_UNUSED); 1970 static AXG_PCLK(mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED); 1971 static AXG_PCLK(vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED); 1972 static AXG_PCLK(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26, CLK_IGNORE_UNUSED); 1973 static AXG_PCLK(gic, HHI_GCLK_MPEG2, 30, CLK_IGNORE_UNUSED); 1974 1975 /* Always On (AO) domain gates */ 1976 1977 static AXG_PCLK(ao_media_cpu, HHI_GCLK_AO, 0, CLK_IGNORE_UNUSED); 1978 static AXG_PCLK(ao_ahb_sram, HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED); 1979 static AXG_PCLK(ao_ahb_bus, HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED); 1980 static AXG_PCLK(ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED); 1981 static AXG_PCLK(ao_i2c, HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED); 1982 1983 /* Array of all clocks provided by this provider */ 1984 1985 static struct clk_hw *axg_hw_clks[] = { 1986 [CLKID_SYS_PLL] = &axg_sys_pll.hw, 1987 [CLKID_FIXED_PLL] = &axg_fixed_pll.hw, 1988 [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw, 1989 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw, 1990 [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw, 1991 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw, 1992 [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw, 1993 [CLKID_GP0_PLL] = &axg_gp0_pll.hw, 1994 [CLKID_MPEG_SEL] = &axg_clk81_sel.hw, 1995 [CLKID_MPEG_DIV] = &axg_clk81_div.hw, 1996 [CLKID_CLK81] = &axg_clk81.hw, 1997 [CLKID_MPLL0] = &axg_mpll0.hw, 1998 [CLKID_MPLL1] = &axg_mpll1.hw, 1999 [CLKID_MPLL2] = &axg_mpll2.hw, 2000 [CLKID_MPLL3] = &axg_mpll3.hw, 2001 [CLKID_DDR] = &axg_ddr.hw, 2002 [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw, 2003 [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw, 2004 [CLKID_ISA] = &axg_isa.hw, 2005 [CLKID_PL301] = &axg_pl301.hw, 2006 [CLKID_PERIPHS] = &axg_periphs.hw, 2007 [CLKID_SPICC0] = &axg_spicc_0.hw, 2008 [CLKID_I2C] = &axg_i2c.hw, 2009 [CLKID_RNG0] = &axg_rng0.hw, 2010 [CLKID_UART0] = &axg_uart0.hw, 2011 [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw, 2012 [CLKID_SPICC1] = &axg_spicc_1.hw, 2013 [CLKID_PCIE_A] = &axg_pcie_a.hw, 2014 [CLKID_PCIE_B] = &axg_pcie_b.hw, 2015 [CLKID_HIU_IFACE] = &axg_hiu_reg.hw, 2016 [CLKID_ASSIST_MISC] = &axg_assist_misc.hw, 2017 [CLKID_SD_EMMC_B] = &axg_emmc_b.hw, 2018 [CLKID_SD_EMMC_C] = &axg_emmc_c.hw, 2019 [CLKID_DMA] = &axg_dma.hw, 2020 [CLKID_SPI] = &axg_spi.hw, 2021 [CLKID_AUDIO] = &axg_audio.hw, 2022 [CLKID_ETH] = &axg_eth_core.hw, 2023 [CLKID_UART1] = &axg_uart1.hw, 2024 [CLKID_G2D] = &axg_g2d.hw, 2025 [CLKID_USB0] = &axg_usb0.hw, 2026 [CLKID_USB1] = &axg_usb1.hw, 2027 [CLKID_RESET] = &axg_reset.hw, 2028 [CLKID_USB] = &axg_usb_general.hw, 2029 [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw, 2030 [CLKID_EFUSE] = &axg_efuse.hw, 2031 [CLKID_BOOT_ROM] = &axg_boot_rom.hw, 2032 [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw, 2033 [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw, 2034 [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw, 2035 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw, 2036 [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw, 2037 [CLKID_VPU_INTR] = &axg_vpu_intr.hw, 2038 [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw, 2039 [CLKID_GIC] = &axg_gic.hw, 2040 [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw, 2041 [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw, 2042 [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw, 2043 [CLKID_AO_IFACE] = &axg_ao_iface.hw, 2044 [CLKID_AO_I2C] = &axg_ao_i2c.hw, 2045 [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw, 2046 [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw, 2047 [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw, 2048 [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw, 2049 [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw, 2050 [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw, 2051 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw, 2052 [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw, 2053 [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw, 2054 [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw, 2055 [CLKID_HIFI_PLL] = &axg_hifi_pll.hw, 2056 [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw, 2057 [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw, 2058 [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw, 2059 [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw, 2060 [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw, 2061 [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw, 2062 [CLKID_PCIE_PLL] = &axg_pcie_pll.hw, 2063 [CLKID_PCIE_MUX] = &axg_pcie_mux.hw, 2064 [CLKID_PCIE_REF] = &axg_pcie_ref.hw, 2065 [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw, 2066 [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw, 2067 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw, 2068 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw, 2069 [CLKID_GEN_CLK] = &axg_gen_clk.hw, 2070 [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw, 2071 [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw, 2072 [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw, 2073 [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw, 2074 [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw, 2075 [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw, 2076 [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw, 2077 [CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw, 2078 [CLKID_VPU_0] = &axg_vpu_0.hw, 2079 [CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw, 2080 [CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw, 2081 [CLKID_VPU_1] = &axg_vpu_1.hw, 2082 [CLKID_VPU] = &axg_vpu.hw, 2083 [CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw, 2084 [CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw, 2085 [CLKID_VAPB_0] = &axg_vapb_0.hw, 2086 [CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw, 2087 [CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw, 2088 [CLKID_VAPB_1] = &axg_vapb_1.hw, 2089 [CLKID_VAPB_SEL] = &axg_vapb_sel.hw, 2090 [CLKID_VAPB] = &axg_vapb.hw, 2091 [CLKID_VCLK] = &axg_vclk.hw, 2092 [CLKID_VCLK2] = &axg_vclk2.hw, 2093 [CLKID_VCLK_SEL] = &axg_vclk_sel.hw, 2094 [CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw, 2095 [CLKID_VCLK_INPUT] = &axg_vclk_input.hw, 2096 [CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw, 2097 [CLKID_VCLK_DIV] = &axg_vclk_div.hw, 2098 [CLKID_VCLK2_DIV] = &axg_vclk2_div.hw, 2099 [CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw, 2100 [CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw, 2101 [CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw, 2102 [CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw, 2103 [CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw, 2104 [CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw, 2105 [CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw, 2106 [CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw, 2107 [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw, 2108 [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw, 2109 [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw, 2110 [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw, 2111 [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw, 2112 [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw, 2113 [CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw, 2114 [CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw, 2115 [CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw, 2116 [CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw, 2117 [CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw, 2118 [CLKID_CTS_ENCL] = &axg_cts_encl.hw, 2119 [CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw, 2120 [CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw, 2121 [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw, 2122 }; 2123 2124 static const struct meson_clkc_data axg_clkc_data = { 2125 .hw_clks = { 2126 .hws = axg_hw_clks, 2127 .num = ARRAY_SIZE(axg_hw_clks), 2128 }, 2129 }; 2130 2131 static const struct of_device_id axg_clkc_match_table[] = { 2132 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data }, 2133 {} 2134 }; 2135 MODULE_DEVICE_TABLE(of, axg_clkc_match_table); 2136 2137 static struct platform_driver axg_clkc_driver = { 2138 .probe = meson_clkc_syscon_probe, 2139 .driver = { 2140 .name = "axg-clkc", 2141 .of_match_table = axg_clkc_match_table, 2142 }, 2143 }; 2144 module_platform_driver(axg_clkc_driver); 2145 2146 MODULE_DESCRIPTION("Amlogic AXG Main Clock Controller driver"); 2147 MODULE_LICENSE("GPL"); 2148 MODULE_IMPORT_NS("CLK_MESON"); 2149