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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-3 {
8 nvidia,ram-code = <3>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
[all …]
H A Dtegra124-apalis-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include <dt-bindings/clock/tegra124-car.h>
11 emc-timings-1 {
12 nvidia,ram-code = <1>;
14 timing-12750000 {
15 clock-frequency = <12750000>;
16 nvidia,parent-clock-frequency = <408000000>;
18 clock-names = "emc-parent";
21 timing-20400000 {
[all …]
H A Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-1 {
8 nvidia,ram-code = <1>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
[all …]
H A Dtegra30-asus-tf300t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300t-init-hog {
13 gpio-hog;
15 output-low;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
H A Dtegra30-asus-tf300tg.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300tg-init-hog {
13 gpio-hog;
28 output-low;
39 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
47 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
55 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
H A Dtegra30-asus-tf700t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
20 remote-endpoint = <&bridge_input>;
21 bus-width = <24>;
36 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
44 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
52 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
60 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
[all …]
H A Dtegra30-asus-tf201.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
19 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
51 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
57 /* Azurewave AW-NH615 BCM4329B1 */
[all …]
H A Dtegra30-asus-tf300tl.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300tl-init-hog {
13 gpio-hog;
15 output-low;
27 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
H A Dtegra124-nyan-big-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-1 {
8 nvidia,ram-code = <1>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
[all …]
H A Dtegra30-lg-p895.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-lg-x3.dtsi"
11 pinctrl-names = "default";
12 pinctrl-0 = <&state_default>;
15 /* GNSS UART-B pinmux */
16 uartb-cts-rxd {
22 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
24 uartb-rts-txd {
30 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
[all …]
H A Dtegra30-pegatron-chagall.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
11 #include "tegra30-asus-lvds-display.dtsi"
16 chassis-type = "tablet";
35 * pre-existing /chosen node to be available to insert the
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-kernel-mm-mempolicy-weighted-interleave3 Contact: Linux memory management mailing list <linux-mm@kvack.org>
4 Description: Configuration Interface for the Weighted Interleave policy
8 Contact: Linux memory management mailing list <linux-mm@kvack.org>
9 Description: Weight configuration interface for nodeN
24 empty string, ...) will return -EINVAL.
29 What: /sys/kernel/mm/mempolicy/weighted_interleave/auto
31 Contact: Linux memory management mailing list <linux-mm@kvack.org>
32 Description: Auto-weighting configuration interface
34 Configuration mode for weighted interleave. 'true' indicates
35 that the system is in auto mode, and a 'false' indicates that
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Daspeed,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Ryan Chen <ryanchen.aspeed@gmail.com>
19 The two slots are supported by a common configuration area. As the SDHCIs for
20 the slots are dependent on the common configuration area, they are described
26 - aspeed,ast2400-sd-controller
27 - aspeed,ast2500-sd-controller
28 - aspeed,ast2600-sd-controller
[all …]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2400pci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
25 * Default offset is required for RSSI <-> dBm conversion.
153 * CSR11: Back-off control register.
154 * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
155 * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
168 * CSR12: Synchronization configuration register 0.
178 * CSR13: Synchronization configuration register 1.
189 * TSF_COUNT: Enable tsf auto counting.
190 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
[all …]
H A Drt2500pci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
36 * Default offset is required for RSSI <-> dBm conversion.
218 * KICK_DECRYPT: Kick decryption engine, self-clear.
228 * CSR11: Back-off control register.
229 * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
230 * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
245 * CSR12: Synchronization configuration register 0.
255 * CSR13: Synchronization configuration register 1.
266 * TSF_COUNT: Enable tsf auto counting.
[all …]
/linux/Documentation/networking/device_drivers/ethernet/intel/
H A De1000.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999 - 2013 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Speed and Duplex Configuration
16 - Additional Configurations
17 - Support
41 parameters, see the "Speed and Duplex Configuration" section in
50 -------
54 :Valid Range: 0x01-0x0F, 0x20-0x2F
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-rkisp1.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. _v4l2-meta-fmt-rk-isp1-stat-3a:
10 Configuration parameters
13 The configuration of the RkISP1 ISP is performed by userspace by providing
18 configuration format and the `extensible parameters` configuration
21 .. _v4l2-meta-fmt-rk-isp1-params:
23 Fixed parameters configuration format
26 When using the fixed configuration format, parameters are passed to the
31 :c:type:`rkisp1_params_cfg` defined in ``rkisp1-config.h``. So the structure can
34 .. code-block:: c
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_device_sysfs.c1 // SPDX-License-Identifier: MIT
25 * vram_d3cold_threshold - Report/change vram used threshold(in MB) below
28 * lb_fan_control_version - Fan control version provisioned by late binding.
31 * lb_voltage_regulator_version - Voltage regulator version provisioned by late
44 ret = sysfs_emit(buf, "%d\n", xe->d3cold.vram_threshold); in vram_d3cold_threshold_show()
63 drm_dbg(&xe->drm, "vram_d3cold_threshold: %u\n", vram_d3cold_threshold); in vram_d3cold_threshold_store()
186 return attr->mode; in late_bind_attr_is_visible()
189 return attr->mode; in late_bind_attr_is_visible()
202 * Default link speed of discrete GPUs is determined by configuration parameters
206 * to host or motherboard limitations and may have to auto-downgrade their link
[all …]
/linux/drivers/net/phy/
H A Dphy-c45.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include "mdio-open-alliance.h"
12 #include "phylib-internal.h"
15 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
22 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
27 phydev->pma_extable = val; in genphy_c45_baset1_able()
30 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
34 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
49 * genphy_c45_pma_resume - wakes up the PMA module
55 return -EOPNOTSUPP; in genphy_c45_pma_resume()
[all …]
/linux/Documentation/sound/hd-audio/
H A Dcontrols.rst2 HD-Audio Codec-Specific Mixer Controls
6 This file explains the codec-specific mixer controls.
9 --------------
12 This is an enum control to change the surround-channel setup,
15 and "8ch". According to the configuration, this also controls the
16 jack-retasking of multi-I/O jacks.
18 Auto-Mute Mode
19 This is an enum control to change the auto-mute behavior of the
20 headphone and line-out jacks. If built-in speakers and headphone
21 and/or line-out jacks are available on a machine, this controls
[all …]
/linux/Documentation/networking/
H A Dnetconsole.rst1 .. SPDX-License-Identifier: GPL-2.0
28 It can be used either built-in or as a module. As a built-in,
34 Sender and receiver configuration:
37 It takes a string configuration parameter "netconsole" in the
40 netconsole=[+][r][src-port]@[src-ip]/[<dev>],[tgt-port]@<tgt-ip>/[tgt-macaddr]
45 src-port source for UDP packets (defaults to 6665)
46 src-ip source IP to use (interface address)
48 tgt-port port for logging agent (6666)
49 tgt-ip IP address for logging agent
50 tgt-macaddr ethernet MAC address for logging agent (broadcast)
[all …]
/linux/drivers/net/ethernet/cirrus/
H A Dcs89x0.h1 /* Copyright, 1988-1992, Russell Nelson, Crynwr Software
18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
19 /* offset 2h -> Model/Product Number */
20 /* offset 3h -> Chip Revision Number */
45 #define PP_BufCFG 0x010A /* Bus configuration Register */
50 #define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */
62 #define PP_AutoNegST 0x013E /* Auto Neg Status */
131 /* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */
142 /* PP_RxCTL - Receive Control bit definition - Read/write */
153 /* Default receive mode - individually addressed, broadcast, and error free */
[all …]
/linux/drivers/net/ethernet/intel/e1000e/
H A Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
9 * e1000e_get_bus_info_pcie - Get PCIe bus information
18 struct pci_dev *pdev = hw->adapter->pdev; in e1000e_get_bus_info_pcie()
19 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie()
20 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
24 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
27 bus->width = (enum e1000_bus_width)FIELD_GET(PCI_EXP_LNKSTA_NLW, in e1000e_get_bus_info_pcie()
31 mac->ops.set_lan_id(hw); in e1000e_get_bus_info_pcie()
37 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
26 - description: external memory clock
28 clock-names:
[all …]

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