| /freebsd/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | armada-xp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada XP family SoC
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 * Contains definitions specific to the Armada XP SoC that are not
13 * common to all Armada SoCs.
16 #include "armada-370-xp.dtsi"
19 #address-cells = <2>;
20 #size-cells = <2>;
22 model = "Marvell Armada XP family SoC";
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| H A D | armada-xp-98dx3236.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * common to all Armada XP SoCs.
11 #include "armada-370-xp.dtsi"
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,98dx3236-smp";
31 cpu@0 {
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| H A D | armada-xp-mv78460.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada XP family SoC
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Contains definitions specific to the Armada XP MV78460 SoC that are not
10 * common to all Armada XP SoCs.
13 #include "armada-xp.dtsi"
16 model = "Marvell Armada XP MV78460 SoC";
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
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| H A D | armada-xp-mv78230.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada XP family SoC
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Contains definitions specific to the Armada XP MV78230 SoC that are not
10 * common to all Armada XP SoCs.
13 #include "armada-xp.dtsi"
16 model = "Marvell Armada XP MV78230 SoC";
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
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| H A D | armada-xp-98dx3336.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * common to all Armada XP SoCs.
11 #include "armada-xp-98dx3236.dtsi"
15 compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
18 cpu@1 {
19 device_type = "cpu";
20 compatible = "marvell,sheeva-v7";
23 clock-latency = <1000000>;
28 internal-regs {
30 compatible = "marvell,98dx3336-resume-ctrl";
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| H A D | armada-370-xp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 * This file contains the definitions that are common to the Armada
13 * 370 and Armada XP SoC.
19 model = "Marvell Armada 370 and XP SoC";
20 compatible = "marvell,armada-370-xp";
28 #address-cells = <1>;
29 #size-cells = <0>;
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| H A D | armada-xp-98dx4251.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * common to all Armada XP SoCs.
11 #include "armada-xp-98dx3236.dtsi"
15 compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
18 cpu@1 {
19 device_type = "cpu";
20 compatible = "marvell,sheeva-v7";
23 clock-latency = <1000000>;
28 internal-regs {
30 compatible = "marvell,98dx3336-resume-ctrl";
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| H A D | armada-370.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 370 family SoC
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * Contains definitions specific to the Armada 370 SoC that are not
12 * common to all Armada SoCs.
15 #include "armada-370-xp.dtsi"
18 #address-cells = <1>;
19 #size-cells = <1>;
21 model = "Marvell Armada 370 family SoC";
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| H A D | armada-xp-mv78260.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada XP family SoC
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Contains definitions specific to the Armada XP MV78260 SoC that are not
10 * common to all Armada XP SoCs.
13 #include "armada-xp.dtsi"
16 model = "Marvell Armada XP MV78260 SoC";
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
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| H A D | armada-39x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 39x family of SoCs.
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
18 model = "Marvell Armada 39x family SoC";
31 #address-cells = <1>;
32 #size-cells = <0>;
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| H A D | armada-38x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 38x family of SoCs.
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
21 model = "Marvell Armada 38x family SoC";
32 compatible = "arm,cortex-a9-pmu";
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| H A D | armada-370-db.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for Marvell Armada 370 evaluation board
4 * (DB-88F6710-BP-DDR3)
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
22 /dts-v1/;
23 #include "armada-370.dtsi"
26 model = "Marvell Armada 370 Evaluation Board";
27 compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
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| H A D | armada-370-c200-v2.dts | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Device Tree file for Ctera C200-V2
8 /dts-v1/;
10 #include "armada-370.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/leds/common.h>
18 compatible = "ctera,c200-v2", "marvell,armada370", "marvell,armada-370-xp";
22 stdout-path = "serial0:115200n8";
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | mvebu-core-clock.txt | 1 * Core Clock bindings for Marvell MVEBU SoCs
3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
7 The following is a list of provided IDs and clock names on Armada 370/XP:
8 0 = tclk (Internal Bus clock)
9 1 = cpuclk (CPU clock)
10 2 = nbclk (L2 Cache clock)
11 3 = hclk (DRAM control clock)
12 4 = dramclk (DDR clock)
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| H A D | mvebu-cpu-clock.txt | 1 Device Tree Clock bindings for cpu clock of Marvell EBU platforms
4 - compatible : shall be one of the following:
5 "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
6 "marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
7 - reg : Address and length of the clock complex register set, followed
9 - #clock-cells : should be set to 1.
10 - clocks : shall be the input parent clock phandle for the clock.
12 cpuclk: clock-complex@d0018700 {
13 #clock-cells = <1>;
14 compatible = "marvell,armada-xp-cpu-clock";
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-mvebu.txt | 5 - compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",
6 "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".
8 "marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,
9 Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"
12 "marvel,armadaxp-gpio" should be used for all Armada XP SoCs
15 "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
17 Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt
20 - reg: Address and length of the register set for the device. Only one
21 entry is expected, except for the "marvell,armadaxp-gpio" variant
23 one for the per-cpu registers. Not used for marvell,armada-8k-gpio.
[all …]
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| /freebsd/sys/arm64/conf/ |
| H A D | NOTES | 2 # NOTES -- Lines that can be cut/pasted into kernel and hints configs.
23 cpu ARM64
25 makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
30 options VFP # Floating-point support
64 device qcom_gcc # Global Clock Controller
69 # Microsoft Hyper-V
72 # CPU frequency control
80 device al_pci # Annapurna Alpine PCI-E
81 options PCI_HP # PCI-Express native HotPlug
82 options PCI_IOV # PCI SR-IOV support
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
34 cpus and cpu node bindings definition
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | mvebu-pci.txt | 5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
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| /freebsd/sys/dts/arm/ |
| H A D | db78460.dts | 3 * Copyright (c) 2010-2011 Semihalf
27 * Marvell DB-78460 Device Tree Source.
30 /dts-v1/;
33 model = "mrvl,DB-78460";
34 #address-cells = <1>;
35 #size-cells = <1>;
42 #address-cells = <1>;
43 #size-cells = <0>;
45 cpu@0 {
46 device_type = "cpu";
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| /freebsd/share/misc/ |
| H A D | pci_vendors | 5 # Date: 2025-07-11 03:15:02
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-2500TX V3 Ethernet
41 7a09 PCI-to-PCI Bridge
51 7a19 PCI-to-PCI Bridge
57 7a29 PCI-to-PCI Bridge
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