1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Sam Shih <sam.shih@mediatek.com> 5 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com> 6 * Author: Jianhui Zhao <zhaojh329@gmail.com> 7 */ 8 9 10 #include <linux/clk-provider.h> 11 #include <linux/platform_device.h> 12 #include "clk-mtk.h" 13 #include "clk-gate.h" 14 #include "clk-mux.h" 15 16 #include <dt-bindings/clock/mediatek,mt7981-clk.h> 17 #include <linux/clk.h> 18 19 static DEFINE_SPINLOCK(mt7981_clk_lock); 20 21 static const struct mtk_fixed_factor top_divs[] = { 22 FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1), 23 FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1), 24 FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2), 25 FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3), 26 FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2), 27 FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4), 28 FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8), 29 FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16), 30 FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1), 31 FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2), 32 FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3), 33 FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15), 34 FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4), 35 FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6), 36 FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12), 37 FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8), 38 FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1), 39 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), 40 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), 41 FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1), 42 FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4), 43 FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5), 44 FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10), 45 FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20), 46 FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8), 47 FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16), 48 FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32), 49 FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1), 50 FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2), 51 FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4), 52 FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8), 53 FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16), 54 FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6), 55 FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1), 56 FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1), 57 FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2), 58 FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250), 59 FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220), 60 FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1), 61 FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1), 62 FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1), 63 FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1), 64 FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1), 65 FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1), 66 FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1), 67 FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1), 68 FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1), 69 FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1), 70 FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1), 71 FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1), 72 FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1), 73 FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1), 74 FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1), 75 FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1), 76 FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1), 77 FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1), 78 FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1), 79 FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1), 80 FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1), 81 FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1), 82 FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1), 83 FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1), 84 FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1), 85 FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1), 86 FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1), 87 FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1), 88 FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1), 89 FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1), 90 FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1), 91 FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1), 92 FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1), 93 FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1), 94 FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1), 95 FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1), 96 FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1), 97 FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1), 98 }; 99 100 static const char * const nfi1x_parents[] __initconst = { 101 "cb_cksq_40m", 102 "cb_mm_d4", 103 "net1_d8_d2", 104 "cb_net2_d6", 105 "cb_m_d4", 106 "cb_mm_d8", 107 "net1_d8_d4", 108 "cb_m_d8" 109 }; 110 111 static const char * const spinfi_parents[] __initconst = { 112 "cksq_40m_d2", 113 "cb_cksq_40m", 114 "net1_d5_d4", 115 "cb_m_d4", 116 "cb_mm_d8", 117 "net1_d8_d4", 118 "mm_d6_d2", 119 "cb_m_d8" 120 }; 121 122 static const char * const spi_parents[] __initconst = { 123 "cb_cksq_40m", 124 "cb_m_d2", 125 "cb_mm_d4", 126 "net1_d8_d2", 127 "cb_net2_d6", 128 "net1_d5_d4", 129 "cb_m_d4", 130 "net1_d8_d4" 131 }; 132 133 static const char * const uart_parents[] __initconst = { 134 "cb_cksq_40m", 135 "cb_m_d8", 136 "m_d8_d2" 137 }; 138 139 static const char * const pwm_parents[] __initconst = { 140 "cb_cksq_40m", 141 "net1_d8_d2", 142 "net1_d5_d4", 143 "cb_m_d4", 144 "m_d8_d2", 145 "cb_rtc_32k" 146 }; 147 148 static const char * const i2c_parents[] __initconst = { 149 "cb_cksq_40m", 150 "net1_d5_d4", 151 "cb_m_d4", 152 "net1_d8_d4" 153 }; 154 155 static const char * const pextp_tl_ck_parents[] __initconst = { 156 "cb_cksq_40m", 157 "net1_d5_d4", 158 "cb_m_d4", 159 "cb_rtc_32k" 160 }; 161 162 static const char * const emmc_208m_parents[] __initconst = { 163 "cb_cksq_40m", 164 "cb_m_d2", 165 "cb_net2_d4", 166 "cb_apll2_196m", 167 "cb_mm_d4", 168 "net1_d8_d2", 169 "cb_mm_d6" 170 }; 171 172 static const char * const emmc_400m_parents[] __initconst = { 173 "cb_cksq_40m", 174 "cb_net2_d2", 175 "cb_mm_d2", 176 "cb_net2_d2" 177 }; 178 179 static const char * const csw_f26m_parents[] __initconst = { 180 "cksq_40m_d2", 181 "m_d8_d2" 182 }; 183 184 static const char * const dramc_md32_parents[] __initconst = { 185 "cb_cksq_40m", 186 "cb_m_d2", 187 "cb_wedmcu_208m" 188 }; 189 190 static const char * const sysaxi_parents[] __initconst = { 191 "cb_cksq_40m", 192 "net1_d8_d2" 193 }; 194 195 static const char * const sysapb_parents[] __initconst = { 196 "cb_cksq_40m", 197 "m_d3_d2" 198 }; 199 200 static const char * const arm_db_main_parents[] __initconst = { 201 "cb_cksq_40m", 202 "cb_net2_d6" 203 }; 204 205 static const char * const ap2cnn_host_parents[] __initconst = { 206 "cb_cksq_40m", 207 "net1_d8_d4" 208 }; 209 210 static const char * const netsys_parents[] __initconst = { 211 "cb_cksq_40m", 212 "cb_mm_d2" 213 }; 214 215 static const char * const netsys_500m_parents[] __initconst = { 216 "cb_cksq_40m", 217 "cb_net1_d5" 218 }; 219 220 static const char * const netsys_mcu_parents[] __initconst = { 221 "cb_cksq_40m", 222 "cb_mm_720m", 223 "cb_net1_d4", 224 "cb_net1_d5", 225 "cb_m_416m" 226 }; 227 228 static const char * const netsys_2x_parents[] __initconst = { 229 "cb_cksq_40m", 230 "cb_net2_800m", 231 "cb_mm_720m" 232 }; 233 234 static const char * const sgm_325m_parents[] __initconst = { 235 "cb_cksq_40m", 236 "cb_sgm_325m" 237 }; 238 239 static const char * const sgm_reg_parents[] __initconst = { 240 "cb_cksq_40m", 241 "cb_net2_d4" 242 }; 243 244 static const char * const eip97b_parents[] __initconst = { 245 "cb_cksq_40m", 246 "cb_net1_d5", 247 "cb_m_416m", 248 "cb_mm_d2", 249 "net1_d5_d2" 250 }; 251 252 static const char * const aud_parents[] __initconst = { 253 "cb_cksq_40m", 254 "cb_apll2_196m" 255 }; 256 257 static const char * const a1sys_parents[] __initconst = { 258 "cb_cksq_40m", 259 "apll2_d4" 260 }; 261 262 static const char * const aud_l_parents[] __initconst = { 263 "cb_cksq_40m", 264 "cb_apll2_196m", 265 "m_d8_d2" 266 }; 267 268 static const char * const a_tuner_parents[] __initconst = { 269 "cb_cksq_40m", 270 "apll2_d4", 271 "m_d8_d2" 272 }; 273 274 static const char * const u2u3_parents[] __initconst = { 275 "cb_cksq_40m", 276 "m_d8_d2" 277 }; 278 279 static const char * const u2u3_sys_parents[] __initconst = { 280 "cb_cksq_40m", 281 "net1_d5_d4" 282 }; 283 284 static const char * const usb_frmcnt_parents[] __initconst = { 285 "cb_cksq_40m", 286 "cb_mm_d3_d5" 287 }; 288 289 static const struct mtk_mux top_muxes[] = { 290 /* CLK_CFG_0 */ 291 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 292 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), 293 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 294 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), 295 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 296 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2), 297 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 298 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), 299 /* CLK_CFG_1 */ 300 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 301 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4), 302 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 303 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5), 304 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 305 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), 306 MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", 307 pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31, 308 0x1C0, 7), 309 /* CLK_CFG_2 */ 310 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", 311 emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7, 312 0x1C0, 8, 0), 313 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", 314 emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15, 315 0x1C0, 9, 0), 316 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", 317 csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23, 318 0x1C0, 10, 319 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 320 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", 321 csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1, 322 31, 0x1C0, 11, 323 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 324 /* CLK_CFG_3 */ 325 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", 326 dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2, 327 7, 0x1C0, 12, 328 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 329 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", 330 sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15, 331 0x1C0, 13, 332 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 333 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", 334 sysapb_parents, 0x030, 0x034, 0x038, 16, 1, 335 23, 0x1C0, 14, 336 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 337 MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", 338 arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31, 339 0x1C0, 15), 340 /* CLK_CFG_4 */ 341 MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", 342 ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7, 343 0x1C0, 16), 344 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 345 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), 346 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", 347 netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 348 0x1C0, 18), 349 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", 350 netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, 351 0x1C0, 19), 352 /* CLK_CFG_5 */ 353 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", 354 netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, 355 0x1C0, 20), 356 MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", 357 sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, 358 0x1C0, 21), 359 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 360 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22, 361 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 362 MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 363 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23), 364 /* CLK_CFG_6 */ 365 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", 366 csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1, 367 7, 0x1C0, 24), 368 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060, 369 0x064, 0x068, 8, 1, 15, 0x1C0, 25), 370 MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 371 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), 372 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 373 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27), 374 /* CLK_CFG_7 */ 375 MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", 376 a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7, 377 0x1C0, 28), 378 MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070, 379 0x074, 0x078, 8, 1, 15, 0x1C0, 29), 380 MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", 381 u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23, 382 0x1C0, 30), 383 MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", 384 u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31, 385 0x1C4, 0), 386 /* CLK_CFG_8 */ 387 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", 388 usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7, 389 0x1C4, 1), 390 }; 391 392 static struct mtk_composite top_aud_divs[] = { 393 DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud", 394 0x0420, 0, 0x0420, 8, 8), 395 }; 396 397 static const struct mtk_clk_desc topck_desc = { 398 .factor_clks = top_divs, 399 .num_factor_clks = ARRAY_SIZE(top_divs), 400 .mux_clks = top_muxes, 401 .num_mux_clks = ARRAY_SIZE(top_muxes), 402 .composite_clks = top_aud_divs, 403 .num_composite_clks = ARRAY_SIZE(top_aud_divs), 404 .clk_lock = &mt7981_clk_lock, 405 }; 406 407 static const struct of_device_id of_match_clk_mt7981_topckgen[] = { 408 { .compatible = "mediatek,mt7981-topckgen", .data = &topck_desc }, 409 { /* sentinel */ } 410 }; 411 MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_topckgen); 412 413 static struct platform_driver clk_mt7981_topckgen_drv = { 414 .probe = mtk_clk_simple_probe, 415 .remove = mtk_clk_simple_remove, 416 .driver = { 417 .name = "clk-mt7981-topckgen", 418 .of_match_table = of_match_clk_mt7981_topckgen, 419 }, 420 }; 421 module_platform_driver(clk_mt7981_topckgen_drv); 422 423 MODULE_DESCRIPTION("MediaTek MT7981 top clock generators driver"); 424 MODULE_LICENSE("GPL"); 425