Searched +full:ar9132 +full:- +full:ddr +full:- +full:controller (Results 1 – 1 of 1) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/interrupt-controller/qca,ar7100-cpu-intc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Qualcomm Atheros ath79 CPU interrupt controller10 - Alban Bedel <albeu@free.fr>13 On most SoC the IRQ controller need to flush the DDR FIFO before running the15 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.20 - items:21 - const: qca,ar9132-cpu-intc[all …]