Lines Matching +full:ar9132 +full:- +full:ddr +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/qca,ar7100-cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros ath79 CPU interrupt controller
10 - Alban Bedel <albeu@free.fr>
13 On most SoC the IRQ controller need to flush the DDR FIFO before running the
15 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
20 - items:
21 - const: qca,ar9132-cpu-intc
22 - const: qca,ar7100-cpu-intc
23 - items:
24 - const: qca,ar7100-cpu-intc
26 interrupt-controller: true
28 '#interrupt-cells':
31 qca,ddr-wb-channel-interrupts:
33 $ref: /schemas/types.yaml#/definitions/uint32-array
35 qca,ddr-wb-channels:
37 $ref: /schemas/types.yaml#/definitions/phandle-array
40 - compatible
41 - interrupt-controller
42 - '#interrupt-cells'
47 - |
48 interrupt-controller {
49 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
51 interrupt-controller;
52 #interrupt-cells = <1>;
54 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
55 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
59 ddr_ctrl: memory-controller {
60 #qca,ddr-wb-channel-cells = <1>;