Searched full:adec (Results 1 – 3 of 3) sorted by relevance
102 /* Row and column bit positions in the address decoder (ADEC) registers. */146 * @adec: Address decode registers.159 u32 adec[ADEC_MAX]; member166 * Address decoder (ADEC) registers to match the order in which the register266 * @error_data: the DDRMC5 ADEC address decoder register data389 high_mem_base = (priv->adec[ADEC2 + offset] & MC5_MEM_MASK) * MC5_HIMEM_BASE; in convert_to_physical()390 interleave = priv->adec[ADEC13 + offset] & MC5_INTERLEAVE_SEL; in convert_to_physical()392 high_mem_offset = priv->adec[ADEC3 + offset] & MC5_MEM_MASK; in convert_to_physical()393 low_mem_offset = priv->adec[ADEC1 + offset] & MC5_MEM_MASK; in convert_to_physical()394 reg = priv->adec[ADEC14 + offset]; in convert_to_physical()[all …]
770 * writes to the ADEC registers based on the address given by the user.776 * match ADEC bit to generate errors at the particular address. ADEC14834 * writes to the ADEC registers based on the address given by the user.838 * are written to the match ADEC bit to generate errors at the
1100 dc.l $00003ffe,$0000cd00,$0549adec,$71590000