100 /* Row and column bit positions in the address decoder (ADEC) registers. */
144  * @adec:		Address decode registers.
157 	u32 adec[ADEC_MAX];  member
164  * Address decoder (ADEC) registers to match the order in which the register
264  * @error_data:	the DDRMC5 ADEC address decoder register data
387 	high_mem_base = (priv->adec[ADEC2 + offset] & MC5_MEM_MASK) * MC5_HIMEM_BASE;  in convert_to_physical()
388 	interleave = priv->adec[ADEC13 + offset] & MC5_INTERLEAVE_SEL;  in convert_to_physical()
390 	high_mem_offset = priv->adec[ADEC3 + offset] & MC5_MEM_MASK;  in convert_to_physical()
391 	low_mem_offset = priv->adec[ADEC1 + offset] & MC5_MEM_MASK;  in convert_to_physical()
392 	reg = priv->adec[ADEC14 + offset];  in convert_to_physical()
410 	if ((priv->adec[ADEC2 + offset] & MC5_HIGH_MEM_EN) && err_addr >= high_mem_base)  in convert_to_physical()
423  * @error_data:	the MC5 ADEC address decoder register data
577 		get_ddr_config(i, &mc_priv->adec[ADEC_NUM * i], amd_mcdi);  in setup_mcdi()
647 				adec_data = mc_priv->adec + ADEC_NUM * i;  in rpmsg_cb()
658 				adec_data = mc_priv->adec + ADEC_NUM * i;  in rpmsg_cb()
772 		config = priv->adec[CONF + i * ADEC_NUM];  in init_versalnet()