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/linux/drivers/gpu/drm/tegra/
H A Dmipi-phy.c16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
24 timing->clktermen = 0; in mipi_dphy_timing_get_default()
25 timing->clktrail = 80; in mipi_dphy_timing_get_default()
26 timing->clkzero = 260; in mipi_dphy_timing_get_default()
27 timing->dtermen = 0; in mipi_dphy_timing_get_default()
[all …]
/linux/drivers/clk/tegra/
H A Dclk-tegra124-emc.c48 * When we change the timing to a timing with a parent that has the same
50 * timing that has a different clock source.
120 struct emc_timing *timing = NULL; in emc_determine_rate() local
136 timing = tegra->timings + i; in emc_determine_rate()
138 if (timing->rate < req->rate && i != t - 1) in emc_determine_rate()
141 if (timing->rate > req->max_rate) { in emc_determine_rate()
147 if (timing->rate < req->min_rate) in emc_determine_rate()
150 req->rate = timing->rate; in emc_determine_rate()
154 if (timing) { in emc_determine_rate()
155 req->rate = timing->rate; in emc_determine_rate()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dtiming.c26 #include <subdev/bios/timing.h>
33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
51 return timing; in nvbios_timingTe()
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/linux/drivers/video/fbdev/
H A Dgbefb.c38 struct gbe_timing_info timing; member
411 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) in gbefb_setup_flatpanel() argument
417 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
419 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
427 timing->pll_m = 4; in gbefb_setup_flatpanel()
428 timing->pll_n = 1; in gbefb_setup_flatpanel()
429 timing->pll_p = 0; in gbefb_setup_flatpanel()
456 struct gbe_timing_info *timing) in compute_gbe_timing() argument
467 /* Determine valid resolution and timing in compute_gbe_timing()
503 /* set video timing information */ in compute_gbe_timing()
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.c70 const struct dc_crtc_timing *timing) in optc201_validate_timing() argument
77 ASSERT(timing != NULL); in optc201_validate_timing()
79 v_blank = (timing->v_total - timing->v_addressable - in optc201_validate_timing()
80 timing->v_border_top - timing->v_border_bottom); in optc201_validate_timing()
82 h_blank = (timing->h_total - timing->h_addressable - in optc201_validate_timing()
83 timing->h_border_right - in optc201_validate_timing()
84 timing->h_border_left); in optc201_validate_timing()
86 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && in optc201_validate_timing()
87 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && in optc201_validate_timing()
88 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && in optc201_validate_timing()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_translation_helper.c82 max_hw_v_total -= stream->timing.v_front_porch + 1; in calc_max_hardware_v_total()
88 static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cfg *timing, in populate_dml21_timing_config_from_stream_state() argument
97 …timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_… in populate_dml21_timing_config_from_stream_state()
98 …timing->v_active = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.… in populate_dml21_timing_config_from_stream_state()
99 timing->h_front_porch = stream->timing.h_front_porch; in populate_dml21_timing_config_from_stream_state()
100 timing->v_front_porch = stream->timing.v_front_porch; in populate_dml21_timing_config_from_stream_state()
101 timing->pixel_clock_khz = stream->timing.pix_clk_100hz / 10; in populate_dml21_timing_config_from_stream_state()
103 timing->pixel_clock_khz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz / 10; in populate_dml21_timing_config_from_stream_state()
104 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) in populate_dml21_timing_config_from_stream_state()
105 timing->pixel_clock_khz *= 2; in populate_dml21_timing_config_from_stream_state()
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/linux/drivers/video/fbdev/via/
H A Dvia_modesetting.c18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
27 raw.hor_sync_end = timing->hor_sync_end / 8; in via_set_primary_timing()
28 raw.ver_total = timing->ver_total - 2; in via_set_primary_timing()
29 raw.ver_addr = timing->ver_addr - 1; in via_set_primary_timing()
30 raw.ver_blank_start = timing->ver_blank_start - 1; in via_set_primary_timing()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A Ddc_dsc.c62 const struct dc_crtc_timing *timing, const uint32_t kbps) in apply_128b_132b_stream_overhead() argument
69 if (!timing->flags.DSC) { in apply_128b_132b_stream_overhead()
74 bpp = dc_fixpt_div_int(bpp, timing->pix_clk_100hz / 10); in apply_128b_132b_stream_overhead()
79 overhead_factor = dc_fixpt_from_int(timing->h_addressable); in apply_128b_132b_stream_overhead()
94 const struct dc_crtc_timing *timing, in dc_bandwidth_in_kbps_from_timing() argument
100 if (timing->flags.DSC) in dc_bandwidth_in_kbps_from_timing()
101 return dc_dsc_stream_bandwidth_in_kbps(timing, in dc_bandwidth_in_kbps_from_timing()
102 timing->dsc_cfg.bits_per_pixel, in dc_bandwidth_in_kbps_from_timing()
103 timing->dsc_cfg.num_slices_h, in dc_bandwidth_in_kbps_from_timing()
104 timing->dsc_cfg.is_dp); in dc_bandwidth_in_kbps_from_timing()
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/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_20nm.c11 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_20nm_dphy_set_timing()
17 writel(DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail), in dsi_20nm_dphy_set_timing()
19 writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare), in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
24 writel(DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), in dsi_20nm_dphy_set_timing()
26 writel(DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero), in dsi_20nm_dphy_set_timing()
28 writel(DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare), in dsi_20nm_dphy_set_timing()
30 writel(DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail), in dsi_20nm_dphy_set_timing()
32 writel(DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst), in dsi_20nm_dphy_set_timing()
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/linux/drivers/gpu/drm/sti/
H A Dsti_awg_utils.c122 struct awg_timing *timing) in awg_generate_line_signal() argument
127 if (timing->trailing_pixels > 0) { in awg_generate_line_signal()
129 val = timing->blanking_level; in awg_generate_line_signal()
132 val = timing->trailing_pixels - 1 + AWG_DELAY; in awg_generate_line_signal()
137 val = timing->blanking_level; in awg_generate_line_signal()
138 ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, in awg_generate_line_signal()
141 if (timing->blanking_pixels > 0) { in awg_generate_line_signal()
143 val = timing->active_pixels - 1; in awg_generate_line_signal()
147 val = timing->blanking_level; in awg_generate_line_signal()
156 struct awg_timing *timing) in sti_awg_generate_code_data_enable_mode() argument
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/linux/drivers/media/rc/img-ir/
H A Dimg-ir-hw.h22 /* Timing information */
53 * struct img_ir_timing_range - range of timing values
54 * @min: Minimum timing value
55 * @max: Maximum timing value (if < @min, this will be set to @min during
65 * struct img_ir_symbol_timing - timing data for a symbol
66 * @pulse: Timing range for the length of the pulse in this symbol
67 * @space: Timing range for the length of the space in this symbol
75 * struct img_ir_free_timing - timing data for free time symbol
88 * struct img_ir_timings - Timing values.
89 * @ldr: Leader symbol timing data
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramnv50.c34 #include <subdev/bios/timing.h>
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
98 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
109 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in nv50_ram_timing_calc()
110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
114 timing[2] = (T(CWL) - 1) << 24 | in nv50_ram_timing_calc()
118 timing[3] = (unkt3b - 2 + T(CL)) << 24 | in nv50_ram_timing_calc()
122 timing[4] = (cur4 & 0xffff0000) | in nv50_ram_timing_calc()
125 timing[5] = T(RFC) << 24 | in nv50_ram_timing_calc()
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/linux/drivers/ata/
H A Dpata_triflex.c62 * triflex_load_timing - timing configuration
76 u32 timing = 0; in triflex_load_timing() local
88 timing = 0x0103;break; in triflex_load_timing()
90 timing = 0x0203;break; in triflex_load_timing()
92 timing = 0x0808;break; in triflex_load_timing()
96 timing = 0x0F0F;break; in triflex_load_timing()
98 timing = 0x0202;break; in triflex_load_timing()
100 timing = 0x0204;break; in triflex_load_timing()
102 timing = 0x0404;break; in triflex_load_timing()
104 timing = 0x0508;break; in triflex_load_timing()
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H A Dpata_cmd640.c54 struct cmd640_reg *timing = ap->private_data; in cmd640_set_piomode() local
68 /* The second channel has shared timings and the setup timing is in cmd640_set_piomode()
100 /* Load setup timing */ in cmd640_set_piomode()
116 timing->reg58[adev->devno] = (t.active << 4) | t.recover; in cmd640_set_piomode()
134 struct cmd640_reg *timing = ap->private_data; in cmd640_qc_issue() local
136 if (ap->port_no != 0 && adev->devno != timing->last) { in cmd640_qc_issue()
137 pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]); in cmd640_qc_issue()
138 timing->last = adev->devno; in cmd640_qc_issue()
154 struct cmd640_reg *timing; in cmd640_port_start() local
156 timing = devm_kzalloc(&pdev->dev, sizeof(struct cmd640_reg), GFP_KERNEL); in cmd640_port_start()
[all …]
H A Dpata_sis.c314 t1 &= 0xC0C00FFF; /* Mask out timing */ in sis_133_set_piomode()
341 u16 timing; in sis_old_set_dmamode() local
346 pci_read_config_word(pdev, drive_pci, &timing); in sis_old_set_dmamode()
349 /* bits 3-0 hold recovery timing bits 8-10 active timing and in sis_old_set_dmamode()
351 timing &= ~0x870F; in sis_old_set_dmamode()
352 timing |= mwdma_bits[speed]; in sis_old_set_dmamode()
356 timing &= ~0x6000; in sis_old_set_dmamode()
357 timing |= udma_bits[speed]; in sis_old_set_dmamode()
359 pci_write_config_word(pdev, drive_pci, timing); in sis_old_set_dmamode()
380 u16 timing; in sis_66_set_dmamode() local
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/linux/Documentation/driver-api/memory-devices/
H A Dti-gpmc.rst20 GPMC generic timing calculation:
29 generic timing routine was developed to achieve above requirements.
37 happen that timing as specified by peripheral datasheet is not present
38 in timing structure, in this scenario, try to correlate peripheral
39 timing to the one available. If that doesn't work, try to add a new
40 field as required by peripheral, educate generic timing routine to
45 Generic timing routine has been verified to work properly on
48 A word of caution: generic timing routine has been developed based
50 custom timing routines, a kind of reverse engineering without
52 in mainline having custom timing routine) and by simulation.
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/linux/drivers/media/i2c/
H A Dbt819.c60 struct timing { struct
70 static struct timing timing_data[] = { argument
164 0x16, 0x07, /* 0x16 Video Timing Polarity in bt819_init()
175 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; in bt819_init() local
178 (((timing->vdelay >> 8) & 0x03) << 6) | in bt819_init()
179 (((timing->vactive >> 8) & 0x03) << 4) | in bt819_init()
180 (((timing->hdelay >> 8) & 0x03) << 2) | in bt819_init()
181 ((timing->hactive >> 8) & 0x03); in bt819_init()
182 init[0x04 * 2 - 1] = timing->vdelay & 0xff; in bt819_init()
183 init[0x05 * 2 - 1] = timing->vactive & 0xff; in bt819_init()
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dsi.c250 struct mtk_phy_timing *timing = &dsi->phy_timing; in mtk_dsi_phy_timconfig() local
252 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; in mtk_dsi_phy_timconfig()
253 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; in mtk_dsi_phy_timconfig()
254 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - in mtk_dsi_phy_timconfig()
255 timing->da_hs_prepare; in mtk_dsi_phy_timconfig()
256 timing->da_hs_trail = timing->da_hs_prepare + 1; in mtk_dsi_phy_timconfig()
258 timing->ta_go = 4 * timing->lpx - 2; in mtk_dsi_phy_timconfig()
259 timing->ta_sure = timing->lpx + 2; in mtk_dsi_phy_timconfig()
260 timing->ta_get = 4 * timing->lpx; in mtk_dsi_phy_timconfig()
261 timing->da_hs_exit = 2 * timing->lpx + 1; in mtk_dsi_phy_timconfig()
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/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.h126 /* determine if given timing can be supported by TG */
129 const struct dc_crtc_timing *timing,
134 /* Program timing generator with given timing */
139 /* Disable/Enable Timing Generator */
166 /*********** Timing Generator Synchronization routines ****/
200 /* Fully program CRTC timing in timing generator */
203 const struct dc_crtc_timing *timing);
247 const struct dc_crtc_timing *timing);
259 const struct dc_crtc_timing *timing,
274 const struct dc_crtc_timing *timing);
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/linux/arch/arm/mach-pxa/
H A Dsmemc.h21 #define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
24 #define MCMEM0 (SMEMC_VIRT + 0x28) /* Card interface Common Memory Space Socket 0 Timing */
25 #define MCMEM1 (SMEMC_VIRT + 0x2C) /* Card interface Common Memory Space Socket 1 Timing */
26 #define MCATT0 (SMEMC_VIRT + 0x30) /* Card interface Attribute Space Socket 0 Timing Configuratio…
27 #define MCATT1 (SMEMC_VIRT + 0x34) /* Card interface Attribute Space Socket 1 Timing Configuratio…
28 #define MCIO0 (SMEMC_VIRT + 0x38) /* Card interface I/O Space Socket 0 Timing Configuration */
29 #define MCIO1 (SMEMC_VIRT + 0x3C) /* Card interface I/O Space Socket 1 Timing Configuration */
44 …e MCMEM(s) (SMEMC_VIRT + 0x28 + ((s)<<2)) /* Card interface Common Memory Space Socket s Timing */
45 #define MCATT(s) (SMEMC_VIRT + 0x30 + ((s)<<2)) /* Card interface Attribute Space Socket s Timing …
46 #define MCIO(s) (SMEMC_VIRT + 0x38 + ((s)<<2)) /* Card interface I/O Space Socket s Timing Config…
/linux/Documentation/devicetree/bindings/mips/cavium/
H A Dbootbus.txt32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
34 - cavium,t-ce: A cell specifying the CE timing (in nS).
36 - cavium,t-oe: A cell specifying the OE timing (in nS).
38 - cavium,t-we: A cell specifying the WE timing (in nS).
40 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
42 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
44 - cavium,t-pause: A cell specifying the PAUSE timing (in nS).
46 - cavium,t-wait: A cell specifying the WAIT timing (in nS).
48 - cavium,t-page: A cell specifying the PAGE timing (in nS).
50 - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
/linux/drivers/gpu/drm/amd/display/modules/freesync/
H A Dfreesync.c120 * 10000) * stream->timing.h_total, in calc_duration_in_us_from_v_total()
121 stream->timing.pix_clk_100hz)); in calc_duration_in_us_from_v_total()
131 max_hw_v_total -= stream->timing.v_front_porch + 1; in calc_max_hardware_v_total()
145 return stream->timing.v_total; in mod_freesync_calc_v_total_from_refresh()
151 if (refresh_in_uhz <= stream->timing.min_refresh_in_uhz) { in mod_freesync_calc_v_total_from_refresh()
157 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), in mod_freesync_calc_v_total_from_refresh()
158 stream->timing.h_total), 1000000); in mod_freesync_calc_v_total_from_refresh()
159 } else if (refresh_in_uhz >= stream->timing.max_refresh_in_uhz) { in mod_freesync_calc_v_total_from_refresh()
165 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), in mod_freesync_calc_v_total_from_refresh()
166 stream->timing.h_total) + (1000000 - 1), 1000000); in mod_freesync_calc_v_total_from_refresh()
[all …]
/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dxlnx,v-tc.txt1 Xilinx Video Timing Controller (VTC)
4 The Video Timing Controller is a general purpose video timing generator and
13 - clocks: Must contain a clock specifier for the VTC core and timing
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/
H A Ddml2_pmo_dcn4_fams2.c740 static bool is_h_timing_divisible_by(const struct dml2_timing_cfg *timing, unsigned char denominato… in is_h_timing_divisible_by() argument
744 * in order for the horizontal timing params to be considered divisible in is_h_timing_divisible_by()
747 unsigned long h_blank_start = timing->h_total - timing->h_front_porch; in is_h_timing_divisible_by()
749 return (timing->h_total % denominator == 0) && in is_h_timing_divisible_by()
751 (timing->h_blank_end % denominator == 0) && in is_h_timing_divisible_by()
752 (timing->h_sync_width % denominator == 0); in is_h_timing_divisible_by()
808 * ODM Combine requires horizontal timing divisible by 2 so each in pmo_dcn4_fams2_init_for_vmin()
811 else if (!is_h_timing_divisible_by(&display_config->stream_descriptors[i].timing, 2)) in pmo_dcn4_fams2_init_for_vmin()
846 odm_load = display_config->stream_descriptors[i].timing.pixel_clock_khz in find_highest_odm_load_stream_index()
901 * actual pixel rate. Therefore horizontal timing must in pmo_dcn4_fams2_optimize_for_vmin()
[all …]
/linux/drivers/memory/samsung/
H A Dexynos-srom.c71 u32 timing[6]; in exynos_srom_configure_bank() local
80 if (of_property_read_u32_array(np, "samsung,srom-timing", timing, in exynos_srom_configure_bank()
81 ARRAY_SIZE(timing))) in exynos_srom_configure_bank()
94 writel_relaxed(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) | in exynos_srom_configure_bank()
95 (timing[1] << EXYNOS_SROM_BCX__TCAH__SHIFT) | in exynos_srom_configure_bank()
96 (timing[2] << EXYNOS_SROM_BCX__TCOH__SHIFT) | in exynos_srom_configure_bank()
97 (timing[3] << EXYNOS_SROM_BCX__TACC__SHIFT) | in exynos_srom_configure_bank()
98 (timing[4] << EXYNOS_SROM_BCX__TCOS__SHIFT) | in exynos_srom_configure_bank()
99 (timing[5] << EXYNOS_SROM_BCX__TACS__SHIFT), in exynos_srom_configure_bank()

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