Searched full:tegra210_clk_pll_p (Results 1 – 4 of 4) sorted by relevance
/linux/Documentation/devicetree/bindings/display/tegra/ |
H A D | nvidia,tegra20-vi.yaml | 205 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 206 <&tegra_car TEGRA210_CLK_PLL_P>, 207 <&tegra_car TEGRA210_CLK_PLL_P>;
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H A D | nvidia,tegra20-host1x.yaml | 424 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 425 <&tegra_car TEGRA210_CLK_PLL_P>, 426 <&tegra_car TEGRA210_CLK_PLL_P>;
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/linux/drivers/clk/tegra/ |
H A D | clk-tegra210.c | 2453 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true }, 2571 { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P }, 3548 { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 }, 3549 { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 }, 3550 { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 }, 3551 { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 }, 3559 { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 }, 3560 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 }, 3562 { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 }, 3563 { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 }, [all …]
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/linux/include/dt-bindings/clock/ |
H A D | tegra210-car.h | 274 #define TEGRA210_CLK_PLL_P 243 macro
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