Lines Matching full:tegra210_clk_pll_p
2453 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },
2571 { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P },
3548 { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 },
3549 { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
3550 { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
3551 { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
3559 { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 },
3560 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
3562 { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 },
3563 { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
3564 { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
3574 { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 },
3575 { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 },
3581 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
3582 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
3583 { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 },
3584 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },
3585 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },
3586 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },
3588 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
3598 { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
3599 { TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },
3600 { TEGRA210_CLK_PWM, TEGRA210_CLK_PLL_P, 48000000, 0 },