| /linux/drivers/power/supply/ |
| H A D | da9150-fg.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DA9150 Fuel-Gauge Driver
22 #include <linux/devm-helpers.h>
84 int soc; member
99 da9150_read_qif(fg->da9150, read_addr, size, buf); in da9150_fg_read_attr()
121 da9150_write_qif(fg->da9150, write_addr, size, buf); in da9150_fg_write_attr()
130 mutex_lock(&fg->io_lock); in da9150_fg_read_sync_start()
150 dev_err(fg->dev, "Failed to perform QIF read sync!\n"); in da9150_fg_read_sync_start()
159 mutex_unlock(&fg->io_lock); in da9150_fg_read_sync_end()
181 mutex_lock(&fg->io_lock); in da9150_fg_write_attr_sync()
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| H A D | max17040_battery.c | 1 // SPDX-License-Identifier: GPL-2.0
4 // fuel-gauge systems for lithium-ion (Li+) batteries
149 int soc; member
160 return regmap_write(chip->regmap, MAX17040_CMD, chip->data.reset_val); in max17040_reset()
163 static int max17040_set_low_soc_alert(struct max17040_chip *chip, u32 level) in max17040_set_low_soc_alert() argument
165 level = 32 - level * (chip->quirk_double_soc ? 2 : 1); in max17040_set_low_soc_alert()
166 return regmap_update_bits(chip->regmap, MAX17040_CONFIG, in max17040_set_low_soc_alert()
167 MAX17040_ATHD_MASK, level); in max17040_set_low_soc_alert()
172 return regmap_update_bits(chip->regmap, MAX17040_CONFIG, in max17040_set_soc_alert()
178 u16 mask = chip->data.rcomp_bytes == 2 ? in max17040_set_rcomp()
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| /linux/Documentation/devicetree/bindings/power/supply/ |
| H A D | maxim,max17040.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
13 - $ref: power-supply.yaml#
18 - maxim,max17040
19 - maxim,max17041
20 - maxim,max17043
21 - maxim,max17044
22 - maxim,max17048
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| H A D | dlg,da9150-fuel-gauge.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/supply/dlg,da9150-fuel-gauge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Dialog Semiconductor DA9150 Fuel-Gauge Power Supply
10 - Sebastian Reichel <sre@kernel.org>
13 - $ref: power-supply.yaml#
17 const: dlg,da9150-fuel-gauge
19 dlg,update-interval:
21 description: Interval time (milliseconds) between battery level checks.
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| /linux/arch/arm/mach-omap2/ |
| H A D | cm_common.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 * cm_ll_data: function pointers to SoC-specific implementations of
41 * cm_split_idlest_reg - split CM_IDLEST reg addr into its components
48 * via the @prcm_inst and @idlest_reg_id. Returns -EINVAL upon error,
56 if (!cm_ll_data->split_idlest_reg) { in cm_split_idlest_reg()
57 WARN_ONCE(1, "cm: %s: no low-level function defined\n", in cm_split_idlest_reg()
59 return -EINVAL; in cm_split_idlest_reg()
62 ret = cm_ll_data->split_idlest_reg(idlest_reg, prcm_inst, in cm_split_idlest_reg()
64 *prcm_inst -= cm_base.offset; in cm_split_idlest_reg()
69 * omap_cm_wait_module_ready - wait for a module to leave idle or standby
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| H A D | prm_common.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Tero Kristo <t-kristo@ti.com>
24 #include <linux/clk-provider.h>
27 #include "soc.h"
45 * actual amount of memory needed for the SoC
76 * prm_ll_data: function pointers to SoC-specific implementations of
92 for (i = 0; i < prcm_irq_setup->nr_regs; i++) { in omap_prcm_events_filter_priority()
94 events[i] & prcm_irq_setup->priority_mask[i]; in omap_prcm_events_filter_priority()
105 * done by the SoC specific individual handlers.
113 int nr_irq = prcm_irq_setup->nr_regs * 32; in omap_prcm_irq_handler()
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| H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap2/clock.c
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
21 #include <linux/clk-provider.h>
29 #include "soc.h"
35 #include "cm-regbits-24xx.h"
36 #include "cm-regbits-34xx.h"
39 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | sprd,pinctrl.txt | 8 pad driving level, system control select and so on ("domain pad
9 driving level": One pin can output 3.0v or 1.8v, depending on the
13 have several systems (AP/CP/CM4) on one SoC.).
16 of them, so we can not make every Spreadtrum-special configuration
32 Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
35 - input-enable
36 - input-disable
37 - output-high
38 - output-low
39 - bias-pull-up
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| /linux/sound/soc/sof/intel/ |
| H A D | telemetry.c | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
12 #include "../ipc4-priv.h"
13 #include "../sof-priv.h"
24 char *level; in sof_ipc4_intel_dump_telemetry_state() local
26 level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; in sof_ipc4_intel_dump_telemetry_state()
36 if (telemetry_data->separator != XTENSA_CORE_DUMP_SEPARATOR) { in sof_ipc4_intel_dump_telemetry_state()
37 dev_err(sdev->dev, "%s invalid separator %#x\n", invalid_slot_msg, in sof_ipc4_intel_dump_telemetry_state()
38 telemetry_data->separator); in sof_ipc4_intel_dump_telemetry_state()
47 if (block->soc != XTENSA_SOC_INTEL_ADSP) { in sof_ipc4_intel_dump_telemetry_state()
48 dev_err(sdev->dev, "%s invalid SOC %d\n", invalid_slot_msg, block->soc); in sof_ipc4_intel_dump_telemetry_state()
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| /linux/arch/arm/mach-at91/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
18 bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
22 Select this if you are using an SoC from Microchip's SAME7, SAMS7 or SAMV7
38 Select this if ou are using one of Microchip's SAMA5D2 family SoC.
49 Select this if you are using one of Microchip's SAMA5D3 family SoC.
63 Select this if you are using one of Microchip's SAMA5D4 family SoC.
74 Select this if you are using one of Microchip's SAMA7D65 family SoC.
85 Select this if you are using one of Microchip's SAMA7G5 family SoC.
88 bool "ARMv7 based Microchip LAN966 SoC family"
94 This enables support for ARMv7 based Microchip LAN966 SoC family.
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 2 * Copyright 2019-2021 Advanced Micro Devices, Inc.
121 /*TODO: correct dispclk/dppclk voltage level determination*/
365 /*TODO: correct dispclk/dppclk voltage level determination*/
458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
460 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
461 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()
471 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
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| /linux/Documentation/driver-api/firmware/ |
| H A D | other_interfaces.rst | 5 --------------
7 .. kernel-doc:: drivers/firmware/dmi_scan.c
11 --------------
13 .. kernel-doc:: drivers/firmware/edd.c
17 -------------------------------------
19 .. kernel-doc:: drivers/firmware/sysfb.c
22 Intel Stratix10 SoC Service Layer
23 ---------------------------------
24 Some features of the Intel Stratix10 SoC require a level of privilege
27 at Exception Level 1 (EL1), access to the features requires
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| /linux/sound/soc/sof/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
21 For backwards-compatibility with previous configurations the selection will
22 be used as default for platform-specific drivers.
32 For backwards-compatibility with previous configurations the selection will
33 be used as default for platform-specific drivers.
62 This option is not user-selectable but automagically handled by
63 'select' statements at a higher level.
69 This option is not user-selectable but automagically handled by
70 'select' statements at a higher level.
121 during topology creation or run-time usage if new functionality
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | mpc5121-psc.txt | 4 ----------------
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
16 Supported <soc>s: mpc5121, mpc5125
17 - reg : Offset and length of the register set for the PSC device
18 - interrupts : <a b> where a is the interrupt number of the
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| H A D | mpc5200.txt | 2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
18 chip? For the MPC5200; the answer is easy. Most of the SoC devices
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
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| /linux/arch/powerpc/boot/dts/fsl/ |
| H A D | t104xsi-pre.dtsi | 2 * T1040/T1042 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2013-2014 Freescale Semiconductor Inc.
35 /dts-v1/;
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
45 ccsr = &soc;
71 #address-cells = <1>;
72 #size-cells = <0>;
78 next-level-cache = <&L2_1>;
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| H A D | p4080si-pre.dtsi | 2 * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
46 ccsr = &soc;
91 #address-cells = <1>;
92 #size-cells = <0>;
98 next-level-cache = <&L2_0>;
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| H A D | p3041si-pre.dtsi | 2 * P3041 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
46 ccsr = &soc;
87 #address-cells = <1>;
88 #size-cells = <0>;
94 next-level-cache = <&L2_0>;
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| H A D | p2041si-pre.dtsi | 2 * P2041 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
46 ccsr = &soc;
86 #address-cells = <1>;
87 #size-cells = <0>;
93 next-level-cache = <&L2_0>;
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| H A D | p5040si-pre.dtsi | 2 * P5040 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
46 ccsr = &soc;
99 #address-cells = <1>;
100 #size-cells = <0>;
106 next-level-cache = <&L2_0>;
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| H A D | t102xsi-pre.dtsi | 2 * T1024/T1023 Silicon/SoC Device Tree Source (pre include)
35 /dts-v1/;
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
45 ccsr = &soc;
71 #address-cells = <1>;
72 #size-cells = <0>;
78 next-level-cache = <&L2_1>;
79 #cooling-cells = <2>;
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| /linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6q.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
24 operating-points = <
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
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| /linux/drivers/pinctrl/intel/ |
| H A D | Kconfig.tng | 1 # SPDX-License-Identifier: GPL-2.0-only
15 If built as a module its name will be pinctrl-tangier.
21 Intel Merrifield Family-Level Interface Shim (FLIS) driver provides
22 an interface that allows configuring of SoC pins and using them as
29 Intel Moorefield Family-Level Interface Shim (FLIS) driver provides
30 an interface that allows configuring of SoC pins and using them as
|
| /linux/arch/arm64/boot/dts/apple/ |
| H A D | t6002.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Apple T6002 "M1 Ultra" SoC
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
16 #include "multi-die-cpp.h"
18 #include "t600x-common.dtsi"
21 compatible = "apple,t6002", "apple,arm-platform";
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | chipidea,usb2-imx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
15 - enum:
16 - fsl,imx27-usb
17 - items:
18 - enum:
19 - fsl,imx23-usb
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